Lines Matching +full:0 +full:x720
24 #define HDA_ANA_CFG 0x0000
25 #define HDA_ANA_SCALE_CTRL_Y 0x0004
26 #define HDA_ANA_SCALE_CTRL_CB 0x0008
27 #define HDA_ANA_SCALE_CTRL_CR 0x000C
28 #define HDA_ANA_ANC_CTRL 0x0010
29 #define HDA_ANA_SRC_Y_CFG 0x0014
30 #define HDA_COEFF_Y_PH1_TAP123 0x0018
31 #define HDA_COEFF_Y_PH1_TAP456 0x001C
32 #define HDA_COEFF_Y_PH2_TAP123 0x0020
33 #define HDA_COEFF_Y_PH2_TAP456 0x0024
34 #define HDA_COEFF_Y_PH3_TAP123 0x0028
35 #define HDA_COEFF_Y_PH3_TAP456 0x002C
36 #define HDA_COEFF_Y_PH4_TAP123 0x0030
37 #define HDA_COEFF_Y_PH4_TAP456 0x0034
38 #define HDA_ANA_SRC_C_CFG 0x0040
39 #define HDA_COEFF_C_PH1_TAP123 0x0044
40 #define HDA_COEFF_C_PH1_TAP456 0x0048
41 #define HDA_COEFF_C_PH2_TAP123 0x004C
42 #define HDA_COEFF_C_PH2_TAP456 0x0050
43 #define HDA_COEFF_C_PH3_TAP123 0x0054
44 #define HDA_COEFF_C_PH3_TAP456 0x0058
45 #define HDA_COEFF_C_PH4_TAP123 0x005C
46 #define HDA_COEFF_C_PH4_TAP456 0x0060
47 #define HDA_SYNC_AWGI 0x0300
50 #define CFG_AWG_ASYNC_EN BIT(0)
55 #define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT)
56 #define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT)
62 #define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
63 #define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */
66 #define SCALE_CTRL_Y_DFLT 0x00C50256
67 #define SCALE_CTRL_CB_DFLT 0x00DB0249
68 #define SCALE_CTRL_CR_DFLT 0x00DB0249
75 #define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000
77 0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
78 0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
81 #define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004
83 0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
84 0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
88 #define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005
89 #define HDA_ANA_SRC_C_CFG_4X 0x01ED0004
91 0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
92 0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
100 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
101 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
102 0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
103 0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
104 0x00000104, 0x00001AE8
111 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
112 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
113 0x00000C44, 0x00000104, 0x00001804, 0x00000971,
114 0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
115 0x00000104, 0x00001AE8
122 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
123 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
124 0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
125 0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
126 0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
127 0x00001C52
134 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
135 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
136 0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
137 0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
138 0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
139 0x00001C52
146 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
147 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
148 0x00000E50, 0x00000104, 0x00001804, 0x00000971,
149 0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
150 0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
151 0x00001C52
158 0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
159 0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
185 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
190 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
195 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
200 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
205 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
209 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
210 1430, 1650, 0, 720, 725, 730, 750, 0,
214 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
215 1430, 1650, 0, 720, 725, 730, 750, 0,
219 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
220 1760, 1980, 0, 720, 725, 730, 750, 0,
225 798, 858, 0, 480, 489, 495, 525, 0,
230 798, 858, 0, 480, 489, 495, 525, 0,
287 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) in hda_get_mode_idx()
316 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
330 for (i = 0; i < AWG_MAX_INST; i++) { in hda_dbg_awg_microcode()
331 if (i % 8 == 0) in hda_dbg_awg_microcode()
341 seq_printf(s, "\n\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); in hda_dbg_video_dacs_ctrl()
351 seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs); in hda_dbg_show()
364 return 0; in hda_dbg_show()
368 { "hda", hda_dbg_show, 0, NULL },
375 for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++) in hda_debugfs_init()
396 for (i = 0; i < nb; i++) in sti_hda_configure_awg()
399 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4); in sti_hda_configure_awg()
416 hda_write(hda, 0, HDA_ANA_ANC_CTRL); in sti_hda_disable()
491 for (i = 0; i < SAMPLER_COEF_NB; i++) { in sti_hda_pre_enable()
497 val = 0; in sti_hda_pre_enable()
499 0 : CFG_AWG_ASYNC_VSYNC_MTD; in sti_hda_pre_enable()
550 if (ret < 0) in sti_hda_set_mode()
556 if (ret < 0) in sti_hda_set_mode()
577 int count = 0; in sti_hda_connector_get_modes()
584 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) { in sti_hda_connector_get_modes()
592 if (i == 0) in sti_hda_connector_get_modes()
649 return 0; in sti_hda_late_register()
702 drm_bridge_attach(encoder, bridge, NULL, 0); in sti_hda_bind()
724 return 0; in sti_hda_bind()