Lines Matching +full:dte +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
14 #include <linux/pci-ats.h>
19 #include <linux/dma-map-ops.h>
20 #include <linux/dma-direct.h>
21 #include <linux/iommu-helper.h>
23 #include <linux/amd-iommu.h>
30 #include <linux/io-pgtable.h>
42 #include "../dma-iommu.h"
45 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
70 int amd_iommu_max_glx_val = -1;
97 return -ENODEV; in get_acpihid_device_id()
100 if (acpi_dev_hid_uid_match(adev, p->hid, in get_acpihid_device_id()
101 p->uid[0] ? p->uid : NULL)) { in get_acpihid_device_id()
104 return p->devid; in get_acpihid_device_id()
107 return -EINVAL; in get_acpihid_device_id()
125 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in get_dev_table()
128 dev_table = pci_seg->dev_table; in get_dev_table()
141 seg = pci_domain_nr(pdev->bus); in get_device_segment()
154 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in amd_iommu_set_rlookup_table()
156 pci_seg->rlookup_table[devid] = iommu; in amd_iommu_set_rlookup_table()
164 if (pci_seg->id == seg) in __rlookup_amd_iommu()
165 return pci_seg->rlookup_table[devid]; in __rlookup_amd_iommu()
188 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in alloc_dev_data()
194 spin_lock_init(&dev_data->lock); in alloc_dev_data()
195 dev_data->devid = devid; in alloc_dev_data()
196 ratelimit_default_init(&dev_data->rs); in alloc_dev_data()
198 llist_add(&dev_data->dev_data_list, &pci_seg->dev_data_list); in alloc_dev_data()
206 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in search_dev_data()
208 if (llist_empty(&pci_seg->dev_data_list)) in search_dev_data()
211 node = pci_seg->dev_data_list.first; in search_dev_data()
213 if (dev_data->devid == devid) in search_dev_data()
229 iommu = rlookup_amd_iommu(&pdev->dev); in clone_alias()
255 clone_alias(pdev, iommu->pci_seg->alias_table[pci_dev_id(pdev)], NULL); in clone_aliases()
263 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in setup_aliases()
274 ivrs_alias = pci_seg->alias_table[pci_dev_id(pdev)]; in setup_aliases()
276 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) in setup_aliases()
294 dev_data->defer_attach = true; in find_dev_data()
313 if ((devid == p->devid) && p->group) in acpihid_device_group()
314 entry->group = p->group; in acpihid_device_group()
317 if (!entry->group) in acpihid_device_group()
318 entry->group = generic_device_group(dev); in acpihid_device_group()
320 iommu_group_ref_get(entry->group); in acpihid_device_group()
322 return entry->group; in acpihid_device_group()
368 pci_seg = iommu->pci_seg; in check_device()
369 if (devid > pci_seg->last_bdf) in check_device()
390 return -ENOMEM; in iommu_init_device()
392 dev_data->dev = dev; in iommu_init_device()
396 * By default we use passthrough mode for IOMMUv2 capable device. in iommu_init_device()
399 * it'll be forced to go into translation mode. in iommu_init_device()
403 dev_data->iommu_v2 = iommu->is_iommu_v2; in iommu_init_device()
413 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in iommu_ignore_device()
422 pci_seg->rlookup_table[devid] = NULL; in iommu_ignore_device()
436 if (dev_data->domain) in amd_iommu_uninit_device()
443 * device is re-plugged - not doing so would introduce a ton of races. in amd_iommu_uninit_device()
459 pr_err("DTE[%d]: %016llx\n", i, dev_table[devid].data[i]); in dump_dte_entry()
468 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]); in dump_command()
483 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), in amd_iommu_report_rmp_hw_error()
486 dev_data = dev_iommu_priv_get(&pdev->dev); in amd_iommu_report_rmp_hw_error()
489 if (__ratelimit(&dev_data->rs)) { in amd_iommu_report_rmp_hw_error()
495 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in amd_iommu_report_rmp_hw_error()
516 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), in amd_iommu_report_rmp_fault()
519 dev_data = dev_iommu_priv_get(&pdev->dev); in amd_iommu_report_rmp_fault()
522 if (__ratelimit(&dev_data->rs)) { in amd_iommu_report_rmp_fault()
528 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in amd_iommu_report_rmp_fault()
549 pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid), in amd_iommu_report_page_fault()
552 dev_data = dev_iommu_priv_get(&pdev->dev); in amd_iommu_report_page_fault()
562 if (dev_data->domain == NULL) { in amd_iommu_report_page_fault()
565 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), in amd_iommu_report_page_fault()
570 if (!report_iommu_fault(&dev_data->domain->domain, in amd_iommu_report_page_fault()
571 &pdev->dev, address, in amd_iommu_report_page_fault()
578 if (__ratelimit(&dev_data->rs)) { in amd_iommu_report_page_fault()
584 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in amd_iommu_report_page_fault()
595 struct device *dev = iommu->iommu.dev; in iommu_print_event()
628 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
635 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
640 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
653 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
658 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
671 iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), in iommu_print_event()
693 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_poll_events()
694 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_poll_events()
697 iommu_print_event(iommu, iommu->evt_buf + head); in iommu_poll_events()
701 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_poll_events()
715 fault.sbdf = PCI_SEG_DEVID_TO_SBDF(iommu->pci_seg->id, PPR_DEVID(raw[0])); in iommu_handle_ppr_entry()
726 if (iommu->ppr_log == NULL) in iommu_poll_ppr_log()
729 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_poll_ppr_log()
730 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_poll_ppr_log()
737 raw = (u64 *)(iommu->ppr_log + head); in iommu_poll_ppr_log()
750 /* Avoid memcpy function-call overhead */ in iommu_poll_ppr_log()
763 /* Update head pointer of hardware ring-buffer */ in iommu_poll_ppr_log()
765 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_poll_ppr_log()
770 /* Refresh ring-buffer information */ in iommu_poll_ppr_log()
771 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_poll_ppr_log()
772 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_poll_ppr_log()
784 * Ensure all in-flight IRQ handlers run to completion before returning in amd_iommu_register_ga_log_notifier()
799 if (iommu->ga_log == NULL) in iommu_poll_ga_log()
802 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_poll_ga_log()
803 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_poll_ga_log()
809 raw = (u64 *)(iommu->ga_log + head); in iommu_poll_ga_log()
811 /* Avoid memcpy function-call overhead */ in iommu_poll_ga_log()
814 /* Update head pointer of hardware ring-buffer */ in iommu_poll_ga_log()
816 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_poll_ga_log()
844 dev_set_msi_domain(dev, iommu->ir_domain); in amd_iommu_set_pci_msi_domain()
858 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_handle_irq()
863 writel(mask, iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_handle_irq()
867 iommu->index, evt_type); in amd_iommu_handle_irq()
876 * When re-enabling interrupt (by writing 1 in amd_iommu_handle_irq()
885 * again and re-clear the bits in amd_iommu_handle_irq()
887 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_handle_irq()
944 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) { in wait_on_sem()
950 pr_alert("Completion-Wait loop timed out\n"); in wait_on_sem()
951 return -EIO; in wait_on_sem()
964 tail = iommu->cmd_buf_tail; in copy_cmd_to_buffer()
965 target = iommu->cmd_buf + tail; in copy_cmd_to_buffer()
969 iommu->cmd_buf_tail = tail; in copy_cmd_to_buffer()
972 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in copy_cmd_to_buffer()
979 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem); in build_completion_wait()
982 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; in build_completion_wait()
983 cmd->data[1] = upper_32_bits(paddr); in build_completion_wait()
984 cmd->data[2] = lower_32_bits(data); in build_completion_wait()
985 cmd->data[3] = upper_32_bits(data); in build_completion_wait()
992 cmd->data[0] = devid; in build_inv_dte()
1009 end = address + size - 1; in build_inv_address()
1015 msb_diff = fls64(end ^ address) - 1; in build_inv_address()
1025 * The msb-bit must be clear on the address. Just set all the in build_inv_address()
1028 address |= (1ull << msb_diff) - 1; in build_inv_address()
1034 /* Set the size bit - we flush more than one 4kb page */ in build_inv_address()
1044 cmd->data[1] |= domid; in build_inv_iommu_pages()
1045 cmd->data[2] = lower_32_bits(inv_address); in build_inv_iommu_pages()
1046 cmd->data[3] = upper_32_bits(inv_address); in build_inv_iommu_pages()
1048 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ in build_inv_iommu_pages()
1049 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; in build_inv_iommu_pages()
1058 cmd->data[0] = devid; in build_inv_iotlb_pages()
1059 cmd->data[0] |= (qdep & 0xff) << 24; in build_inv_iotlb_pages()
1060 cmd->data[1] = devid; in build_inv_iotlb_pages()
1061 cmd->data[2] = lower_32_bits(inv_address); in build_inv_iotlb_pages()
1062 cmd->data[3] = upper_32_bits(inv_address); in build_inv_iotlb_pages()
1073 cmd->data[0] = pasid; in build_inv_iommu_pasid()
1074 cmd->data[1] = domid; in build_inv_iommu_pasid()
1075 cmd->data[2] = lower_32_bits(address); in build_inv_iommu_pasid()
1076 cmd->data[3] = upper_32_bits(address); in build_inv_iommu_pasid()
1077 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; in build_inv_iommu_pasid()
1078 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; in build_inv_iommu_pasid()
1080 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; in build_inv_iommu_pasid()
1091 cmd->data[0] = devid; in build_inv_iotlb_pasid()
1092 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; in build_inv_iotlb_pasid()
1093 cmd->data[0] |= (qdep & 0xff) << 24; in build_inv_iotlb_pasid()
1094 cmd->data[1] = devid; in build_inv_iotlb_pasid()
1095 cmd->data[1] |= (pasid & 0xff) << 16; in build_inv_iotlb_pasid()
1096 cmd->data[2] = lower_32_bits(address); in build_inv_iotlb_pasid()
1097 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; in build_inv_iotlb_pasid()
1098 cmd->data[3] = upper_32_bits(address); in build_inv_iotlb_pasid()
1100 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; in build_inv_iotlb_pasid()
1109 cmd->data[0] = devid; in build_complete_ppr()
1111 cmd->data[1] = pasid; in build_complete_ppr()
1112 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; in build_complete_ppr()
1114 cmd->data[3] = tag & 0x1ff; in build_complete_ppr()
1115 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; in build_complete_ppr()
1129 cmd->data[0] = devid; in build_inv_irt()
1144 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; in __iommu_queue_command_sync()
1146 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; in __iommu_queue_command_sync()
1153 return -EIO; in __iommu_queue_command_sync()
1160 iommu->cmd_buf_head = readl(iommu->mmio_base + in __iommu_queue_command_sync()
1169 iommu->need_sync = sync; in __iommu_queue_command_sync()
1181 raw_spin_lock_irqsave(&iommu->lock, flags); in iommu_queue_command_sync()
1183 raw_spin_unlock_irqrestore(&iommu->lock, flags); in iommu_queue_command_sync()
1204 if (!iommu->need_sync) in iommu_completion_wait()
1207 data = atomic64_add_return(1, &iommu->cmd_sem_val); in iommu_completion_wait()
1210 raw_spin_lock_irqsave(&iommu->lock, flags); in iommu_completion_wait()
1219 raw_spin_unlock_irqrestore(&iommu->lock, flags); in iommu_completion_wait()
1236 u16 last_bdf = iommu->pci_seg->last_bdf; in amd_iommu_flush_dte_all()
1251 u16 last_bdf = iommu->pci_seg->last_bdf; in amd_iommu_flush_tlb_all()
1296 u16 last_bdf = iommu->pci_seg->last_bdf; in amd_iommu_flush_irt_all()
1298 if (iommu->irtcachedis_enabled) in amd_iommu_flush_irt_all()
1319 * Command send function for flushing on-device TLB
1328 qdep = dev_data->ats.qdep; in device_flush_iotlb()
1329 iommu = rlookup_amd_iommu(dev_data->dev); in device_flush_iotlb()
1331 return -EINVAL; in device_flush_iotlb()
1333 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); in device_flush_iotlb()
1356 iommu = rlookup_amd_iommu(dev_data->dev); in device_flush_dte()
1358 return -EINVAL; in device_flush_dte()
1360 if (dev_is_pci(dev_data->dev)) in device_flush_dte()
1361 pdev = to_pci_dev(dev_data->dev); in device_flush_dte()
1367 ret = iommu_flush_dte(iommu, dev_data->devid); in device_flush_dte()
1371 pci_seg = iommu->pci_seg; in device_flush_dte()
1372 alias = pci_seg->alias_table[dev_data->devid]; in device_flush_dte()
1373 if (alias != dev_data->devid) { in device_flush_dte()
1379 if (dev_data->ats.enabled) in device_flush_dte()
1397 build_inv_iommu_pages(&cmd, address, size, domain->id, pde); in __domain_flush_pages()
1400 if (!domain->dev_iommu[i]) in __domain_flush_pages()
1410 list_for_each_entry(dev_data, &domain->dev_list, list) { in __domain_flush_pages()
1412 if (!dev_data->ats.enabled) in __domain_flush_pages()
1446 * size is always non-zero, but address might be zero, causing in domain_flush_pages()
1449 * of the address on x86-32, cast to long when doing the check. in domain_flush_pages()
1460 size -= flush_size; in domain_flush_pages()
1464 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1475 if (domain && !domain->dev_iommu[i]) in amd_iommu_domain_flush_complete()
1493 spin_lock_irqsave(&domain->lock, flags); in domain_flush_np_cache()
1496 spin_unlock_irqrestore(&domain->lock, flags); in domain_flush_np_cache()
1508 list_for_each_entry(dev_data, &domain->dev_list, list) in domain_flush_devices()
1578 if (domain->glx == 2) in free_gcr3_table()
1579 free_gcr3_tbl_level2(domain->gcr3_tbl); in free_gcr3_table()
1580 else if (domain->glx == 1) in free_gcr3_table()
1581 free_gcr3_tbl_level1(domain->gcr3_tbl); in free_gcr3_table()
1583 BUG_ON(domain->glx != 0); in free_gcr3_table()
1585 free_page((unsigned long)domain->gcr3_tbl); in free_gcr3_table()
1596 if (domain->iop.mode != PAGE_MODE_NONE) in set_dte_entry()
1597 pte_root = iommu_virt_to_phys(domain->iop.root); in set_dte_entry()
1599 pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK) in set_dte_entry()
1608 if (!amd_iommu_snp_en || (domain->id != 0)) in set_dte_entry()
1621 if (domain->flags & PD_IOMMUV2_MASK) { in set_dte_entry()
1622 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); in set_dte_entry()
1623 u64 glx = domain->glx; in set_dte_entry()
1636 /* Encode GCR3 table into DTE */ in set_dte_entry()
1651 if (domain->flags & PD_GIOV_MASK) in set_dte_entry()
1656 flags |= domain->id; in set_dte_entry()
1664 * the previous kernel--if so, it needs to flush the translation cache in set_dte_entry()
1693 iommu = rlookup_amd_iommu(dev_data->dev); in do_attach()
1696 ats = dev_data->ats.enabled; in do_attach()
1699 dev_data->domain = domain; in do_attach()
1700 list_add(&dev_data->list, &domain->dev_list); in do_attach()
1703 if (domain->nid == NUMA_NO_NODE) in do_attach()
1704 domain->nid = dev_to_node(dev_data->dev); in do_attach()
1707 domain->dev_iommu[iommu->index] += 1; in do_attach()
1708 domain->dev_cnt += 1; in do_attach()
1711 set_dte_entry(iommu, dev_data->devid, domain, in do_attach()
1712 ats, dev_data->iommu_v2); in do_attach()
1713 clone_aliases(iommu, dev_data->dev); in do_attach()
1720 struct protection_domain *domain = dev_data->domain; in do_detach()
1723 iommu = rlookup_amd_iommu(dev_data->dev); in do_detach()
1728 dev_data->domain = NULL; in do_detach()
1729 list_del(&dev_data->list); in do_detach()
1730 clear_dte_entry(iommu, dev_data->devid); in do_detach()
1731 clone_aliases(iommu, dev_data->dev); in do_detach()
1733 /* Flush the DTE entry */ in do_detach()
1742 /* decrease reference counters - needs to happen after the flushes */ in do_detach()
1743 domain->dev_iommu[iommu->index] -= 1; in do_detach()
1744 domain->dev_cnt -= 1; in do_detach()
1758 /* Only allow access to user-accessible pages */ in pdev_pri_ats_enable()
1801 spin_lock_irqsave(&domain->lock, flags); in attach_device()
1805 spin_lock(&dev_data->lock); in attach_device()
1807 ret = -EBUSY; in attach_device()
1808 if (dev_data->domain != NULL) in attach_device()
1815 if (domain->flags & PD_IOMMUV2_MASK) { in attach_device()
1818 ret = -EINVAL; in attach_device()
1821 * In case of using AMD_IOMMU_V1 page table mode and the device in attach_device()
1826 def_domain->type != IOMMU_DOMAIN_IDENTITY) { in attach_device()
1830 if (dev_data->iommu_v2) { in attach_device()
1834 dev_data->ats.enabled = true; in attach_device()
1835 dev_data->ats.qdep = pci_ats_queue_depth(pdev); in attach_device()
1836 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev); in attach_device()
1840 dev_data->ats.enabled = true; in attach_device()
1841 dev_data->ats.qdep = pci_ats_queue_depth(pdev); in attach_device()
1850 * We might boot into a crash-kernel here. The crashed kernel in attach_device()
1859 spin_unlock(&dev_data->lock); in attach_device()
1861 spin_unlock_irqrestore(&domain->lock, flags); in attach_device()
1876 domain = dev_data->domain; in detach_device()
1878 spin_lock_irqsave(&domain->lock, flags); in detach_device()
1880 spin_lock(&dev_data->lock); in detach_device()
1888 if (WARN_ON(!dev_data->domain)) in detach_device()
1896 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) in detach_device()
1898 else if (dev_data->ats.enabled) in detach_device()
1901 dev_data->ats.enabled = false; in detach_device()
1904 spin_unlock(&dev_data->lock); in detach_device()
1906 spin_unlock_irqrestore(&domain->lock, flags); in detach_device()
1916 return ERR_PTR(-ENODEV); in amd_iommu_probe_device()
1920 return ERR_PTR(-ENODEV); in amd_iommu_probe_device()
1923 if (!iommu->iommu.ops) in amd_iommu_probe_device()
1924 return ERR_PTR(-ENODEV); in amd_iommu_probe_device()
1927 return &iommu->iommu; in amd_iommu_probe_device()
1931 if (ret != -ENOTSUPP) in amd_iommu_probe_device()
1932 dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); in amd_iommu_probe_device()
1937 iommu_dev = &iommu->iommu; in amd_iommu_probe_device()
1947 /* Domains are initialized for this device - have a look what we ended up with */ in amd_iommu_probe_finalize()
1985 list_for_each_entry(dev_data, &domain->dev_list, list) { in update_device_table()
1986 struct amd_iommu *iommu = rlookup_amd_iommu(dev_data->dev); in update_device_table()
1990 set_dte_entry(iommu, dev_data->devid, domain, in update_device_table()
1991 dev_data->ats.enabled, dev_data->iommu_v2); in update_device_table()
1992 clone_aliases(iommu, dev_data->dev); in update_device_table()
2027 spin_lock_irqsave(&domain->lock, flags); in cleanup_domain()
2029 while (!list_empty(&domain->dev_list)) { in cleanup_domain()
2030 entry = list_first_entry(&domain->dev_list, in cleanup_domain()
2032 BUG_ON(!entry->domain); in cleanup_domain()
2036 spin_unlock_irqrestore(&domain->lock, flags); in cleanup_domain()
2044 if (domain->iop.pgtbl_cfg.tlb) in protection_domain_free()
2045 free_io_pgtable_ops(&domain->iop.iop.ops); in protection_domain_free()
2047 if (domain->id) in protection_domain_free()
2048 domain_id_free(domain->id); in protection_domain_free()
2053 static int protection_domain_init_v1(struct protection_domain *domain, int mode) in protection_domain_init_v1() argument
2057 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL); in protection_domain_init_v1()
2059 spin_lock_init(&domain->lock); in protection_domain_init_v1()
2060 domain->id = domain_id_alloc(); in protection_domain_init_v1()
2061 if (!domain->id) in protection_domain_init_v1()
2062 return -ENOMEM; in protection_domain_init_v1()
2063 INIT_LIST_HEAD(&domain->dev_list); in protection_domain_init_v1()
2065 if (mode != PAGE_MODE_NONE) { in protection_domain_init_v1()
2068 domain_id_free(domain->id); in protection_domain_init_v1()
2069 return -ENOMEM; in protection_domain_init_v1()
2073 amd_iommu_domain_set_pgtable(domain, pt_root, mode); in protection_domain_init_v1()
2080 spin_lock_init(&domain->lock); in protection_domain_init_v2()
2081 domain->id = domain_id_alloc(); in protection_domain_init_v2()
2082 if (!domain->id) in protection_domain_init_v2()
2083 return -ENOMEM; in protection_domain_init_v2()
2084 INIT_LIST_HEAD(&domain->dev_list); in protection_domain_init_v2()
2086 domain->flags |= PD_GIOV_MASK; in protection_domain_init_v2()
2088 domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2; in protection_domain_init_v2()
2091 domain_id_free(domain->id); in protection_domain_init_v2()
2092 return -ENOMEM; in protection_domain_init_v2()
2103 int mode = DEFAULT_PGTABLE_LEVEL; in protection_domain_alloc() local
2108 * when allocating domain for pass-through devices. in protection_domain_alloc()
2112 mode = PAGE_MODE_NONE; in protection_domain_alloc()
2127 ret = protection_domain_init_v1(domain, mode); in protection_domain_alloc()
2133 ret = -EINVAL; in protection_domain_alloc()
2139 /* No need to allocate io pgtable ops in passthrough mode */ in protection_domain_alloc()
2143 domain->nid = NUMA_NO_NODE; in protection_domain_alloc()
2145 pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain); in protection_domain_alloc()
2147 domain_id_free(domain->id); in protection_domain_alloc()
2163 return ((1ULL << PM_LEVEL_SHIFT(amd_iommu_gpt_level)) - 1); in dma_max_address()
2171 * Since DTE[Mode]=0 is prohibited on SNP-enabled system, in amd_iommu_domain_alloc()
2181 domain->domain.geometry.aperture_start = 0; in amd_iommu_domain_alloc()
2182 domain->domain.geometry.aperture_end = dma_max_address(); in amd_iommu_domain_alloc()
2183 domain->domain.geometry.force_aperture = true; in amd_iommu_domain_alloc()
2185 return &domain->domain; in amd_iommu_domain_alloc()
2194 if (domain->dev_cnt > 0) in amd_iommu_domain_free()
2197 BUG_ON(domain->dev_cnt != 0); in amd_iommu_domain_free()
2202 if (domain->flags & PD_IOMMUV2_MASK) in amd_iommu_domain_free()
2220 if (dev_data->domain == domain) in amd_iommu_attach_device()
2223 dev_data->defer_attach = false; in amd_iommu_attach_device()
2225 if (dev_data->domain) in amd_iommu_attach_device()
2232 if (dom->type == IOMMU_DOMAIN_UNMANAGED) in amd_iommu_attach_device()
2233 dev_data->use_vapic = 1; in amd_iommu_attach_device()
2235 dev_data->use_vapic = 0; in amd_iommu_attach_device()
2248 struct io_pgtable_ops *ops = &domain->iop.iop.ops; in amd_iommu_iotlb_sync_map()
2250 if (ops->map_pages) in amd_iommu_iotlb_sync_map()
2259 struct io_pgtable_ops *ops = &domain->iop.iop.ops; in amd_iommu_map_pages()
2261 int ret = -EINVAL; in amd_iommu_map_pages()
2264 (domain->iop.mode == PAGE_MODE_NONE)) in amd_iommu_map_pages()
2265 return -EINVAL; in amd_iommu_map_pages()
2272 if (ops->map_pages) { in amd_iommu_map_pages()
2273 ret = ops->map_pages(ops, iova, paddr, pgsize, in amd_iommu_map_pages()
2287 * to whether "non-present cache" is on, it is probably best to prefer in amd_iommu_iotlb_gather_add_page()
2291 * the guest, and the trade-off is different: unnecessary TLB flushes in amd_iommu_iotlb_gather_add_page()
2306 struct io_pgtable_ops *ops = &domain->iop.iop.ops; in amd_iommu_unmap_pages()
2310 (domain->iop.mode == PAGE_MODE_NONE)) in amd_iommu_unmap_pages()
2313 r = (ops->unmap_pages) ? ops->unmap_pages(ops, iova, pgsize, pgcount, NULL) : 0; in amd_iommu_unmap_pages()
2325 struct io_pgtable_ops *ops = &domain->iop.iop.ops; in amd_iommu_iova_to_phys()
2327 return ops->iova_to_phys(ops, iova); in amd_iommu_iova_to_phys()
2367 pci_seg = iommu->pci_seg; in amd_iommu_get_resv_regions()
2369 list_for_each_entry(entry, &pci_seg->unity_map, list) { in amd_iommu_get_resv_regions()
2373 if (devid < entry->devid_start || devid > entry->devid_end) in amd_iommu_get_resv_regions()
2377 length = entry->address_end - entry->address_start; in amd_iommu_get_resv_regions()
2378 if (entry->prot & IOMMU_PROT_IR) in amd_iommu_get_resv_regions()
2380 if (entry->prot & IOMMU_PROT_IW) in amd_iommu_get_resv_regions()
2382 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE) in amd_iommu_get_resv_regions()
2386 region = iommu_alloc_resv_region(entry->address_start, in amd_iommu_get_resv_regions()
2390 dev_err(dev, "Out of memory allocating dm-regions\n"); in amd_iommu_get_resv_regions()
2393 list_add_tail(®ion->list, head); in amd_iommu_get_resv_regions()
2397 MSI_RANGE_END - MSI_RANGE_START + 1, in amd_iommu_get_resv_regions()
2401 list_add_tail(®ion->list, head); in amd_iommu_get_resv_regions()
2404 HT_RANGE_END - HT_RANGE_START + 1, in amd_iommu_get_resv_regions()
2408 list_add_tail(®ion->list, head); in amd_iommu_get_resv_regions()
2415 return dev_data->defer_attach; in amd_iommu_is_attach_deferred()
2424 spin_lock_irqsave(&dom->lock, flags); in amd_iommu_flush_iotlb_all()
2427 spin_unlock_irqrestore(&dom->lock, flags); in amd_iommu_flush_iotlb_all()
2436 spin_lock_irqsave(&dom->lock, flags); in amd_iommu_iotlb_sync()
2437 domain_flush_pages(dom, gather->start, gather->end - gather->start + 1, 1); in amd_iommu_iotlb_sync()
2439 spin_unlock_irqrestore(&dom->lock, flags); in amd_iommu_iotlb_sync()
2452 * - memory encryption is active, because some of those devices in amd_iommu_def_domain_type()
2453 * (AMD GPUs) don't have the encryption bit in their DMA-mask in amd_iommu_def_domain_type()
2455 * - SNP is enabled, because it prohibits DTE[Mode]=0. in amd_iommu_def_domain_type()
2457 if (dev_data->iommu_v2 && in amd_iommu_def_domain_type()
2499 * mode
2501 * In passthrough mode the IOMMU is initialized and enabled but not used for
2502 * DMA-API translation.
2524 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_domain_direct_map()
2526 if (domain->iop.pgtbl_cfg.tlb) in amd_iommu_domain_direct_map()
2527 free_io_pgtable_ops(&domain->iop.iop.ops); in amd_iommu_domain_direct_map()
2529 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_domain_direct_map()
2533 /* Note: This function expects iommu_domain->lock to be held prior calling the function. */
2539 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) in domain_enable_v2()
2543 return -EINVAL; in domain_enable_v2()
2545 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); in domain_enable_v2()
2546 if (domain->gcr3_tbl == NULL) in domain_enable_v2()
2547 return -ENOMEM; in domain_enable_v2()
2549 domain->glx = levels; in domain_enable_v2()
2550 domain->flags |= PD_IOMMUV2_MASK; in domain_enable_v2()
2563 spin_lock_irqsave(&pdom->lock, flags); in amd_iommu_domain_enable_v2()
2568 * devices attached when it is switched into IOMMUv2 mode. in amd_iommu_domain_enable_v2()
2570 ret = -EBUSY; in amd_iommu_domain_enable_v2()
2571 if (pdom->dev_cnt > 0 || pdom->flags & PD_IOMMUV2_MASK) in amd_iommu_domain_enable_v2()
2574 if (!pdom->gcr3_tbl) in amd_iommu_domain_enable_v2()
2578 spin_unlock_irqrestore(&pdom->lock, flags); in amd_iommu_domain_enable_v2()
2590 if (!(domain->flags & PD_IOMMUV2_MASK)) in __flush_pasid()
2591 return -EINVAL; in __flush_pasid()
2593 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); in __flush_pasid()
2600 if (domain->dev_iommu[i] == 0) in __flush_pasid()
2612 list_for_each_entry(dev_data, &domain->dev_list, list) { in __flush_pasid()
2617 There might be non-IOMMUv2 capable devices in an IOMMUv2 in __flush_pasid()
2620 if (!dev_data->ats.enabled) in __flush_pasid()
2623 qdep = dev_data->ats.qdep; in __flush_pasid()
2624 iommu = rlookup_amd_iommu(dev_data->dev); in __flush_pasid()
2627 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, in __flush_pasid()
2658 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_flush_page()
2660 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_flush_page()
2678 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_flush_tlb()
2680 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_flush_tlb()
2712 level -= 1; in __get_gcr3_pte()
2723 if (domain->iop.mode != PAGE_MODE_NONE) in __set_gcr3()
2724 return -EINVAL; in __set_gcr3()
2726 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); in __set_gcr3()
2728 return -ENOMEM; in __set_gcr3()
2739 if (domain->iop.mode != PAGE_MODE_NONE) in __clear_gcr3()
2740 return -EINVAL; in __clear_gcr3()
2742 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); in __clear_gcr3()
2758 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_domain_set_gcr3()
2760 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_domain_set_gcr3()
2772 spin_lock_irqsave(&domain->lock, flags); in amd_iommu_domain_clear_gcr3()
2774 spin_unlock_irqrestore(&domain->lock, flags); in amd_iommu_domain_clear_gcr3()
2787 dev_data = dev_iommu_priv_get(&pdev->dev); in amd_iommu_complete_ppr()
2788 iommu = rlookup_amd_iommu(&pdev->dev); in amd_iommu_complete_ppr()
2790 return -ENODEV; in amd_iommu_complete_ppr()
2792 build_complete_ppr(&cmd, dev_data->devid, pasid, status, in amd_iommu_complete_ppr()
2793 tag, dev_data->pri_tlp); in amd_iommu_complete_ppr()
2806 return -EINVAL; in amd_iommu_device_info()
2809 return -EINVAL; in amd_iommu_device_info()
2814 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; in amd_iommu_device_info()
2818 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; in amd_iommu_device_info()
2827 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; in amd_iommu_device_info()
2828 info->max_pasids = min(pci_max_pasids(pdev), max_pasids); in amd_iommu_device_info()
2832 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; in amd_iommu_device_info()
2834 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; in amd_iommu_device_info()
2859 if (iommu->irtcachedis_enabled) in iommu_flush_irt_and_complete()
2863 data = atomic64_add_return(1, &iommu->cmd_sem_val); in iommu_flush_irt_and_complete()
2866 raw_spin_lock_irqsave(&iommu->lock, flags); in iommu_flush_irt_and_complete()
2875 raw_spin_unlock_irqrestore(&iommu->lock, flags); in iommu_flush_irt_and_complete()
2881 u64 dte; in set_dte_irq_entry() local
2884 dte = dev_table[devid].data[2]; in set_dte_irq_entry()
2885 dte &= ~DTE_IRQ_PHYS_ADDR_MASK; in set_dte_irq_entry()
2886 dte |= iommu_virt_to_phys(table->table); in set_dte_irq_entry()
2887 dte |= DTE_IRQ_REMAP_INTCTL; in set_dte_irq_entry()
2888 dte |= DTE_INTTABLEN; in set_dte_irq_entry()
2889 dte |= DTE_IRQ_REMAP_ENABLE; in set_dte_irq_entry()
2891 dev_table[devid].data[2] = dte; in set_dte_irq_entry()
2897 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in get_irq_table()
2899 if (WARN_ONCE(!pci_seg->rlookup_table[devid], in get_irq_table()
2901 __func__, pci_seg->id, devid)) in get_irq_table()
2904 table = pci_seg->irq_lookup_table[devid]; in get_irq_table()
2906 __func__, pci_seg->id, devid)) in get_irq_table()
2920 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL); in __alloc_irq_table()
2921 if (!table->table) { in __alloc_irq_table()
2925 raw_spin_lock_init(&table->lock); in __alloc_irq_table()
2928 memset(table->table, 0, in __alloc_irq_table()
2931 memset(table->table, 0, in __alloc_irq_table()
2939 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in set_remap_table_entry()
2941 pci_seg->irq_lookup_table[devid] = table; in set_remap_table_entry()
2951 struct amd_iommu *iommu = rlookup_amd_iommu(&pdev->dev); in set_remap_table_entry_alias()
2954 return -EINVAL; in set_remap_table_entry_alias()
2956 pci_seg = iommu->pci_seg; in set_remap_table_entry_alias()
2957 pci_seg->irq_lookup_table[alias] = table; in set_remap_table_entry_alias()
2959 iommu_flush_dte(pci_seg->rlookup_table[alias], alias); in set_remap_table_entry_alias()
2975 pci_seg = iommu->pci_seg; in alloc_irq_table()
2976 table = pci_seg->irq_lookup_table[devid]; in alloc_irq_table()
2980 alias = pci_seg->alias_table[devid]; in alloc_irq_table()
2981 table = pci_seg->irq_lookup_table[alias]; in alloc_irq_table()
2995 table = pci_seg->irq_lookup_table[devid]; in alloc_irq_table()
2999 table = pci_seg->irq_lookup_table[alias]; in alloc_irq_table()
3024 kmem_cache_free(amd_iommu_irq_cache, new_table->table); in alloc_irq_table()
3039 return -ENODEV; in alloc_irq_index()
3044 raw_spin_lock_irqsave(&table->lock, flags); in alloc_irq_index()
3047 for (index = ALIGN(table->min_index, alignment), c = 0; in alloc_irq_index()
3049 if (!iommu->irte_ops->is_allocated(table, index)) { in alloc_irq_index()
3058 for (; c != 0; --c) in alloc_irq_index()
3059 iommu->irte_ops->set_allocated(table, index - c + 1); in alloc_irq_index()
3061 index -= count - 1; in alloc_irq_index()
3068 index = -ENOSPC; in alloc_irq_index()
3071 raw_spin_unlock_irqrestore(&table->lock, flags); in alloc_irq_index()
3086 return -ENOMEM; in modify_irte_ga()
3088 raw_spin_lock_irqsave(&table->lock, flags); in modify_irte_ga()
3090 entry = (struct irte_ga *)table->table; in modify_irte_ga()
3094 * We use cmpxchg16 to atomically update the 128-bit IRTE, in modify_irte_ga()
3099 old = entry->irte; in modify_irte_ga()
3100 WARN_ON(!try_cmpxchg128(&entry->irte, &old, irte->irte)); in modify_irte_ga()
3102 raw_spin_unlock_irqrestore(&table->lock, flags); in modify_irte_ga()
3117 return -ENOMEM; in modify_irte()
3119 raw_spin_lock_irqsave(&table->lock, flags); in modify_irte()
3120 table->table[index] = irte->val; in modify_irte()
3121 raw_spin_unlock_irqrestore(&table->lock, flags); in modify_irte()
3137 raw_spin_lock_irqsave(&table->lock, flags); in free_irte()
3138 iommu->irte_ops->clear_allocated(table, index); in free_irte()
3139 raw_spin_unlock_irqrestore(&table->lock, flags); in free_irte()
3150 irte->val = 0; in irte_prepare()
3151 irte->fields.vector = vector; in irte_prepare()
3152 irte->fields.int_type = delivery_mode; in irte_prepare()
3153 irte->fields.destination = dest_apicid; in irte_prepare()
3154 irte->fields.dm = dest_mode; in irte_prepare()
3155 irte->fields.valid = 1; in irte_prepare()
3164 irte->lo.val = 0; in irte_ga_prepare()
3165 irte->hi.val = 0; in irte_ga_prepare()
3166 irte->lo.fields_remap.int_type = delivery_mode; in irte_ga_prepare()
3167 irte->lo.fields_remap.dm = dest_mode; in irte_ga_prepare()
3168 irte->hi.fields.vector = vector; in irte_ga_prepare()
3169 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid); in irte_ga_prepare()
3170 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); in irte_ga_prepare()
3171 irte->lo.fields_remap.valid = 1; in irte_ga_prepare()
3178 irte->fields.valid = 1; in irte_activate()
3186 irte->lo.fields_remap.valid = 1; in irte_ga_activate()
3194 irte->fields.valid = 0; in irte_deactivate()
3202 irte->lo.fields_remap.valid = 0; in irte_ga_deactivate()
3211 irte->fields.vector = vector; in irte_set_affinity()
3212 irte->fields.destination = dest_apicid; in irte_set_affinity()
3221 if (!irte->lo.fields_remap.guest_mode) { in irte_ga_set_affinity()
3222 irte->hi.fields.vector = vector; in irte_ga_set_affinity()
3223 irte->lo.fields_remap.destination = in irte_ga_set_affinity()
3225 irte->hi.fields.destination = in irte_ga_set_affinity()
3234 table->table[index] = IRTE_ALLOCATED; in irte_set_allocated()
3239 struct irte_ga *ptr = (struct irte_ga *)table->table; in irte_ga_set_allocated()
3242 memset(&irte->lo.val, 0, sizeof(u64)); in irte_ga_set_allocated()
3243 memset(&irte->hi.val, 0, sizeof(u64)); in irte_ga_set_allocated()
3244 irte->hi.fields.vector = 0xff; in irte_ga_set_allocated()
3249 union irte *ptr = (union irte *)table->table; in irte_is_allocated()
3252 return irte->val != 0; in irte_is_allocated()
3257 struct irte_ga *ptr = (struct irte_ga *)table->table; in irte_ga_is_allocated()
3260 return irte->hi.fields.vector != 0; in irte_ga_is_allocated()
3265 table->table[index] = 0; in irte_clear_allocated()
3270 struct irte_ga *ptr = (struct irte_ga *)table->table; in irte_ga_clear_allocated()
3273 memset(&irte->lo.val, 0, sizeof(u64)); in irte_ga_clear_allocated()
3274 memset(&irte->hi.val, 0, sizeof(u64)); in irte_ga_clear_allocated()
3279 switch (info->type) { in get_devid()
3281 return get_ioapic_devid(info->devid); in get_devid()
3283 return get_hpet_devid(info->devid); in get_devid()
3286 return get_device_sbdf_id(msi_desc_to_dev(info->desc)); in get_devid()
3289 return -1; in get_devid()
3303 msg->data = index; in fill_msi_msg()
3304 msg->address_lo = 0; in fill_msi_msg()
3305 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW; in fill_msi_msg()
3306 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH; in fill_msi_msg()
3314 struct irq_2_irte *irte_info = &data->irq_2_irte; in irq_remapping_prepare_irte()
3315 struct amd_iommu *iommu = data->iommu; in irq_remapping_prepare_irte()
3320 data->irq_2_irte.devid = devid; in irq_remapping_prepare_irte()
3321 data->irq_2_irte.index = index + sub_handle; in irq_remapping_prepare_irte()
3322 iommu->irte_ops->prepare(data->entry, apic->delivery_mode, in irq_remapping_prepare_irte()
3323 apic->dest_mode_logical, irq_cfg->vector, in irq_remapping_prepare_irte()
3324 irq_cfg->dest_apicid, devid); in irq_remapping_prepare_irte()
3326 switch (info->type) { in irq_remapping_prepare_irte()
3331 fill_msi_msg(&data->msi_entry, irte_info->index); in irq_remapping_prepare_irte()
3372 return -EINVAL; in irq_remapping_alloc()
3373 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI) in irq_remapping_alloc()
3374 return -EINVAL; in irq_remapping_alloc()
3378 return -EINVAL; in irq_remapping_alloc()
3384 return -EINVAL; in irq_remapping_alloc()
3390 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { in irq_remapping_alloc()
3395 if (!table->min_index) { in irq_remapping_alloc()
3400 table->min_index = 32; in irq_remapping_alloc()
3402 iommu->irte_ops->set_allocated(table, i); in irq_remapping_alloc()
3404 WARN_ON(table->min_index != 32); in irq_remapping_alloc()
3405 index = info->ioapic.pin; in irq_remapping_alloc()
3407 index = -ENOMEM; in irq_remapping_alloc()
3409 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI || in irq_remapping_alloc()
3410 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) { in irq_remapping_alloc()
3411 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI); in irq_remapping_alloc()
3414 msi_desc_to_pci_dev(info->desc)); in irq_remapping_alloc()
3429 ret = -EINVAL; in irq_remapping_alloc()
3433 ret = -ENOMEM; in irq_remapping_alloc()
3439 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); in irq_remapping_alloc()
3441 data->entry = kzalloc(sizeof(struct irte_ga), in irq_remapping_alloc()
3443 if (!data->entry) { in irq_remapping_alloc()
3448 data->iommu = iommu; in irq_remapping_alloc()
3449 irq_data->hwirq = (devid << 16) + i; in irq_remapping_alloc()
3450 irq_data->chip_data = data; in irq_remapping_alloc()
3451 irq_data->chip = &amd_ir_chip; in irq_remapping_alloc()
3459 for (i--; i >= 0; i--) { in irq_remapping_alloc()
3462 kfree(irq_data->chip_data); in irq_remapping_alloc()
3481 if (irq_data && irq_data->chip_data) { in irq_remapping_free()
3482 data = irq_data->chip_data; in irq_remapping_free()
3483 irte_info = &data->irq_2_irte; in irq_remapping_free()
3484 free_irte(data->iommu, irte_info->devid, irte_info->index); in irq_remapping_free()
3485 kfree(data->entry); in irq_remapping_free()
3500 struct amd_ir_data *data = irq_data->chip_data; in irq_remapping_activate()
3501 struct irq_2_irte *irte_info = &data->irq_2_irte; in irq_remapping_activate()
3502 struct amd_iommu *iommu = data->iommu; in irq_remapping_activate()
3508 iommu->irte_ops->activate(iommu, data->entry, irte_info->devid, in irq_remapping_activate()
3509 irte_info->index); in irq_remapping_activate()
3517 struct amd_ir_data *data = irq_data->chip_data; in irq_remapping_deactivate()
3518 struct irq_2_irte *irte_info = &data->irq_2_irte; in irq_remapping_deactivate()
3519 struct amd_iommu *iommu = data->iommu; in irq_remapping_deactivate()
3522 iommu->irte_ops->deactivate(iommu, data->entry, irte_info->devid, in irq_remapping_deactivate()
3523 irte_info->index); in irq_remapping_deactivate()
3530 int devid = -1; in irq_remapping_select()
3536 devid = get_ioapic_devid(fwspec->param[0]); in irq_remapping_select()
3538 devid = get_hpet_devid(fwspec->param[0]); in irq_remapping_select()
3544 return iommu && iommu->ir_domain == d; in irq_remapping_select()
3558 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; in amd_iommu_activate_guest_mode()
3564 valid = entry->lo.fields_vapic.valid; in amd_iommu_activate_guest_mode()
3566 entry->lo.val = 0; in amd_iommu_activate_guest_mode()
3567 entry->hi.val = 0; in amd_iommu_activate_guest_mode()
3569 entry->lo.fields_vapic.valid = valid; in amd_iommu_activate_guest_mode()
3570 entry->lo.fields_vapic.guest_mode = 1; in amd_iommu_activate_guest_mode()
3571 entry->lo.fields_vapic.ga_log_intr = 1; in amd_iommu_activate_guest_mode()
3572 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr; in amd_iommu_activate_guest_mode()
3573 entry->hi.fields.vector = ir_data->ga_vector; in amd_iommu_activate_guest_mode()
3574 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; in amd_iommu_activate_guest_mode()
3576 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, in amd_iommu_activate_guest_mode()
3577 ir_data->irq_2_irte.index, entry); in amd_iommu_activate_guest_mode()
3584 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; in amd_iommu_deactivate_guest_mode()
3585 struct irq_cfg *cfg = ir_data->cfg; in amd_iommu_deactivate_guest_mode()
3589 !entry || !entry->lo.fields_vapic.guest_mode) in amd_iommu_deactivate_guest_mode()
3592 valid = entry->lo.fields_remap.valid; in amd_iommu_deactivate_guest_mode()
3594 entry->lo.val = 0; in amd_iommu_deactivate_guest_mode()
3595 entry->hi.val = 0; in amd_iommu_deactivate_guest_mode()
3597 entry->lo.fields_remap.valid = valid; in amd_iommu_deactivate_guest_mode()
3598 entry->lo.fields_remap.dm = apic->dest_mode_logical; in amd_iommu_deactivate_guest_mode()
3599 entry->lo.fields_remap.int_type = apic->delivery_mode; in amd_iommu_deactivate_guest_mode()
3600 entry->hi.fields.vector = cfg->vector; in amd_iommu_deactivate_guest_mode()
3601 entry->lo.fields_remap.destination = in amd_iommu_deactivate_guest_mode()
3602 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid); in amd_iommu_deactivate_guest_mode()
3603 entry->hi.fields.destination = in amd_iommu_deactivate_guest_mode()
3604 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); in amd_iommu_deactivate_guest_mode()
3606 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, in amd_iommu_deactivate_guest_mode()
3607 ir_data->irq_2_irte.index, entry); in amd_iommu_deactivate_guest_mode()
3615 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; in amd_ir_set_vcpu_affinity()
3616 struct amd_ir_data *ir_data = data->chip_data; in amd_ir_set_vcpu_affinity()
3617 struct irq_2_irte *irte_info = &ir_data->irq_2_irte; in amd_ir_set_vcpu_affinity()
3620 if (ir_data->iommu == NULL) in amd_ir_set_vcpu_affinity()
3621 return -EINVAL; in amd_ir_set_vcpu_affinity()
3623 dev_data = search_dev_data(ir_data->iommu, irte_info->devid); in amd_ir_set_vcpu_affinity()
3626 * This device has never been set up for guest mode. in amd_ir_set_vcpu_affinity()
3629 if (!dev_data || !dev_data->use_vapic) in amd_ir_set_vcpu_affinity()
3630 return -EINVAL; in amd_ir_set_vcpu_affinity()
3632 ir_data->cfg = irqd_cfg(data); in amd_ir_set_vcpu_affinity()
3633 pi_data->ir_data = ir_data; in amd_ir_set_vcpu_affinity()
3636 * SVM tries to set up for VAPIC mode, but we are in in amd_ir_set_vcpu_affinity()
3637 * legacy mode. So, we force legacy mode instead. in amd_ir_set_vcpu_affinity()
3642 pi_data->is_guest_mode = false; in amd_ir_set_vcpu_affinity()
3645 pi_data->prev_ga_tag = ir_data->cached_ga_tag; in amd_ir_set_vcpu_affinity()
3646 if (pi_data->is_guest_mode) { in amd_ir_set_vcpu_affinity()
3647 ir_data->ga_root_ptr = (pi_data->base >> 12); in amd_ir_set_vcpu_affinity()
3648 ir_data->ga_vector = vcpu_pi_info->vector; in amd_ir_set_vcpu_affinity()
3649 ir_data->ga_tag = pi_data->ga_tag; in amd_ir_set_vcpu_affinity()
3652 ir_data->cached_ga_tag = pi_data->ga_tag; in amd_ir_set_vcpu_affinity()
3661 ir_data->cached_ga_tag = 0; in amd_ir_set_vcpu_affinity()
3678 iommu->irte_ops->set_affinity(iommu, ir_data->entry, irte_info->devid, in amd_ir_update_irte()
3679 irte_info->index, cfg->vector, in amd_ir_update_irte()
3680 cfg->dest_apicid); in amd_ir_update_irte()
3686 struct amd_ir_data *ir_data = data->chip_data; in amd_ir_set_affinity()
3687 struct irq_2_irte *irte_info = &ir_data->irq_2_irte; in amd_ir_set_affinity()
3689 struct irq_data *parent = data->parent_data; in amd_ir_set_affinity()
3690 struct amd_iommu *iommu = ir_data->iommu; in amd_ir_set_affinity()
3694 return -ENODEV; in amd_ir_set_affinity()
3696 ret = parent->chip->irq_set_affinity(parent, mask, force); in amd_ir_set_affinity()
3713 struct amd_ir_data *ir_data = irq_data->chip_data; in ir_compose_msi_msg()
3715 *msg = ir_data->msi_entry; in ir_compose_msi_msg()
3719 .name = "AMD-IR",
3730 .prefix = "IR-",
3737 .prefix = "vIR-",
3745 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); in amd_iommu_create_irq_domain()
3747 return -ENOMEM; in amd_iommu_create_irq_domain()
3748 iommu->ir_domain = irq_domain_create_hierarchy(arch_get_ir_parent_domain(), 0, 0, in amd_iommu_create_irq_domain()
3750 if (!iommu->ir_domain) { in amd_iommu_create_irq_domain()
3752 return -ENOMEM; in amd_iommu_create_irq_domain()
3755 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_AMDVI); in amd_iommu_create_irq_domain()
3756 iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT | in amd_iommu_create_irq_domain()
3760 iommu->ir_domain->msi_parent_ops = &virt_amdvi_msi_parent_ops; in amd_iommu_create_irq_domain()
3762 iommu->ir_domain->msi_parent_ops = &amdvi_msi_parent_ops; in amd_iommu_create_irq_domain()
3770 struct irte_ga *entry = (struct irte_ga *) ir_data->entry; in amd_iommu_update_ga()
3773 !entry || !entry->lo.fields_vapic.guest_mode) in amd_iommu_update_ga()
3776 if (!ir_data->iommu) in amd_iommu_update_ga()
3777 return -ENODEV; in amd_iommu_update_ga()
3780 entry->lo.fields_vapic.destination = in amd_iommu_update_ga()
3782 entry->hi.fields.destination = in amd_iommu_update_ga()
3785 entry->lo.fields_vapic.is_run = is_run; in amd_iommu_update_ga()
3787 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, in amd_iommu_update_ga()
3788 ir_data->irq_2_irte.index, entry); in amd_iommu_update_ga()