Lines Matching +full:wr +full:- +full:setup
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
6 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de)
15 * sources, on which this driver (and the dvb-dibusb) are based.
17 * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
36 #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
41 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
56 { .addr = state->config.demod_address, .flags = 0, .buf = wb, .len = 2 }, in dib3000_read_reg()
57 { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 }, in dib3000_read_reg()
60 if (i2c_transfer(state->i2c, msg, 2) != 2) in dib3000_read_reg()
76 { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 } in dib3000_write_reg()
80 return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0; in dib3000_write_reg()
97 return -1; // try again in dib3000_search_status()
118 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_set_frontend()
119 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in dib3000mb_set_frontend()
123 if (tuner && fe->ops.tuner_ops.set_params) { in dib3000mb_set_frontend()
124 fe->ops.tuner_ops.set_params(fe); in dib3000mb_set_frontend()
125 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); in dib3000mb_set_frontend()
127 switch (c->bandwidth_hz) { in dib3000mb_set_frontend()
141 return -EOPNOTSUPP; in dib3000mb_set_frontend()
144 return -EINVAL; in dib3000mb_set_frontend()
146 deb_setf("bandwidth: %d MHZ\n", c->bandwidth_hz / 1000000); in dib3000mb_set_frontend()
148 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); in dib3000mb_set_frontend()
150 switch (c->transmission_mode) { in dib3000mb_set_frontend()
153 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K); in dib3000mb_set_frontend()
157 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K); in dib3000mb_set_frontend()
163 return -EINVAL; in dib3000mb_set_frontend()
166 switch (c->guard_interval) { in dib3000mb_set_frontend()
169 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32); in dib3000mb_set_frontend()
173 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16); in dib3000mb_set_frontend()
177 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8); in dib3000mb_set_frontend()
181 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4); in dib3000mb_set_frontend()
187 return -EINVAL; in dib3000mb_set_frontend()
190 switch (c->inversion) { in dib3000mb_set_frontend()
193 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF); in dib3000mb_set_frontend()
200 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON); in dib3000mb_set_frontend()
203 return -EINVAL; in dib3000mb_set_frontend()
206 switch (c->modulation) { in dib3000mb_set_frontend()
209 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK); in dib3000mb_set_frontend()
213 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM); in dib3000mb_set_frontend()
217 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM); in dib3000mb_set_frontend()
222 return -EINVAL; in dib3000mb_set_frontend()
224 switch (c->hierarchy) { in dib3000mb_set_frontend()
230 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1); in dib3000mb_set_frontend()
234 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2); in dib3000mb_set_frontend()
238 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4); in dib3000mb_set_frontend()
244 return -EINVAL; in dib3000mb_set_frontend()
247 if (c->hierarchy == HIERARCHY_NONE) { in dib3000mb_set_frontend()
248 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF); in dib3000mb_set_frontend()
249 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP); in dib3000mb_set_frontend()
250 fe_cr = c->code_rate_HP; in dib3000mb_set_frontend()
251 } else if (c->hierarchy != HIERARCHY_AUTO) { in dib3000mb_set_frontend()
252 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON); in dib3000mb_set_frontend()
253 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP); in dib3000mb_set_frontend()
254 fe_cr = c->code_rate_LP; in dib3000mb_set_frontend()
259 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2); in dib3000mb_set_frontend()
263 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3); in dib3000mb_set_frontend()
267 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4); in dib3000mb_set_frontend()
271 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6); in dib3000mb_set_frontend()
275 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8); in dib3000mb_set_frontend()
284 return -EINVAL; in dib3000mb_set_frontend()
288 [c->transmission_mode == TRANSMISSION_MODE_AUTO] in dib3000mb_set_frontend()
289 [c->guard_interval == GUARD_INTERVAL_AUTO] in dib3000mb_set_frontend()
290 [c->inversion == INVERSION_AUTO]; in dib3000mb_set_frontend()
294 wr(DIB3000MB_REG_SEQ, seq); in dib3000mb_set_frontend()
296 wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE); in dib3000mb_set_frontend()
298 if (c->transmission_mode == TRANSMISSION_MODE_2K) { in dib3000mb_set_frontend()
299 if (c->guard_interval == GUARD_INTERVAL_1_8) { in dib3000mb_set_frontend()
300 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8); in dib3000mb_set_frontend()
302 wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT); in dib3000mb_set_frontend()
305 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K); in dib3000mb_set_frontend()
307 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT); in dib3000mb_set_frontend()
310 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF); in dib3000mb_set_frontend()
311 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF); in dib3000mb_set_frontend()
312 wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF); in dib3000mb_set_frontend()
316 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE); in dib3000mb_set_frontend()
318 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL); in dib3000mb_set_frontend()
319 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); in dib3000mb_set_frontend()
327 if (c->modulation == QAM_AUTO || in dib3000mb_set_frontend()
328 c->hierarchy == HIERARCHY_AUTO || in dib3000mb_set_frontend()
330 c->inversion == INVERSION_AUTO) { in dib3000mb_set_frontend()
335 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT); in dib3000mb_set_frontend()
337 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH); in dib3000mb_set_frontend()
338 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); in dib3000mb_set_frontend()
357 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL); in dib3000mb_set_frontend()
358 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF); in dib3000mb_set_frontend()
366 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_fe_init()
369 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP); in dib3000mb_fe_init()
371 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC); in dib3000mb_fe_init()
373 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE); in dib3000mb_fe_init()
374 wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST); in dib3000mb_fe_init()
376 wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT); in dib3000mb_fe_init()
378 wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON); in dib3000mb_fe_init()
380 wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB); in dib3000mb_fe_init()
381 wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB); in dib3000mb_fe_init()
390 wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT); in dib3000mb_fe_init()
398 wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT); in dib3000mb_fe_init()
399 wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4); in dib3000mb_fe_init()
400 wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT); in dib3000mb_fe_init()
401 wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]); in dib3000mb_fe_init()
405 wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68); in dib3000mb_fe_init()
406 wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69); in dib3000mb_fe_init()
407 wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71); in dib3000mb_fe_init()
408 wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77); in dib3000mb_fe_init()
409 wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78); in dib3000mb_fe_init()
410 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT); in dib3000mb_fe_init()
411 wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92); in dib3000mb_fe_init()
412 wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96); in dib3000mb_fe_init()
413 wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97); in dib3000mb_fe_init()
414 wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106); in dib3000mb_fe_init()
415 wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107); in dib3000mb_fe_init()
416 wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108); in dib3000mb_fe_init()
417 wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122); in dib3000mb_fe_init()
418 wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF); in dib3000mb_fe_init()
419 wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT); in dib3000mb_fe_init()
423 wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON); in dib3000mb_fe_init()
424 wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB); in dib3000mb_fe_init()
425 wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB); in dib3000mb_fe_init()
427 wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE); in dib3000mb_fe_init()
429 wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142); in dib3000mb_fe_init()
430 wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188); in dib3000mb_fe_init()
431 wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE); in dib3000mb_fe_init()
432 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT); in dib3000mb_fe_init()
433 wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146); in dib3000mb_fe_init()
434 wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147); in dib3000mb_fe_init()
436 wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF); in dib3000mb_fe_init()
444 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_get_frontend()
471 c->inversion = in dib3000mb_get_frontend()
476 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, c->inversion); in dib3000mb_get_frontend()
481 c->modulation = QPSK; in dib3000mb_get_frontend()
485 c->modulation = QAM_16; in dib3000mb_get_frontend()
489 c->modulation = QAM_64; in dib3000mb_get_frontend()
499 cr = &c->code_rate_LP; in dib3000mb_get_frontend()
500 c->code_rate_HP = FEC_NONE; in dib3000mb_get_frontend()
504 c->hierarchy = HIERARCHY_NONE; in dib3000mb_get_frontend()
508 c->hierarchy = HIERARCHY_1; in dib3000mb_get_frontend()
512 c->hierarchy = HIERARCHY_2; in dib3000mb_get_frontend()
516 c->hierarchy = HIERARCHY_4; in dib3000mb_get_frontend()
527 cr = &c->code_rate_HP; in dib3000mb_get_frontend()
528 c->code_rate_LP = FEC_NONE; in dib3000mb_get_frontend()
529 c->hierarchy = HIERARCHY_NONE; in dib3000mb_get_frontend()
564 c->guard_interval = GUARD_INTERVAL_1_32; in dib3000mb_get_frontend()
568 c->guard_interval = GUARD_INTERVAL_1_16; in dib3000mb_get_frontend()
572 c->guard_interval = GUARD_INTERVAL_1_8; in dib3000mb_get_frontend()
576 c->guard_interval = GUARD_INTERVAL_1_4; in dib3000mb_get_frontend()
587 c->transmission_mode = TRANSMISSION_MODE_2K; in dib3000mb_get_frontend()
591 c->transmission_mode = TRANSMISSION_MODE_8K; in dib3000mb_get_frontend()
605 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_read_status()
637 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_read_ber()
643 /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
646 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_read_signal_strength()
654 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_read_snr()
664 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_read_unc_blocks()
672 struct dib3000_state* state = fe->demodulator_priv; in dib3000mb_sleep()
674 wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN); in dib3000mb_sleep()
680 tune->min_delay_ms = 800; in dib3000mb_fe_get_tune_settings()
696 struct dib3000_state *state = fe->demodulator_priv; in dib3000mb_release()
703 struct dib3000_state *state = fe->demodulator_priv; in dib3000mb_pid_control()
705 wr(index+DIB3000MB_REG_FIRST_PID,pid); in dib3000mb_pid_control()
711 struct dib3000_state *state = fe->demodulator_priv; in dib3000mb_fifo_control()
715 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE); in dib3000mb_fifo_control()
717 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT); in dib3000mb_fifo_control()
724 struct dib3000_state *state = fe->demodulator_priv; in dib3000mb_pid_parse()
726 wr(DIB3000MB_REG_PID_PARSE,onoff); in dib3000mb_pid_parse()
732 struct dib3000_state *state = fe->demodulator_priv; in dib3000mb_tuner_pass_ctrl()
734 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr)); in dib3000mb_tuner_pass_ctrl()
736 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr)); in dib3000mb_tuner_pass_ctrl()
753 /* setup the state */ in dib3000mb_attach()
754 state->i2c = i2c; in dib3000mb_attach()
755 memcpy(&state->config,config,sizeof(struct dib3000_config)); in dib3000mb_attach()
765 memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops)); in dib3000mb_attach()
766 state->frontend.demodulator_priv = state; in dib3000mb_attach()
769 xfer_ops->pid_parse = dib3000mb_pid_parse; in dib3000mb_attach()
770 xfer_ops->fifo_ctrl = dib3000mb_fifo_control; in dib3000mb_attach()
771 xfer_ops->pid_ctrl = dib3000mb_pid_control; in dib3000mb_attach()
772 xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl; in dib3000mb_attach()
774 return &state->frontend; in dib3000mb_attach()
784 .name = "DiBcom 3000M-B DVB-T",