Lines Matching +full:dw +full:- +full:mshc
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
19 #include "dw_mmc-pltfm.h"
20 #include "dw_mmc-exynos.h"
22 /* Variations in Exynos specific dw-mshc controller */
55 .compatible = "samsung,exynos4210-dw-mshc",
58 .compatible = "samsung,exynos4412-dw-mshc",
61 .compatible = "samsung,exynos5250-dw-mshc",
64 .compatible = "samsung,exynos5420-dw-mshc",
67 .compatible = "samsung,exynos5420-dw-mshc-smu",
70 .compatible = "samsung,exynos7-dw-mshc",
73 .compatible = "samsung,exynos7-dw-mshc-smu",
76 .compatible = "samsung,exynos7870-dw-mshc",
79 .compatible = "samsung,exynos7870-dw-mshc-smu",
82 .compatible = "axis,artpec8-dw-mshc",
89 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_get_ciu_div()
91 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) in dw_mci_exynos_get_ciu_div()
93 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) in dw_mci_exynos_get_ciu_div()
95 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_get_ciu_div()
96 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_get_ciu_div()
97 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_get_ciu_div()
98 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_get_ciu_div()
99 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_get_ciu_div()
107 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_config_smu()
111 * set for non-ecryption mode at this time. in dw_mci_exynos_config_smu()
113 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || in dw_mci_exynos_config_smu()
114 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_config_smu()
115 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU) { in dw_mci_exynos_config_smu()
127 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_priv_init()
131 if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) { in dw_mci_exynos_priv_init()
132 priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL); in dw_mci_exynos_priv_init()
133 priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN); in dw_mci_exynos_priv_init()
134 priv->saved_dqs_en |= AXI_NON_BLOCKING_WR; in dw_mci_exynos_priv_init()
135 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en); in dw_mci_exynos_priv_init()
136 if (!priv->dqs_delay) in dw_mci_exynos_priv_init()
137 priv->dqs_delay = in dw_mci_exynos_priv_init()
138 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); in dw_mci_exynos_priv_init()
141 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_priv_init()
142 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU) { in dw_mci_exynos_priv_init()
144 host->quirks |= DW_MMC_QUIRK_FIFO64_32; in dw_mci_exynos_priv_init()
147 if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { in dw_mci_exynos_priv_init()
148 /* Quirk needed for the ARTPEC-8 SoC */ in dw_mci_exynos_priv_init()
149 host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; in dw_mci_exynos_priv_init()
152 host->bus_hz /= (priv->ciu_div + 1); in dw_mci_exynos_priv_init()
159 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_set_clksel_timing()
162 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_set_clksel_timing()
163 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_set_clksel_timing()
164 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_set_clksel_timing()
165 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_set_clksel_timing()
166 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_set_clksel_timing()
173 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_set_clksel_timing()
174 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_set_clksel_timing()
175 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_set_clksel_timing()
176 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_set_clksel_timing()
177 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_set_clksel_timing()
184 * use of bit 29 (which is reserved on standard MSHC controllers) for in dw_mci_exynos_set_clksel_timing()
189 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) in dw_mci_exynos_set_clksel_timing()
190 set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags); in dw_mci_exynos_set_clksel_timing()
211 * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code
224 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
237 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_resume_noirq()
245 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_resume_noirq()
246 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_resume_noirq()
247 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_resume_noirq()
248 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_resume_noirq()
249 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_resume_noirq()
255 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_resume_noirq()
256 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_resume_noirq()
257 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_resume_noirq()
258 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_resume_noirq()
259 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_resume_noirq()
273 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_config_hs400()
280 if ((priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) || in dw_mci_exynos_config_hs400()
281 (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)) { in dw_mci_exynos_config_hs400()
283 dev_warn(host->dev, in dw_mci_exynos_config_hs400()
288 dqs = priv->saved_dqs_en; in dw_mci_exynos_config_hs400()
289 strobe = priv->saved_strobe_ctrl; in dw_mci_exynos_config_hs400()
293 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay); in dw_mci_exynos_config_hs400()
306 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_adjust_clock()
314 if (!wanted || IS_ERR(host->ciu_clk)) in dw_mci_exynos_adjust_clock()
321 if (wanted == priv->cur_speed) in dw_mci_exynos_adjust_clock()
325 ret = clk_set_rate(host->ciu_clk, wanted * div); in dw_mci_exynos_adjust_clock()
327 dev_warn(host->dev, in dw_mci_exynos_adjust_clock()
328 "failed to set clk-rate %u error: %d\n", in dw_mci_exynos_adjust_clock()
330 actual = clk_get_rate(host->ciu_clk); in dw_mci_exynos_adjust_clock()
331 host->bus_hz = actual / div; in dw_mci_exynos_adjust_clock()
332 priv->cur_speed = wanted; in dw_mci_exynos_adjust_clock()
333 host->current_speed = 0; in dw_mci_exynos_adjust_clock()
338 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_set_ios()
339 unsigned int wanted = ios->clock; in dw_mci_exynos_set_ios()
340 u32 timing = ios->timing, clksel; in dw_mci_exynos_set_ios()
346 priv->hs400_timing, priv->tuned_sample); in dw_mci_exynos_set_ios()
350 clksel = priv->ddr_timing; in dw_mci_exynos_set_ios()
352 if (ios->bus_width == MMC_BUS_WIDTH_8) in dw_mci_exynos_set_ios()
357 clksel = (priv->sdr_timing & 0xfff8ffff) | in dw_mci_exynos_set_ios()
358 (priv->ciu_div << 16); in dw_mci_exynos_set_ios()
361 clksel = (priv->ddr_timing & 0xfff8ffff) | in dw_mci_exynos_set_ios()
362 (priv->ciu_div << 16); in dw_mci_exynos_set_ios()
365 clksel = priv->sdr_timing; in dw_mci_exynos_set_ios()
381 struct device_node *np = host->dev->of_node; in dw_mci_exynos_parse_dt()
387 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); in dw_mci_exynos_parse_dt()
389 return -ENOMEM; in dw_mci_exynos_parse_dt()
393 priv->ctrl_type = exynos_compat[idx].ctrl_type; in dw_mci_exynos_parse_dt()
396 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) in dw_mci_exynos_parse_dt()
397 priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; in dw_mci_exynos_parse_dt()
398 else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) in dw_mci_exynos_parse_dt()
399 priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; in dw_mci_exynos_parse_dt()
401 of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); in dw_mci_exynos_parse_dt()
402 priv->ciu_div = div; in dw_mci_exynos_parse_dt()
406 "samsung,dw-mshc-sdr-timing", timing, 2); in dw_mci_exynos_parse_dt()
410 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); in dw_mci_exynos_parse_dt()
413 "samsung,dw-mshc-ddr-timing", timing, 2); in dw_mci_exynos_parse_dt()
417 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); in dw_mci_exynos_parse_dt()
420 "samsung,dw-mshc-hs400-timing", timing, 2); in dw_mci_exynos_parse_dt()
422 "samsung,read-strobe-delay", &priv->dqs_delay)) in dw_mci_exynos_parse_dt()
423 dev_dbg(host->dev, in dw_mci_exynos_parse_dt()
424 "read-strobe-delay is not found, assuming usage of default value\n"); in dw_mci_exynos_parse_dt()
426 priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], in dw_mci_exynos_parse_dt()
428 host->priv = priv; in dw_mci_exynos_parse_dt()
434 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_get_clksmpl()
436 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_get_clksmpl()
437 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_get_clksmpl()
438 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_get_clksmpl()
439 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_get_clksmpl()
440 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_get_clksmpl()
449 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_set_clksmpl()
451 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_set_clksmpl()
452 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_set_clksmpl()
453 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_set_clksmpl()
454 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_set_clksmpl()
455 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_set_clksmpl()
460 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_set_clksmpl()
461 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_set_clksmpl()
462 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_set_clksmpl()
463 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_set_clksmpl()
464 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_set_clksmpl()
472 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_move_next_clksmpl()
476 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_move_next_clksmpl()
477 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_move_next_clksmpl()
478 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_move_next_clksmpl()
479 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_move_next_clksmpl()
480 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_move_next_clksmpl()
488 if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || in dw_mci_exynos_move_next_clksmpl()
489 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || in dw_mci_exynos_move_next_clksmpl()
490 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 || in dw_mci_exynos_move_next_clksmpl()
491 priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU || in dw_mci_exynos_move_next_clksmpl()
492 priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) in dw_mci_exynos_move_next_clksmpl()
504 s8 i, loc = -1; in dw_mci_exynos_get_best_clksmpl()
523 * If there is no cadiates value, then it needs to return -EIO. in dw_mci_exynos_get_best_clksmpl()
540 struct dw_mci *host = slot->host; in dw_mci_exynos_execute_tuning()
541 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_execute_tuning()
542 struct mmc_host *mmc = slot->mmc; in dw_mci_exynos_execute_tuning()
561 priv->tuned_sample = found; in dw_mci_exynos_execute_tuning()
563 ret = -EIO; in dw_mci_exynos_execute_tuning()
564 dev_warn(&mmc->class_dev, in dw_mci_exynos_execute_tuning()
574 struct dw_mci_exynos_priv_data *priv = host->priv; in dw_mci_exynos_prepare_hs400_tuning()
576 dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing); in dw_mci_exynos_prepare_hs400_tuning()
577 dw_mci_exynos_adjust_clock(host, (ios->clock) << 1); in dw_mci_exynos_prepare_hs400_tuning()
593 tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC); in dw_mci_exynos_set_data_timeout()
601 * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) in dw_mci_exynos_set_data_timeout()
611 tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); in dw_mci_exynos_set_data_timeout()
616 dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x", in dw_mci_exynos_set_data_timeout()
626 return (((drto_clks & 0x7) - 1) * 0xFFFFFF) + ((drto_clks & 0xFFFFF8)); in dw_mci_exynos_get_drto_clks()
659 { .compatible = "samsung,exynos4412-dw-mshc",
661 { .compatible = "samsung,exynos5250-dw-mshc",
663 { .compatible = "samsung,exynos5420-dw-mshc",
665 { .compatible = "samsung,exynos5420-dw-mshc-smu",
667 { .compatible = "samsung,exynos7-dw-mshc",
669 { .compatible = "samsung,exynos7-dw-mshc-smu",
671 { .compatible = "samsung,exynos7870-dw-mshc",
673 { .compatible = "samsung,exynos7870-dw-mshc-smu",
675 { .compatible = "axis,artpec8-dw-mshc",
687 match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node); in dw_mci_exynos_probe()
688 drv_data = match->data; in dw_mci_exynos_probe()
690 pm_runtime_get_noresume(&pdev->dev); in dw_mci_exynos_probe()
691 pm_runtime_set_active(&pdev->dev); in dw_mci_exynos_probe()
692 pm_runtime_enable(&pdev->dev); in dw_mci_exynos_probe()
696 pm_runtime_disable(&pdev->dev); in dw_mci_exynos_probe()
697 pm_runtime_set_suspended(&pdev->dev); in dw_mci_exynos_probe()
698 pm_runtime_put_noidle(&pdev->dev); in dw_mci_exynos_probe()
708 pm_runtime_disable(&pdev->dev); in dw_mci_exynos_remove()
709 pm_runtime_set_suspended(&pdev->dev); in dw_mci_exynos_remove()
710 pm_runtime_put_noidle(&pdev->dev); in dw_mci_exynos_remove()
736 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");