Lines Matching +full:hs400 +full:- +full:ds +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
34 #include <linux/mmc/slot-gpio.h>
41 /*--------------------------------------------------------------------------*/
43 /*--------------------------------------------------------------------------*/
50 /*--------------------------------------------------------------------------*/
52 /*--------------------------------------------------------------------------*/
89 /*--------------------------------------------------------------------------*/
91 /*--------------------------------------------------------------------------*/
96 /*--------------------------------------------------------------------------*/
98 /*--------------------------------------------------------------------------*/
330 #define PAD_DELAY_MAX 32 /* PAD delay cells */
331 /*--------------------------------------------------------------------------*/
333 /*--------------------------------------------------------------------------*/
464 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
465 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
467 /* cmd response sample selection for HS400 */
468 bool hs400_mode; /* current eMMC will run at hs400 mode */
469 bool hs400_tuning; /* hs400 mode online tuning */
470 bool internal_cd; /* Use internal card-detect logic */
621 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
622 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
623 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
624 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
625 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
626 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
627 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
628 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
629 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
630 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
631 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
658 tv |= ((val) << (ffs((unsigned int)field) - 1)); in sdr_set_field()
666 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); in sdr_get_field()
673 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
674 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
676 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
677 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val, in msdc_reset_hw()
680 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
681 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
701 return 0xff - (u8) sum; in msdc_dma_calcs()
714 sg = data->sg; in msdc_dma_setup()
716 gpd = dma->gpd; in msdc_dma_setup()
717 bd = dma->bd; in msdc_dma_setup()
720 gpd->gpd_info |= GPDMA_DESC_HWO; in msdc_dma_setup()
721 gpd->gpd_info |= GPDMA_DESC_BDP; in msdc_dma_setup()
723 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; in msdc_dma_setup()
724 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; in msdc_dma_setup()
727 for_each_sg(data->sg, sg, data->sg_count, j) { in msdc_dma_setup()
735 if (host->dev_comp->support_64g) { in msdc_dma_setup()
741 if (host->dev_comp->support_64g) { in msdc_dma_setup()
749 if (j == data->sg_count - 1) /* the last bd */ in msdc_dma_setup()
759 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
760 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
763 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
764 if (host->dev_comp->support_64g) in msdc_dma_setup()
765 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
766 upper_32_bits(dma->gpd_addr) & 0xf); in msdc_dma_setup()
767 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
772 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { in msdc_prepare_data()
773 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
775 if (data->sg_count) in msdc_prepare_data()
776 data->host_cookie |= MSDC_PREPARE_FLAG; in msdc_prepare_data()
782 return data->host_cookie & MSDC_PREPARE_FLAG; in msdc_data_prepared()
787 if (data->host_cookie & MSDC_ASYNC_FLAG) in msdc_unprepare_data()
790 if (data->host_cookie & MSDC_PREPARE_FLAG) { in msdc_unprepare_data()
791 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
793 data->host_cookie &= ~MSDC_PREPARE_FLAG; in msdc_unprepare_data()
803 if (mmc->actual_clock == 0) { in msdc_timeout_cal()
807 do_div(clk_ns, mmc->actual_clock); in msdc_timeout_cal()
808 timeout = ns + clk_ns - 1; in msdc_timeout_cal()
813 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
814 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
817 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
821 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_timeout_cal()
831 host->timeout_ns = ns; in msdc_set_timeout()
832 host->timeout_clks = clks; in msdc_set_timeout()
835 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
844 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
850 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_gate_clock()
851 clk_disable_unprepare(host->crypto_clk); in msdc_gate_clock()
852 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
853 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
854 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
855 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
863 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
864 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
865 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
866 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
867 clk_prepare_enable(host->crypto_clk); in msdc_ungate_clock()
868 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_ungate_clock()
870 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); in msdc_ungate_clock()
874 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
885 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
889 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
890 host->mclk = 0; in msdc_set_mclk()
891 mmc->actual_clock = 0; in msdc_set_mclk()
892 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
896 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
897 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
898 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
899 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
901 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
911 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
913 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
915 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
916 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
921 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
922 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
923 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
926 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
928 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
931 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
934 sclk = host->src_clk_freq; in msdc_set_mclk()
937 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
939 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
941 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
942 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
945 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
947 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
948 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
949 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
953 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
957 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
958 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
959 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
960 mmc->actual_clock = sclk; in msdc_set_mclk()
961 host->mclk = hz; in msdc_set_mclk()
962 host->timing = timing; in msdc_set_mclk()
964 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
965 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
971 if (mmc->actual_clock <= 52000000) { in msdc_set_mclk()
972 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
973 if (host->top_base) { in msdc_set_mclk()
974 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
975 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
976 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
977 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
979 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
980 host->base + tune_reg); in msdc_set_mclk()
983 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
984 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
985 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
986 if (host->top_base) { in msdc_set_mclk()
987 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
988 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
989 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
990 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
992 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
993 host->base + tune_reg); in msdc_set_mclk()
998 host->dev_comp->hs400_tune) in msdc_set_mclk()
999 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
1001 host->hs400_cmd_int_delay); in msdc_set_mclk()
1002 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
1042 u32 opcode = cmd->opcode; in msdc_cmd_prepare_raw_cmd()
1046 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
1048 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || in msdc_cmd_prepare_raw_cmd()
1060 if (cmd->data) { in msdc_cmd_prepare_raw_cmd()
1061 struct mmc_data *data = cmd->data; in msdc_cmd_prepare_raw_cmd()
1064 if (mmc_card_mmc(mmc->card) && mrq->sbc && in msdc_cmd_prepare_raw_cmd()
1065 !(mrq->sbc->arg & 0xFFFF0000)) in msdc_cmd_prepare_raw_cmd()
1069 rawcmd |= ((data->blksz & 0xFFF) << 16); in msdc_cmd_prepare_raw_cmd()
1070 if (data->flags & MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
1072 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
1077 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1079 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1080 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1081 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1082 data->timeout_clks); in msdc_cmd_prepare_raw_cmd()
1084 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1094 WARN_ON(host->data); in msdc_start_data()
1095 host->data = data; in msdc_start_data()
1096 read = data->flags & MMC_DATA_READ; in msdc_start_data()
1098 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1099 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1100 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1101 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1102 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1103 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1104 __func__, cmd->opcode, data->blocks, read); in msdc_start_data()
1110 u32 *rsp = cmd->resp; in msdc_auto_cmd_done()
1112 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1115 cmd->error = 0; in msdc_auto_cmd_done()
1119 cmd->error = -EILSEQ; in msdc_auto_cmd_done()
1120 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1122 cmd->error = -ETIMEDOUT; in msdc_auto_cmd_done()
1123 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1125 dev_err(host->dev, in msdc_auto_cmd_done()
1127 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); in msdc_auto_cmd_done()
1129 return cmd->error; in msdc_auto_cmd_done()
1133 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1144 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in msdc_recheck_sdio_irq()
1145 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1147 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1148 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1160 if (host->error) in msdc_track_cmd_data()
1161 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1162 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1173 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1175 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1176 host->mrq = NULL; in msdc_request_done()
1177 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1179 msdc_track_cmd_data(host, mrq->cmd); in msdc_request_done()
1180 if (mrq->data) in msdc_request_done()
1181 msdc_unprepare_data(host, mrq->data); in msdc_request_done()
1182 if (host->error) in msdc_request_done()
1185 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1198 if (mrq->sbc && cmd == mrq->cmd && in msdc_cmd_done()
1201 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1203 sbc_error = mrq->sbc && mrq->sbc->error; in msdc_cmd_done()
1210 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1211 done = !host->cmd; in msdc_cmd_done()
1212 host->cmd = NULL; in msdc_cmd_done()
1213 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1217 rsp = cmd->resp; in msdc_cmd_done()
1219 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1221 if (cmd->flags & MMC_RSP_PRESENT) { in msdc_cmd_done()
1222 if (cmd->flags & MMC_RSP_136) { in msdc_cmd_done()
1223 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1224 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1225 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1226 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1228 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1233 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) || in msdc_cmd_done()
1234 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) in msdc_cmd_done()
1242 cmd->error = -EILSEQ; in msdc_cmd_done()
1243 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1245 cmd->error = -ETIMEDOUT; in msdc_cmd_done()
1246 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1249 if (cmd->error) in msdc_cmd_done()
1250 dev_dbg(host->dev, in msdc_cmd_done()
1252 __func__, cmd->opcode, cmd->arg, rsp[0], in msdc_cmd_done()
1253 cmd->error); in msdc_cmd_done()
1270 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1273 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1274 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1279 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { in msdc_cmd_is_ready()
1281 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1284 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1285 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1299 WARN_ON(host->cmd); in msdc_start_command()
1300 host->cmd = cmd; in msdc_start_command()
1302 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1306 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1307 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1308 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1312 cmd->error = 0; in msdc_start_command()
1315 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1316 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1317 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1319 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1320 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1326 if ((cmd->error && !host->hs400_tuning && in msdc_cmd_next()
1327 !(cmd->error == -EILSEQ && in msdc_cmd_next()
1328 mmc_op_tuning(cmd->opcode))) || in msdc_cmd_next()
1329 (mrq->sbc && mrq->sbc->error)) in msdc_cmd_next()
1331 else if (cmd == mrq->sbc) in msdc_cmd_next()
1332 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1333 else if (!cmd->data) in msdc_cmd_next()
1336 msdc_start_data(host, cmd, cmd->data); in msdc_cmd_next()
1343 host->error = 0; in msdc_ops_request()
1344 WARN_ON(host->mrq); in msdc_ops_request()
1345 host->mrq = mrq; in msdc_ops_request()
1347 if (mrq->data) { in msdc_ops_request()
1348 msdc_prepare_data(host, mrq->data); in msdc_ops_request()
1349 if (!msdc_data_prepared(mrq->data)) { in msdc_ops_request()
1350 host->mrq = NULL; in msdc_ops_request()
1355 mrq->cmd->error = -ENOSPC; in msdc_ops_request()
1365 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || in msdc_ops_request()
1366 (mrq->sbc->arg & 0xFFFF0000))) in msdc_ops_request()
1367 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1369 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1375 struct mmc_data *data = mrq->data; in msdc_pre_req()
1381 data->host_cookie |= MSDC_ASYNC_FLAG; in msdc_pre_req()
1388 struct mmc_data *data = mrq->data; in msdc_post_req()
1393 if (data->host_cookie) { in msdc_post_req()
1394 data->host_cookie &= ~MSDC_ASYNC_FLAG; in msdc_post_req()
1401 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && in msdc_data_xfer_next()
1402 !mrq->sbc) in msdc_data_xfer_next()
1403 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1421 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1422 done = !host->data; in msdc_data_xfer_done()
1424 host->data = NULL; in msdc_data_xfer_done()
1425 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1429 stop = data->stop; in msdc_data_xfer_done()
1431 if (check_data || (stop && stop->error)) { in msdc_data_xfer_done()
1432 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1433 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1434 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1437 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, in msdc_data_xfer_done()
1440 dev_dbg(host->dev, "DMA stop timed out\n"); in msdc_data_xfer_done()
1442 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, in msdc_data_xfer_done()
1445 dev_dbg(host->dev, "DMA inactive timed out\n"); in msdc_data_xfer_done()
1447 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1448 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1450 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { in msdc_data_xfer_done()
1451 data->bytes_xfered = data->blocks * data->blksz; in msdc_data_xfer_done()
1453 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1455 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1456 data->bytes_xfered = 0; in msdc_data_xfer_done()
1459 data->error = -ETIMEDOUT; in msdc_data_xfer_done()
1461 data->error = -EILSEQ; in msdc_data_xfer_done()
1463 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1464 __func__, mrq->cmd->opcode, data->blocks); in msdc_data_xfer_done()
1465 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1466 (int)data->error, data->bytes_xfered); in msdc_data_xfer_done()
1475 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1492 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1493 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1501 if (!IS_ERR(mmc->supply.vqmmc)) { in msdc_ops_switch_volt()
1502 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && in msdc_ops_switch_volt()
1503 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { in msdc_ops_switch_volt()
1504 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1505 return -EINVAL; in msdc_ops_switch_volt()
1510 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1511 ret, ios->signal_voltage); in msdc_ops_switch_volt()
1516 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in msdc_ops_switch_volt()
1517 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1519 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1527 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1539 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1540 if (host->mrq) { in msdc_request_timeout()
1541 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1542 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1543 if (host->cmd) { in msdc_request_timeout()
1544 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1545 __func__, host->cmd->opcode); in msdc_request_timeout()
1546 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1547 host->cmd); in msdc_request_timeout()
1548 } else if (host->data) { in msdc_request_timeout()
1549 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1550 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1551 host->data->blocks); in msdc_request_timeout()
1552 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1553 host->data); in msdc_request_timeout()
1561 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1562 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1563 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1566 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1567 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1577 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1579 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1581 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { in msdc_enable_sdio_irq()
1589 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_enable_sdio_irq()
1590 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); in msdc_enable_sdio_irq()
1593 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); in msdc_enable_sdio_irq()
1594 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1595 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1597 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); in msdc_enable_sdio_irq()
1600 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_enable_sdio_irq()
1602 dev_pm_clear_wake_irq(host->dev); in msdc_enable_sdio_irq()
1606 /* Ensure host->pins_eint is NULL */ in msdc_enable_sdio_irq()
1607 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1608 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1610 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1621 cmd_err = -EILSEQ; in msdc_cmdq_irq()
1622 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1624 cmd_err = -ETIMEDOUT; in msdc_cmdq_irq()
1625 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1629 dat_err = -EILSEQ; in msdc_cmdq_irq()
1630 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1632 dat_err = -ETIMEDOUT; in msdc_cmdq_irq()
1633 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1637 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", in msdc_cmdq_irq()
1655 spin_lock(&host->lock); in msdc_irq()
1656 events = readl(host->base + MSDC_INT); in msdc_irq()
1657 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1661 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1663 mrq = host->mrq; in msdc_irq()
1664 cmd = host->cmd; in msdc_irq()
1665 data = host->data; in msdc_irq()
1666 spin_unlock(&host->lock); in msdc_irq()
1672 if (host->internal_cd) in msdc_irq()
1680 if ((mmc->caps2 & MMC_CAP2_CQE) && in msdc_irq()
1684 writel(events, host->base + MSDC_INT); in msdc_irq()
1689 dev_err(host->dev, in msdc_irq()
1696 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1710 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1713 if (host->reset) { in msdc_init_hw()
1714 reset_control_assert(host->reset); in msdc_init_hw()
1716 reset_control_deassert(host->reset); in msdc_init_hw()
1720 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1726 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1727 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1728 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1731 if (host->internal_cd) { in msdc_init_hw()
1732 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1734 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1735 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1736 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1738 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1739 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1740 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1743 if (host->top_base) { in msdc_init_hw()
1744 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1745 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1747 writel(0, host->base + tune_reg); in msdc_init_hw()
1749 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1750 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1751 writel(0x403c0046, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1752 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); in msdc_init_hw()
1753 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1754 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1756 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1757 sdr_set_field(host->base + MSDC_PATCH_BIT1, in msdc_init_hw()
1759 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1761 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1765 if (host->dev_comp->busy_check) in msdc_init_hw()
1766 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); in msdc_init_hw()
1768 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1769 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1771 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1772 if (host->top_base) in msdc_init_hw()
1773 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1776 sdr_set_bits(host->base + SDC_ADV_CFG0, in msdc_init_hw()
1779 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1781 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1784 /* use async fifo, then no need tune internal delay */ in msdc_init_hw()
1785 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1787 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1791 if (host->dev_comp->support_64g) in msdc_init_hw()
1792 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1794 if (host->dev_comp->data_tune) { in msdc_init_hw()
1795 if (host->top_base) { in msdc_init_hw()
1796 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1798 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1800 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1803 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1809 if (host->top_base) in msdc_init_hw()
1810 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1813 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1817 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_init_hw()
1818 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1819 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in msdc_init_hw()
1820 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1823 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1826 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
1827 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1831 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
1833 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1834 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1835 if (host->top_base) { in msdc_init_hw()
1836 host->def_tune_para.emmc_top_control = in msdc_init_hw()
1837 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1838 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
1839 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1840 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
1841 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1842 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
1843 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1845 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1846 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1848 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
1855 if (host->internal_cd) { in msdc_deinit_hw()
1856 /* Disabled card-detect */ in msdc_deinit_hw()
1857 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
1858 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
1862 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
1864 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
1865 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
1871 struct mt_gpdma_desc *gpd = dma->gpd; in msdc_init_gpd_bd()
1872 struct mt_bdma_desc *bd = dma->bd; in msdc_init_gpd_bd()
1878 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); in msdc_init_gpd_bd()
1879 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ in msdc_init_gpd_bd()
1880 /* gpd->next is must set for desc DMA in msdc_init_gpd_bd()
1883 gpd->next = lower_32_bits(dma_addr); in msdc_init_gpd_bd()
1884 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1885 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; in msdc_init_gpd_bd()
1887 dma_addr = dma->bd_addr; in msdc_init_gpd_bd()
1888 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ in msdc_init_gpd_bd()
1889 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1890 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; in msdc_init_gpd_bd()
1893 for (i = 0; i < (MAX_BD_NUM - 1); i++) { in msdc_init_gpd_bd()
1894 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); in msdc_init_gpd_bd()
1896 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1906 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
1909 switch (ios->power_mode) { in msdc_ops_set_ios()
1911 if (!IS_ERR(mmc->supply.vmmc)) { in msdc_ops_set_ios()
1913 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in msdc_ops_set_ios()
1914 ios->vdd); in msdc_ops_set_ios()
1916 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
1922 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
1923 ret = regulator_enable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1925 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
1927 host->vqmmc_enabled = true; in msdc_ops_set_ios()
1931 if (!IS_ERR(mmc->supply.vmmc)) in msdc_ops_set_ios()
1932 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in msdc_ops_set_ios()
1934 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
1935 regulator_disable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1936 host->vqmmc_enabled = false; in msdc_ops_set_ios()
1943 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
1944 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
1947 static u32 test_delay_bit(u32 delay, u32 bit) in test_delay_bit() argument
1950 return delay & BIT(bit); in test_delay_bit()
1953 static int get_delay_len(u32 delay, u32 start_bit) in get_delay_len() argument
1957 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { in get_delay_len()
1958 if (test_delay_bit(delay, start_bit + i) == 0) in get_delay_len()
1961 return PAD_DELAY_MAX - start_bit; in get_delay_len()
1964 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) in get_best_delay() argument
1971 if (delay == 0) { in get_best_delay()
1972 dev_err(host->dev, "phase error: [map:%x]\n", delay); in get_best_delay()
1978 len = get_delay_len(delay, start); in get_best_delay()
1988 /* The rule is that to find the smallest delay cell */ in get_best_delay()
1993 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", in get_best_delay()
1994 delay, len_final, final_phase); in get_best_delay()
2004 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
2006 if (host->top_base) in msdc_set_cmd_delay()
2007 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, in msdc_set_cmd_delay()
2010 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
2016 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
2018 if (host->top_base) in msdc_set_data_delay()
2019 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2022 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
2034 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
2038 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in msdc_tune_response()
2039 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in msdc_tune_response()
2040 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2042 host->hs200_cmd_int_delay); in msdc_tune_response()
2044 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2068 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2093 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2096 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2101 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
2105 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2111 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2113 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2116 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2117 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
2130 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2131 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2133 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in hs400_tune_response()
2134 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in hs400_tune_response()
2135 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2137 host->hs200_cmd_int_delay); in hs400_tune_response()
2139 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2140 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2142 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2144 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2162 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2166 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2167 return final_delay == 0xff ? -EIO : 0; in hs400_tune_response()
2178 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2179 host->latch_ck); in msdc_tune_data()
2180 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2181 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2194 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2195 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2207 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2208 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2211 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2212 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2217 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2218 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
2233 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2234 host->latch_ck); in msdc_tune_together()
2236 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2237 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2252 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2253 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2267 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2268 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2272 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2273 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2281 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2282 return final_delay == 0xff ? -EIO : 0; in msdc_tune_together()
2289 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2291 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2293 if (host->hs400_mode) { in msdc_execute_tuning()
2294 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_execute_tuning()
2300 if (host->hs400_mode && in msdc_execute_tuning()
2301 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2305 if (ret == -EIO) { in msdc_execute_tuning()
2306 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2309 if (host->hs400_mode == false) { in msdc_execute_tuning()
2311 if (ret == -EIO) in msdc_execute_tuning()
2312 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2316 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2317 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2318 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2319 if (host->top_base) { in msdc_execute_tuning()
2320 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2322 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2332 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2334 if (host->top_base) { in msdc_prepare_hs400_tuning()
2335 if (host->hs400_ds_dly3) in msdc_prepare_hs400_tuning()
2336 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_prepare_hs400_tuning()
2337 PAD_DS_DLY3, host->hs400_ds_dly3); in msdc_prepare_hs400_tuning()
2338 if (host->hs400_ds_delay) in msdc_prepare_hs400_tuning()
2339 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2340 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2342 if (host->hs400_ds_dly3) in msdc_prepare_hs400_tuning()
2343 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_prepare_hs400_tuning()
2344 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); in msdc_prepare_hs400_tuning()
2345 if (host->hs400_ds_delay) in msdc_prepare_hs400_tuning()
2346 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2348 /* hs400 mode must set it to 0 */ in msdc_prepare_hs400_tuning()
2349 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2351 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2364 if (host->top_base) { in msdc_execute_hs400_tuning()
2365 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2367 sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2370 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); in msdc_execute_hs400_tuning()
2371 sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL); in msdc_execute_hs400_tuning()
2374 host->hs400_tuning = true; in msdc_execute_hs400_tuning()
2376 if (host->top_base) in msdc_execute_hs400_tuning()
2377 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2380 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2388 host->hs400_tuning = false; in msdc_execute_hs400_tuning()
2392 dev_err(host->dev, "Failed to get DLY1 delay!\n"); in msdc_execute_hs400_tuning()
2395 if (host->top_base) in msdc_execute_hs400_tuning()
2396 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2399 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2402 if (host->top_base) in msdc_execute_hs400_tuning()
2403 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2405 val = readl(host->base + PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2407 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); in msdc_execute_hs400_tuning()
2412 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); in msdc_execute_hs400_tuning()
2413 return -EIO; in msdc_execute_hs400_tuning()
2420 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2422 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2430 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2432 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2440 if (mmc->caps & MMC_CAP_NONREMOVABLE) in msdc_get_cd()
2443 if (!host->internal_cd) in msdc_get_cd()
2446 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2447 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) in msdc_get_cd()
2458 if (ios->enhanced_strobe) { in msdc_hs400_enhanced_strobe()
2460 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); in msdc_hs400_enhanced_strobe()
2461 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); in msdc_hs400_enhanced_strobe()
2462 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); in msdc_hs400_enhanced_strobe()
2464 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2465 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2466 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); in msdc_hs400_enhanced_strobe()
2468 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); in msdc_hs400_enhanced_strobe()
2469 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); in msdc_hs400_enhanced_strobe()
2470 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); in msdc_hs400_enhanced_strobe()
2472 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2473 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2474 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); in msdc_hs400_enhanced_strobe()
2481 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_cit_cal()
2490 hclk_freq = (u64)clk_get_rate(host->h_clk); in msdc_cqe_cit_cal()
2508 host->cq_ssc1_time = 0x40; in msdc_cqe_cit_cal()
2514 host->cq_ssc1_time = value; in msdc_cqe_cit_cal()
2520 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_enable()
2523 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2525 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2532 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1); in msdc_cqe_enable()
2541 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2543 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2545 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2546 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2549 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2551 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, in msdc_cqe_disable()
2554 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2563 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_pre_enable()
2573 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_post_disable()
2609 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", in msdc_of_property_parse()
2610 &host->latch_ck); in msdc_of_property_parse()
2612 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", in msdc_of_property_parse()
2613 &host->hs400_ds_delay); in msdc_of_property_parse()
2615 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", in msdc_of_property_parse()
2616 &host->hs400_ds_dly3); in msdc_of_property_parse()
2618 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", in msdc_of_property_parse()
2619 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2621 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", in msdc_of_property_parse()
2622 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2624 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2625 "mediatek,hs400-cmd-resp-sel-rising")) in msdc_of_property_parse()
2626 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2628 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2630 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2631 "supports-cqe")) in msdc_of_property_parse()
2632 host->cqhci = true; in msdc_of_property_parse()
2634 host->cqhci = false; in msdc_of_property_parse()
2642 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2643 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2644 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2646 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_of_clock_parse()
2647 if (IS_ERR(host->h_clk)) in msdc_of_clock_parse()
2648 return PTR_ERR(host->h_clk); in msdc_of_clock_parse()
2650 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); in msdc_of_clock_parse()
2651 if (IS_ERR(host->bus_clk)) in msdc_of_clock_parse()
2652 host->bus_clk = NULL; in msdc_of_clock_parse()
2655 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); in msdc_of_clock_parse()
2656 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2657 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2660 * Fallback for legacy device-trees: src_clk and HCLK use the same in msdc_of_clock_parse()
2666 if (!host->src_clk_cg) { in msdc_of_clock_parse()
2667 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
2668 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2669 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2673 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); in msdc_of_clock_parse()
2674 if (IS_ERR(host->sys_clk_cg)) in msdc_of_clock_parse()
2675 host->sys_clk_cg = NULL; in msdc_of_clock_parse()
2677 host->bulk_clks[0].id = "pclk_cg"; in msdc_of_clock_parse()
2678 host->bulk_clks[1].id = "axi_cg"; in msdc_of_clock_parse()
2679 host->bulk_clks[2].id = "ahb_cg"; in msdc_of_clock_parse()
2680 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, in msdc_of_clock_parse()
2681 host->bulk_clks); in msdc_of_clock_parse()
2683 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); in msdc_of_clock_parse()
2697 if (!pdev->dev.of_node) { in msdc_drv_probe()
2698 dev_err(&pdev->dev, "No DT found\n"); in msdc_drv_probe()
2699 return -EINVAL; in msdc_drv_probe()
2703 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host)); in msdc_drv_probe()
2705 return -ENOMEM; in msdc_drv_probe()
2712 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2713 if (IS_ERR(host->base)) in msdc_drv_probe()
2714 return PTR_ERR(host->base); in msdc_drv_probe()
2718 host->top_base = devm_ioremap_resource(&pdev->dev, res); in msdc_drv_probe()
2719 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2720 host->top_base = NULL; in msdc_drv_probe()
2731 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
2733 if (IS_ERR(host->reset)) in msdc_drv_probe()
2734 return PTR_ERR(host->reset); in msdc_drv_probe()
2737 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { in msdc_drv_probe()
2738 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); in msdc_drv_probe()
2739 if (IS_ERR(host->crypto_clk)) in msdc_drv_probe()
2740 return PTR_ERR(host->crypto_clk); in msdc_drv_probe()
2741 else if (host->crypto_clk) in msdc_drv_probe()
2742 mmc->caps2 |= MMC_CAP2_CRYPTO; in msdc_drv_probe()
2745 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
2746 if (host->irq < 0) in msdc_drv_probe()
2747 return host->irq; in msdc_drv_probe()
2749 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
2750 if (IS_ERR(host->pinctrl)) in msdc_drv_probe()
2751 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl), in msdc_drv_probe()
2754 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
2755 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
2756 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); in msdc_drv_probe()
2757 return PTR_ERR(host->pins_default); in msdc_drv_probe()
2760 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
2761 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
2762 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); in msdc_drv_probe()
2763 return PTR_ERR(host->pins_uhs); in msdc_drv_probe()
2767 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { in msdc_drv_probe()
2768 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup"); in msdc_drv_probe()
2769 if (host->eint_irq > 0) { in msdc_drv_probe()
2770 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); in msdc_drv_probe()
2771 if (IS_ERR(host->pins_eint)) { in msdc_drv_probe()
2772 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); in msdc_drv_probe()
2773 host->pins_eint = NULL; in msdc_drv_probe()
2775 device_init_wakeup(&pdev->dev, true); in msdc_drv_probe()
2782 host->dev = &pdev->dev; in msdc_drv_probe()
2783 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2784 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
2786 mmc->ops = &mt_msdc_ops; in msdc_drv_probe()
2787 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
2788 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
2790 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
2792 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && in msdc_drv_probe()
2794 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
2799 host->internal_cd = true; in msdc_drv_probe()
2802 if (mmc->caps & MMC_CAP_SDIO_IRQ) in msdc_drv_probe()
2803 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in msdc_drv_probe()
2805 mmc->caps |= MMC_CAP_CMD23; in msdc_drv_probe()
2806 if (host->cqhci) in msdc_drv_probe()
2807 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in msdc_drv_probe()
2809 mmc->max_segs = MAX_BD_NUM; in msdc_drv_probe()
2810 if (host->dev_comp->support_64g) in msdc_drv_probe()
2811 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; in msdc_drv_probe()
2813 mmc->max_seg_size = BDMA_DESC_BUFLEN; in msdc_drv_probe()
2814 mmc->max_blk_size = 2048; in msdc_drv_probe()
2815 mmc->max_req_size = 512 * 1024; in msdc_drv_probe()
2816 mmc->max_blk_count = mmc->max_req_size / 512; in msdc_drv_probe()
2817 if (host->dev_comp->support_64g) in msdc_drv_probe()
2818 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
2820 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
2821 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
2823 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
2824 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2826 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
2827 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2829 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
2830 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
2831 ret = -ENOMEM; in msdc_drv_probe()
2834 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
2835 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
2836 spin_lock_init(&host->lock); in msdc_drv_probe()
2841 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); in msdc_drv_probe()
2846 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_drv_probe()
2847 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
2848 sizeof(*host->cq_host), in msdc_drv_probe()
2850 if (!host->cq_host) { in msdc_drv_probe()
2851 ret = -ENOMEM; in msdc_drv_probe()
2854 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
2855 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
2856 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
2857 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
2860 mmc->max_segs = 128; in msdc_drv_probe()
2862 /* 0 size, means 65536 so we don't have to -1 here */ in msdc_drv_probe()
2863 mmc->max_seg_size = 64 * 1024; in msdc_drv_probe()
2868 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
2869 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
2873 pm_runtime_set_active(host->dev); in msdc_drv_probe()
2874 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
2875 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
2876 pm_runtime_enable(host->dev); in msdc_drv_probe()
2884 pm_runtime_disable(host->dev); in msdc_drv_probe()
2891 device_init_wakeup(&pdev->dev, false); in msdc_drv_probe()
2892 if (host->dma.gpd) in msdc_drv_probe()
2893 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2895 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
2896 if (host->dma.bd) in msdc_drv_probe()
2897 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2899 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
2911 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
2918 pm_runtime_disable(host->dev); in msdc_drv_remove()
2919 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
2920 dma_free_coherent(&pdev->dev, in msdc_drv_remove()
2922 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
2923 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), in msdc_drv_remove()
2924 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
2925 device_init_wakeup(&pdev->dev, false); in msdc_drv_remove()
2930 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
2932 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
2933 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
2934 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
2935 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
2936 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
2937 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
2938 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
2939 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
2940 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
2941 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
2942 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
2943 if (host->top_base) { in msdc_save_reg()
2944 host->save_para.emmc_top_control = in msdc_save_reg()
2945 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
2946 host->save_para.emmc_top_cmd = in msdc_save_reg()
2947 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
2948 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
2949 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
2951 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
2958 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
2960 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
2961 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
2962 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
2963 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
2964 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
2965 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
2966 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
2967 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
2968 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
2969 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
2970 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
2971 if (host->top_base) { in msdc_restore_reg()
2972 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
2973 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
2974 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
2975 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
2976 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
2977 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
2979 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
2994 if (host->pins_eint) { in msdc_runtime_suspend()
2995 disable_irq(host->irq); in msdc_runtime_suspend()
2996 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_runtime_suspend()
3017 if (sdio_irq_claimed(mmc) && host->pins_eint) { in msdc_runtime_resume()
3018 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_runtime_resume()
3019 enable_irq(host->irq); in msdc_runtime_resume()
3031 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_suspend()
3035 val = readl(host->base + MSDC_INT); in msdc_suspend()
3036 writel(val, host->base + MSDC_INT); in msdc_suspend()
3040 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will in msdc_suspend()
3043 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_suspend()
3054 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_resume()
3069 .name = "mtk-msdc",