150  * The flag tells that the ESDHC controller is an USDHC block that is
162  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
174  * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card
348 	 * USDHC has one limition, require the SDIO device a different
370 	{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
371 	{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
372 	{ .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
373 	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
374 	{ .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
375 	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
376 	{ .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
377 	{ .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
378 	{ .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
379 	{ .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
380 	{ .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
470 	 * For USDHC, auto tuning circuit can not handle the async sdio  in usdhc_auto_tuning_mode_sel_and_en()
640 			 * The usdhc register returns a wrong host version.  in esdhc_readw_le()
770 				 * tuning, when send tuning command, usdhc will  in esdhc_writew_le()
888 			 * The reset on usdhc fails to clear MIX_CTRL register.  in esdhc_writeb_le()
1081 			 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which  in esdhc_reset_tuning()
1106 	 * i.MX uSDHC internally already uses a fixed optimized timing for  in usdhc_execute_tuning()
1135 	/* IC suggest to reset USDHC before every tuning command */  in esdhc_prepare_tuning()
1274 	 * for the uSDHC loopback read clock  in esdhc_set_strobe_dll()
1359 	/* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */  in esdhc_get_max_timeout_count()
1431 		 * to zero if this usdhc is chosen to boot system. Change  in sdhci_esdhc_imx_hwinit()
1458 		 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a  in sdhci_esdhc_imx_hwinit()
1500 			 * the buffer read ready interrupt immediately. If usdhc send  in sdhci_esdhc_imx_hwinit()
1726 		 * Link usdhc specific mmc_host_ops execute_tuning function,  in sdhci_esdhc_imx_probe()
1732 		 * Link usdhc specific mmc_host_ops init card function,  in sdhci_esdhc_imx_probe()