Lines Matching +full:enable +full:- +full:ssc
1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
335 /* enable tuning parameters control */ in gli_set_9750()
392 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
405 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
407 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
408 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
412 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
415 return -EAGAIN; in __sdhci_execute_tuning_9750()
420 host->mmc->retune_period = 0; in gl9750_execute_tuning()
421 if (host->tuning_mode == SDHCI_TUNING_MODE_1) in gl9750_execute_tuning()
422 host->mmc->retune_period = host->tuning_count; in gl9750_execute_tuning()
425 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); in gl9750_execute_tuning()
474 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) in gl9750_set_ssc() argument
477 u32 ssc; in gl9750_set_ssc() local
481 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
484 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; in gl9750_set_ssc()
486 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); in gl9750_set_ssc()
487 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); in gl9750_set_ssc()
488 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
495 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_205mhz() local
497 /* set pll to 205MHz and ssc */ in gl9750_set_ssc_pll_205mhz()
498 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); in gl9750_set_ssc_pll_205mhz()
504 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_100mhz() local
506 /* set pll to 100MHz and ssc */ in gl9750_set_ssc_pll_100mhz()
507 gl9750_set_ssc(host, enable, 0xE, 0x51EC); in gl9750_set_ssc_pll_100mhz()
513 bool enable = gl9750_ssc_enable(host); in gl9750_set_ssc_pll_50mhz() local
515 /* set pll to 50MHz and ssc */ in gl9750_set_ssc_pll_50mhz()
516 gl9750_set_ssc(host, enable, 0xE, 0x51EC); in gl9750_set_ssc_pll_50mhz()
522 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9750_set_clock()
525 host->mmc->actual_clock = 0; in sdhci_gl9750_set_clock()
533 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9750_set_clock()
534 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9750_set_clock()
535 host->mmc->actual_clock = 205000000; in sdhci_gl9750_set_clock()
552 pdev = slot->chip->pdev; in gl9750_hw_setting()
582 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, in gli_pcie_enable_msi()
585 pr_warn("%s: enable PCI MSI failed, error=%d\n", in gli_pcie_enable_msi()
586 mmc_hostname(slot->host->mmc), ret); in gli_pcie_enable_msi()
590 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); in gli_pcie_enable_msi()
670 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) in gl9755_set_ssc() argument
673 u32 ssc; in gl9755_set_ssc() local
677 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); in gl9755_set_ssc()
680 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; in gl9755_set_ssc()
682 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); in gl9755_set_ssc()
683 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); in gl9755_set_ssc()
684 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); in gl9755_set_ssc()
691 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_205mhz() local
693 /* set pll to 205MHz and ssc */ in gl9755_set_ssc_pll_205mhz()
694 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); in gl9755_set_ssc_pll_205mhz()
700 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_100mhz() local
702 /* set pll to 100MHz and ssc */ in gl9755_set_ssc_pll_100mhz()
703 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); in gl9755_set_ssc_pll_100mhz()
709 bool enable = gl9755_ssc_enable(pdev); in gl9755_set_ssc_pll_50mhz() local
711 /* set pll to 50MHz and ssc */ in gl9755_set_ssc_pll_50mhz()
712 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); in gl9755_set_ssc_pll_50mhz()
719 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9755_set_clock()
723 pdev = slot->chip->pdev; in sdhci_gl9755_set_clock()
724 host->mmc->actual_clock = 0; in sdhci_gl9755_set_clock()
732 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9755_set_clock()
733 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9755_set_clock()
734 host->mmc->actual_clock = 205000000; in sdhci_gl9755_set_clock()
747 struct pci_dev *pdev = slot->chip->pdev; in gl9755_hw_setting()
757 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) in gl9755_hw_setting()
759 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) in gl9755_hw_setting()
765 /* enable short circuit protection */ in gl9755_hw_setting()
829 u8 enable; in gl9767_ssc_enable() local
834 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value); in gl9767_ssc_enable()
838 return enable; in gl9767_ssc_enable()
841 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) in gl9767_set_ssc() argument
844 u32 ssc; in gl9767_set_ssc() local
849 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); in gl9767_set_ssc()
852 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; in gl9767_set_ssc()
854 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable); in gl9767_set_ssc()
855 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); in gl9767_set_ssc()
856 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); in gl9767_set_ssc()
885 bool enable = gl9767_ssc_enable(pdev); in gl9767_set_ssc_pll_205mhz() local
887 /* set pll to 205MHz and ssc */ in gl9767_set_ssc_pll_205mhz()
888 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3); in gl9767_set_ssc_pll_205mhz()
905 static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable) in gl9767_set_low_power_negotiation() argument
912 if (enable) in gl9767_set_low_power_negotiation()
924 struct mmc_ios *ios = &host->mmc->ios; in sdhci_gl9767_set_clock()
928 pdev = slot->chip->pdev; in sdhci_gl9767_set_clock()
929 host->mmc->actual_clock = 0; in sdhci_gl9767_set_clock()
940 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); in sdhci_gl9767_set_clock()
941 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { in sdhci_gl9767_set_clock()
942 host->mmc->actual_clock = 205000000; in sdhci_gl9767_set_clock()
961 struct pci_dev *pdev = slot->chip->pdev; in gl9767_hw_setting()
1007 pdev = slot->chip->pdev; in gl9767_init_sd_express()
1009 if (mmc->ops->get_ro(mmc)) { in gl9767_init_sd_express()
1010 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1070 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); in gl9767_init_sd_express()
1091 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9750()
1095 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9750()
1103 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9755()
1107 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9755()
1115 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9767()
1120 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; in gli_probe_slot_gl9767()
1121 host->mmc->caps2 |= MMC_CAP2_SD_EXP; in gli_probe_slot_gl9767()
1122 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; in gli_probe_slot_gl9767()
1134 * (6) Set 1.8V Signal Enable in the Host Control 2 register. in sdhci_gli_voltage_switch()
1137 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gli_voltage_switch()
1140 * Wait 5ms after set 1.8V signal enable in Host Control 2 register in sdhci_gli_voltage_switch()
1141 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. in sdhci_gli_voltage_switch()
1157 * (6) Set 1.8V Signal Enable in the Host Control 2 register. in sdhci_gl9767_voltage_switch()
1160 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to in sdhci_gl9767_voltage_switch()
1163 * Wait 5ms after set 1.8V signal enable in Host Control 2 register in sdhci_gl9767_voltage_switch()
1164 * to ensure 1.8V signal enable bit is set by GL9767. in sdhci_gl9767_voltage_switch()
1180 value = readl(host->ioaddr + reg); in sdhci_gl9750_readl()
1194 if (ios->enhanced_strobe) in gl9763e_hs400_enhanced_strobe()
1203 bool enable) in gl9763e_set_low_power_negotiation() argument
1205 struct pci_dev *pdev = slot->chip->pdev; in gl9763e_set_low_power_negotiation()
1215 if (enable) in gl9763e_set_low_power_negotiation()
1254 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_pre_enable()
1278 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_gl9763e_cqhci_irq()
1286 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_gl9763e_cqe_post_disable()
1296 .enable = sdhci_gl9763e_cqe_enable,
1305 struct device *dev = &slot->chip->pdev->dev; in gl9763e_add_host()
1306 struct sdhci_host *host = slot->host; in gl9763e_add_host()
1317 ret = -ENOMEM; in gl9763e_add_host()
1321 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; in gl9763e_add_host()
1322 cq_host->ops = &sdhci_gl9763e_cqhci_ops; in gl9763e_add_host()
1324 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in gl9763e_add_host()
1326 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in gl9763e_add_host()
1328 ret = cqhci_init(cq_host, host->mmc, dma64); in gl9763e_add_host()
1348 struct pci_dev *pdev = slot->chip->pdev; in gli_set_gl9763e()
1384 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_suspend()
1385 struct sdhci_host *host = slot->host; in gl9763e_runtime_suspend()
1388 /* Enable LPM negotiation to allow entering L1 state */ in gl9763e_runtime_suspend()
1400 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_runtime_resume()
1401 struct sdhci_host *host = slot->host; in gl9763e_runtime_resume()
1404 if (host->mmc->ios.power_mode != MMC_POWER_ON) in gl9763e_runtime_resume()
1417 mmc_hostname(host->mmc)); in gl9763e_runtime_resume()
1434 struct sdhci_pci_slot *slot = chip->slots[0]; in sdhci_pci_gli_resume()
1436 pci_free_irq_vectors(slot->chip->pdev); in sdhci_pci_gli_resume()
1444 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_resume()
1451 ret = cqhci_resume(slot->host->mmc); in gl9763e_resume()
1466 struct sdhci_pci_slot *slot = chip->slots[0]; in gl9763e_suspend()
1470 * Certain SoCs can suspend only with the bus in low- in gl9763e_suspend()
1472 * Re-enable LPM negotiation to allow entering L1 state in gl9763e_suspend()
1477 ret = cqhci_suspend(slot->host->mmc); in gl9763e_suspend()
1481 ret = sdhci_suspend_host(slot->host); in gl9763e_suspend()
1488 cqhci_resume(slot->host->mmc); in gl9763e_suspend()
1497 struct pci_dev *pdev = slot->chip->pdev; in gli_probe_slot_gl9763e()
1498 struct sdhci_host *host = slot->host; in gli_probe_slot_gl9763e()
1501 host->mmc->caps |= MMC_CAP_8_BIT_DATA | in gli_probe_slot_gl9763e()
1504 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | in gli_probe_slot_gl9763e()
1513 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in gli_probe_slot_gl9763e()
1516 host->mmc_host_ops.hs400_enhanced_strobe = in gli_probe_slot_gl9763e()
1528 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readw()
1537 u32 val = readl(host->ioaddr + (reg & ~3)); in sdhci_gli_readb()