Lines Matching +full:0 +full:x40d
12 #define MT7530_ALL_MEMBERS 0xff
18 ID_MT7530 = 0,
26 #define TRGMII_BASE(x) (0x10000 + (x))
29 #define ETHSYS_CLKCFG0 0x2c
32 #define SYSC_REG_RSTCTRL 0x34
36 #define MT753X_AGC 0xc
40 #define MT7530_MFC 0x10
41 #define BC_FFP(x) (((x) & 0xff) << 24)
42 #define BC_FFP_MASK BC_FFP(~0)
43 #define UNM_FFP(x) (((x) & 0xff) << 16)
44 #define UNM_FFP_MASK UNM_FFP(~0)
45 #define UNU_FFP(x) (((x) & 0xff) << 8)
46 #define UNU_FFP_MASK UNU_FFP(~0)
49 #define CPU_MASK (0xf << 4)
51 #define MIRROR_PORT(x) ((x) & 0x7)
52 #define MIRROR_MASK 0x7
55 #define MT7531_CFC 0x4
60 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
71 #define MT753X_BPC 0x24
79 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
82 #define MT753X_RGAC1 0x28
91 #define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
93 /* Register for :03 and :0E MAC DA frame control */
94 #define MT753X_RGAC2 0x2c
103 #define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
114 #define MT7530_ATA1 0x74
115 #define STATIC_EMP 0
117 #define MT7530_ATA2 0x78
119 #define ATA2_FID(x) (((x) & 0x7) << 12)
122 #define MT7530_ATWD 0x7c
125 #define MT7530_ATC 0x80
126 #define ATC_HASH (((x) & 0xfff) << 16)
131 #define ATC_MAT(x) (((x) & 0xf) << 8)
132 #define ATC_MAT_MACTAB ATC_MAT(0)
135 MT7530_FDB_READ = 0,
143 #define MT7530_TSRA1 0x84
147 #define MAC_BYTE_3 0
148 #define MAC_BYTE_MASK 0xff
150 #define MT7530_TSRA2 0x88
153 #define CVID 0
154 #define CVID_MASK 0xfff
156 #define MT7530_ATRD 0x8C
158 #define AGE_TIMER_MASK 0xff
160 #define PORT_MAP_MASK 0xff
162 #define ENT_STATUS_MASK 0x3
165 #define MT7530_VTCR 0x90
168 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
169 #define VTCR_VID ((x) & 0xfff)
175 MT7530_VTCR_RD_VID = 0,
180 #define MT7530_VAWD1 0x94
189 #define PORT_MEM(x) (((x) & 0xff) << 16)
191 #define FID(x) (((x) & 0x7) << 1)
193 #define VLAN_VALID BIT(0)
195 #define PORT_MEM_MASK 0xff
198 FID_STANDALONE = 0,
202 #define MT7530_VAWD2 0x98
204 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
208 MT7530_VLAN_EGRESS_UNTAG = 0,
214 #define MT7530_AAC 0xa0
219 #define AGE_CNT_MAX 0xff
222 #define AGE_UNIT_MASK GENMASK(11, 0)
223 #define AGE_UNIT_MAX 0xfff
227 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
228 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
229 #define FID_PST_MASK(fid) FID_PST(fid, 0x3)
232 MT7530_STP_DISABLED = 0,
240 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
243 #define PORT_VLAN(x) ((x) & 0x3)
247 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
261 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
262 #define PORT_PRI(x) (((x) & 0x7) << 24)
263 #define EG_TAG(x) (((x) & 0x3) << 28)
264 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
265 #define PCR_MATRIX_CLR PCR_MATRIX(0)
269 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
273 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
275 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
277 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
279 #define ACC_FRM_MASK GENMASK(1, 0)
282 MT7530_VLAN_EG_DISABLED = 0,
288 MT7530_VLAN_USER = 0,
293 MT7530_VLAN_ACC_ALL = 0,
298 #define STAG_VPID (((x) & 0xffff) << 16)
301 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
302 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
303 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
304 #define G0_PORT_VID_DEF G0_PORT_VID(0)
307 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
308 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
323 #define PMCR_FORCE_LNK BIT(0)
351 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
352 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
353 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
358 #define LPI_MODE_EN BIT(0)
360 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
367 #define PMSR_SPEED_10 0x00
370 #define PMSR_LINK BIT(0)
373 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
376 #define MT7530_GMACCR 0x30e0
379 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
380 #define MAX_RX_PKT_LEN_1522 0x0
381 #define MAX_RX_PKT_LEN_1536 0x1
382 #define MAX_RX_PKT_LEN_1552 0x2
383 #define MAX_RX_PKT_LEN_JUMBO 0x3
386 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
387 #define MT7530_MIB_CCR 0x4fe0
404 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
405 #define MT7531_PHYA_CTRL_SIGNAL3 0x128
408 #define MT7530_SYS_CTRL 0x7000
411 #define SYS_CTRL_REG_RST BIT(0)
414 #define MT7530_SYS_INT_EN 0x7008
417 #define MT7530_SYS_INT_STS 0x700c
420 #define MT7531_PHY_IAC 0x701C
422 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
423 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
424 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
425 #define MT7531_MDIO_ST_MASK (0x3 << 16)
426 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
427 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
428 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
429 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
430 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
431 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
434 MT7531_MDIO_ADDR = 0,
442 MT7531_MDIO_ST_CL45 = 0,
458 #define MT7531_CLKGEN_CTRL 0x7500
459 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
461 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
465 #define GP_MODE(x) (((x) & 0x3) << 1)
467 #define GP_CLK_EN BIT(0)
470 MT7531_GP_MODE_RGMII = 0,
476 MT7531_CLK_SKEW_NO_CHG = 0,
483 #define MT7530_HWTRAP 0x7800
489 #define MT7531_HWTRAP 0x7800
492 #define HWTRAP_XTAL_FSEL_40MHZ 0
500 #define MT7530_MHWTRAP 0x7804
510 #define MT7530_TOP_SIG_CTRL 0x7808
513 #define MT7531_TOP_SIG_SR 0x780c
515 #define PAD_MCM_SMI_EN BIT(0)
517 #define MT7530_IO_DRV_CR 0x7810
518 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
519 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
521 #define MT7531_CHIP_REV 0x781C
523 #define MT7531_PLLGP_EN 0x7820
526 #define SW_PLLGP BIT(0)
528 #define MT7530_P6ECR 0x7830
529 #define P6_INTF_MODE_MASK 0x3
530 #define P6_INTF_MODE(x) ((x) & 0x3)
532 #define MT7531_PLLGP_CR0 0x78a8
535 #define RG_COREPLL_POSDIV_M 0x3800000
537 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
538 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
541 #define MT7531_ANA_PLLGP_CR2 0x78b0
542 #define MT7531_ANA_PLLGP_CR5 0x78bc
545 #define MT7530_TRGMII_RCK_CTRL 0x7a00
548 #define DQSI1_TAP_MASK (0x7f << 8)
549 #define DQSI0_TAP_MASK 0x7f
550 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
551 #define DQSI0_TAP(x) ((x) & 0x7f)
553 #define MT7530_TRGMII_RCK_RTT 0x7a04
557 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
560 #define RD_TAP_MASK 0x7f
561 #define RD_TAP(x) ((x) & 0x7f)
563 #define MT7530_TRGMII_TXCTRL 0x7a40
568 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
569 #define TD_DM_DRVP(x) ((x) & 0xf)
570 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
572 #define MT7530_TRGMII_TCK_CTRL 0x7a78
573 #define TCK_TAP(x) (((x) & 0xf) << 8)
575 #define MT7530_P5RGMIIRXCR 0x7b00
577 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
579 #define MT7530_P5RGMIITXCR 0x7b04
580 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
583 #define MT7531_GPIO_MODE0 0x7c0c
584 #define MT7531_GPIO0_MASK GENMASK(3, 0)
587 #define MT7531_GPIO_MODE1 0x7c10
595 * [ 2: 0] port 0
602 /* LED enable, 0: Disable, 1: Enable (Default) */
603 #define MT7530_LED_EN 0x7d00
604 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
605 #define MT7530_LED_IO_MODE 0x7d04
606 /* GPIO direction, 0: Input, 1: Output */
607 #define MT7530_LED_GPIO_DIR 0x7d10
608 /* GPIO output enable, 0: Disable, 1: Enable */
609 #define MT7530_LED_GPIO_OE 0x7d14
610 /* GPIO value, 0: Low, 1: High */
611 #define MT7530_LED_GPIO_DATA 0x7d18
613 #define MT7530_CREV 0x7ffc
615 #define MT7530_ID 0x7530
617 #define MT7531_CREV 0x781C
618 #define CHIP_REV_M 0x0f
619 #define MT7531_ID 0x7531
622 #define CORE_PLL_GROUP2 0x401
626 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
628 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
629 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
631 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
633 #define CORE_PLL_GROUP4 0x403
641 #define MT753X_CTRL_PHY_ADDR 0
643 #define CORE_PLL_GROUP5 0x404
644 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
646 #define CORE_PLL_GROUP6 0x405
647 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
649 #define CORE_PLL_GROUP7 0x406
652 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
655 #define CORE_PLL_GROUP10 0x409
656 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
658 #define CORE_PLL_GROUP11 0x40a
659 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
661 #define CORE_GSWPLL_GRP1 0x40d
662 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
663 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
668 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
670 #define CORE_GSWPLL_GRP2 0x40e
671 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
672 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
674 #define CORE_TRGMII_GSW_CLK_CG 0x410
675 #define REG_GSWCK_EN BIT(0)
716 P5_DISABLED = 0,