73  * and another 16 bytes to allow us to align the dma command
74  * buffers on a 16 byte boundary.
307     out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);  in dbdma_reset()
321     volatile struct mace __iomem *mb = mp->mace;  in mace_reset()  local
327 	out_8(&mb->biucc, SWRST);  in mace_reset()
328 	if (in_8(&mb->biucc) & SWRST) {  in mace_reset()
339     out_8(&mb->imr, 0xff);	/* disable all intrs for now */  in mace_reset()
340     i = in_8(&mb->ir);  in mace_reset()
341     out_8(&mb->maccc, 0);	/* turn off tx, rx */  in mace_reset()
343     out_8(&mb->biucc, XMTSP_64);  in mace_reset()
344     out_8(&mb->utr, RTRD);  in mace_reset()
345     out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);  in mace_reset()
346     out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */  in mace_reset()
347     out_8(&mb->rcvfc, 0);  in mace_reset()
354 	out_8(&mb->iac, LOGADDR);  in mace_reset()
356 	out_8(&mb->iac, ADDRCHG | LOGADDR);  in mace_reset()
357 	while ((in_8(&mb->iac) & ADDRCHG) != 0)  in mace_reset()
361 	out_8(&mb->ladrf, 0);  in mace_reset()
365 	out_8(&mb->iac, 0);  in mace_reset()
368 	out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);  in mace_reset()
370 	out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);  in mace_reset()
376     volatile struct mace __iomem *mb = mp->mace;  in __mace_set_address()  local
383 	out_8(&mb->iac, PHYADDR);  in __mace_set_address()
385 	out_8(&mb->iac, ADDRCHG | PHYADDR);  in __mace_set_address()
386 	while ((in_8(&mb->iac) & ADDRCHG) != 0)  in __mace_set_address()
390         out_8(&mb->padr, macaddr[i] = p[i]);  in __mace_set_address()
395         out_8(&mb->iac, 0);  in __mace_set_address()
401     volatile struct mace __iomem *mb = mp->mace;  in mace_set_address()  local
409     out_8(&mb->maccc, mp->maccc);  in mace_set_address()
436     volatile struct mace __iomem *mb = mp->mace;  in mace_open()  local
477     out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */  in mace_open()
479     out_le32(&rd->control, (RUN << 16) | RUN);  in mace_open()
487     out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);  in mace_open()
496     out_8(&mb->maccc, mp->maccc);  in mace_open()
498     out_8(&mb->imr, RCVINT);  in mace_open()
506     volatile struct mace __iomem *mb = mp->mace;  in mace_close()  local
511     out_8(&mb->maccc, 0);  in mace_close()
512     out_8(&mb->imr, 0xff);		/* disable all intrs */  in mace_close()
515     rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */  in mace_close()
516     td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */  in mace_close()
576 	out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));  in mace_xmit_start()
592     volatile struct mace __iomem *mb = mp->mace;  in mace_set_multicast()  local
625 	    out_8(&mb->iac, LOGADDR);  in mace_set_multicast()
627 	    out_8(&mb->iac, ADDRCHG | LOGADDR);  in mace_set_multicast()
628 	    while ((in_8(&mb->iac) & ADDRCHG) != 0)  in mace_set_multicast()
632 	    out_8(&mb->ladrf, multicast_filter[i]);  in mace_set_multicast()
634 	    out_8(&mb->iac, 0);  in mace_set_multicast()
637     out_8(&mb->maccc, mp->maccc);  in mace_set_multicast()
643     volatile struct mace __iomem *mb = mp->mace;  in mace_handle_misc_intrs()  local
648     dev->stats.rx_missed_errors += in_8(&mb->mpc);   /* reading clears it */  in mace_handle_misc_intrs()
651     dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */  in mace_handle_misc_intrs()
666     volatile struct mace __iomem *mb = mp->mace;  in mace_interrupt()  local
675     intr = in_8(&mb->ir);		/* read interrupt register */  in mace_interrupt()
676     in_8(&mb->xmtrc);			/* get retries */  in mace_interrupt()
680     while (in_8(&mb->pr) & XMTSV) {  in mace_interrupt()
688 	intr = in_8(&mb->ir);  in mace_interrupt()
692 	    fs = in_8(&mb->xmtfs);  in mace_interrupt()
694 	    out_8(&mb->xmtfc, AUTO_PAD_XMIT);  in mace_interrupt()
699 	out_le32(&td->control, RUN << 16);  in mace_interrupt()
704 	xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;  in mace_interrupt()
717 	    out_8(&mb->xmtfc, DXMTFCS);  in mace_interrupt()
719 	fs = in_8(&mb->xmtfs);  in mace_interrupt()
737 	    x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;  in mace_interrupt()
749 		out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);  in mace_interrupt()
750 		out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);  in mace_interrupt()
752 		out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);  in mace_interrupt()
753 		out_8(&mb->xmtfc, AUTO_PAD_XMIT);  in mace_interrupt()
801 	out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));  in mace_interrupt()
812     volatile struct mace __iomem *mb = mp->mace;  in mace_tx_timeout()  local
825     mace_handle_misc_intrs(mp, in_8(&mb->ir), dev);  in mace_tx_timeout()
830     out_8(&mb->maccc, 0);  in mace_tx_timeout()
840     out_le32(&rd->control, (RUN << 16) | RUN);  in mace_tx_timeout()
861 	out_le32(&td->control, (RUN << 16) | RUN);  in mace_tx_timeout()
867     out_8(&mb->imr, RCVINT);  in mace_tx_timeout()
868     out_8(&mb->maccc, mp->maccc);  in mace_tx_timeout()
975 	    out_le32(&rd->control, (PAUSE << 16) | PAUSE);  in mace_rxdma_intr()
983 	out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));  in mace_rxdma_intr()