Lines Matching +full:ext +full:- +full:reset +full:- +full:output
1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
28 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
29 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
30 #define ERR_RES 0x30 /* Error Reset */
31 #define RES_H_IUS 0x38 /* Reset highest IUS */
33 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
34 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
35 #define RES_EOM_L 0xC0 /* Reset EOM latch */
39 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
112 #define NORESET 0 /* No reset on write to R9 */
113 #define CHRB 0x40 /* Reset channel B */
114 #define CHRA 0x80 /* Reset channel A */
115 #define FHWRES 0xc0 /* Force hardware reset */
130 #define TRxCXT 0 /* TRxC = Xtal output */
132 #define TRxCBR 2 /* TRxC = BR Generator Output */
133 #define TRxCDP 3 /* TRxC = DPLL output */
137 #define TCBR 0x10 /* Transmit clock = BR Generator output */
138 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
141 #define RCBR 0x40 /* Receive clock = BR Generator output */
142 #define RCDPLL 0x60 /* Receive clock = DPLL output */
156 #define RMC 0x40 /* Reset missing clock */
199 /* Read Register 2 (channel b only) - Interrupt vector */
202 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
205 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
227 #define AUTOEOM 0x02 /* Auto EOM Latch Reset */