Lines Matching +full:0 +full:x3e3
33 #define REG_EXT_CTRL 0x100 /* RW External LNA/PA and internal PA control */
34 #define REG_TX_FSK_TEST 0x101 /* RW TX FSK test mode configuration */
35 #define REG_CCA1 0x105 /* RW RSSI threshold for CCA */
36 #define REG_CCA2 0x106 /* RW CCA mode configuration */
37 #define REG_BUFFERCFG 0x107 /* RW RX_BUFFER overwrite control */
38 #define REG_PKT_CFG 0x108 /* RW FCS evaluation configuration */
39 #define REG_DELAYCFG0 0x109 /* RW RC_RX command to SFD or sync word delay */
40 #define REG_DELAYCFG1 0x10A /* RW RC_TX command to TX state */
41 #define REG_DELAYCFG2 0x10B /* RW Mac delay extension */
42 #define REG_SYNC_WORD0 0x10C /* RW sync word bits [7:0] of [23:0] */
43 #define REG_SYNC_WORD1 0x10D /* RW sync word bits [15:8] of [23:0] */
44 #define REG_SYNC_WORD2 0x10E /* RW sync word bits [23:16] of [23:0] */
45 #define REG_SYNC_CONFIG 0x10F /* RW sync word configuration */
46 #define REG_RC_CFG 0x13E /* RW RX / TX packet configuration */
47 #define REG_RC_VAR44 0x13F /* RW RESERVED */
48 #define REG_CH_FREQ0 0x300 /* RW Channel Frequency Settings - Low */
49 #define REG_CH_FREQ1 0x301 /* RW Channel Frequency Settings - Middle */
50 #define REG_CH_FREQ2 0x302 /* RW Channel Frequency Settings - High */
51 #define REG_TX_FD 0x304 /* RW TX Frequency Deviation Register */
52 #define REG_DM_CFG0 0x305 /* RW RX Discriminator BW Register */
53 #define REG_TX_M 0x306 /* RW TX Mode Register */
54 #define REG_RX_M 0x307 /* RW RX Mode Register */
55 #define REG_RRB 0x30C /* R RSSI Readback Register */
56 #define REG_LRB 0x30D /* R Link Quality Readback Register */
57 #define REG_DR0 0x30E /* RW bits [15:8] of [15:0] data rate setting */
58 #define REG_DR1 0x30F /* RW bits [7:0] of [15:0] data rate setting */
59 #define REG_PRAMPG 0x313 /* RW RESERVED */
60 #define REG_TXPB 0x314 /* RW TX Packet Storage Base Address */
61 #define REG_RXPB 0x315 /* RW RX Packet Storage Base Address */
62 #define REG_TMR_CFG0 0x316 /* RW Wake up Timer Conf Register - High */
63 #define REG_TMR_CFG1 0x317 /* RW Wake up Timer Conf Register - Low */
64 #define REG_TMR_RLD0 0x318 /* RW Wake up Timer Value Register - High */
65 #define REG_TMR_RLD1 0x319 /* RW Wake up Timer Value Register - Low */
66 #define REG_TMR_CTRL 0x31A /* RW Wake up Timer Timeout flag */
67 #define REG_PD_AUX 0x31E /* RW Battmon enable */
68 #define REG_GP_CFG 0x32C /* RW GPIO Configuration */
69 #define REG_GP_OUT 0x32D /* RW GPIO Configuration */
70 #define REG_GP_IN 0x32E /* R GPIO Configuration */
71 #define REG_SYNT 0x335 /* RW bandwidth calibration timers */
72 #define REG_CAL_CFG 0x33D /* RW Calibration Settings */
73 #define REG_PA_BIAS 0x36E /* RW PA BIAS */
74 #define REG_SYNT_CAL 0x371 /* RW Oscillator and Doubler Configuration */
75 #define REG_IIRF_CFG 0x389 /* RW BB Filter Decimation Rate */
76 #define REG_CDR_CFG 0x38A /* RW CDR kVCO */
77 #define REG_DM_CFG1 0x38B /* RW Postdemodulator Filter */
78 #define REG_AGCSTAT 0x38E /* R RXBB Ref Osc Calibration Engine Readback */
79 #define REG_RXCAL0 0x395 /* RW RX BB filter tuning, LSB */
80 #define REG_RXCAL1 0x396 /* RW RX BB filter tuning, MSB */
81 #define REG_RXFE_CFG 0x39B /* RW RXBB Ref Osc & RXFE Calibration */
82 #define REG_PA_RR 0x3A7 /* RW Set PA ramp rate */
83 #define REG_PA_CFG 0x3A8 /* RW PA enable */
84 #define REG_EXTPA_CFG 0x3A9 /* RW External PA BIAS DAC */
85 #define REG_EXTPA_MSC 0x3AA /* RW PA Bias Mode */
86 #define REG_ADC_RBK 0x3AE /* R Readback temp */
87 #define REG_AGC_CFG1 0x3B2 /* RW GC Parameters */
88 #define REG_AGC_MAX 0x3B4 /* RW Slew rate */
89 #define REG_AGC_CFG2 0x3B6 /* RW RSSI Parameters */
90 #define REG_AGC_CFG3 0x3B7 /* RW RSSI Parameters */
91 #define REG_AGC_CFG4 0x3B8 /* RW RSSI Parameters */
92 #define REG_AGC_CFG5 0x3B9 /* RW RSSI & NDEC Parameters */
93 #define REG_AGC_CFG6 0x3BA /* RW NDEC Parameters */
94 #define REG_OCL_CFG1 0x3C4 /* RW OCL System Parameters */
95 #define REG_IRQ1_EN0 0x3C7 /* RW Interrupt Mask set bits for IRQ1 */
96 #define REG_IRQ1_EN1 0x3C8 /* RW Interrupt Mask set bits for IRQ1 */
97 #define REG_IRQ2_EN0 0x3C9 /* RW Interrupt Mask set bits for IRQ2 */
98 #define REG_IRQ2_EN1 0x3CA /* RW Interrupt Mask set bits for IRQ2 */
99 #define REG_IRQ1_SRC0 0x3CB /* RW Interrupt Source bits for IRQ */
100 #define REG_IRQ1_SRC1 0x3CC /* RW Interrupt Source bits for IRQ */
101 #define REG_OCL_BW0 0x3D2 /* RW OCL System Parameters */
102 #define REG_OCL_BW1 0x3D3 /* RW OCL System Parameters */
103 #define REG_OCL_BW2 0x3D4 /* RW OCL System Parameters */
104 #define REG_OCL_BW3 0x3D5 /* RW OCL System Parameters */
105 #define REG_OCL_BW4 0x3D6 /* RW OCL System Parameters */
106 #define REG_OCL_BWS 0x3D7 /* RW OCL System Parameters */
107 #define REG_OCL_CFG13 0x3E0 /* RW OCL System Parameters */
108 #define REG_GP_DRV 0x3E3 /* RW I/O pads Configuration and bg trim */
109 #define REG_BM_CFG 0x3E6 /* RW Batt. Monitor Threshold Voltage setting */
110 #define REG_SFD_15_4 0x3F4 /* RW Option to set non standard SFD */
111 #define REG_AFC_CFG 0x3F7 /* RW AFC mode and polarity */
112 #define REG_AFC_KI_KP 0x3F8 /* RW AFC ki and kp */
113 #define REG_AFC_RANGE 0x3F9 /* RW AFC range */
114 #define REG_AFC_READ 0x3FA /* RW Readback frequency error */
117 #define PA_PWR(x) (((x) & 0xF) << 4)
119 #define EXTPA_BIAS_MODE(x) (((x) & 0x7) << 0)
122 #define PA_BRIDGE_DBIAS(x) (((x) & 0x1F) << 0)
127 #define PA_BIAS_CTRL(x) (((x) & 0x1F) << 1)
128 #define REG_PA_BIAS_DFL BIT(0)
132 #define REG_PAN_ID0 0x112
133 #define REG_PAN_ID1 0x113
134 #define REG_SHORT_ADDR_0 0x114
135 #define REG_SHORT_ADDR_1 0x115
136 #define REG_IEEE_ADDR_0 0x116
137 #define REG_IEEE_ADDR_1 0x117
138 #define REG_IEEE_ADDR_2 0x118
139 #define REG_IEEE_ADDR_3 0x119
140 #define REG_IEEE_ADDR_4 0x11A
141 #define REG_IEEE_ADDR_5 0x11B
142 #define REG_IEEE_ADDR_6 0x11C
143 #define REG_IEEE_ADDR_7 0x11D
144 #define REG_FFILT_CFG 0x11E
145 #define REG_AUTO_CFG 0x11F
146 #define REG_AUTO_TX1 0x120
147 #define REG_AUTO_TX2 0x121
148 #define REG_AUTO_STATUS 0x122
151 #define ACCEPT_BEACON_FRAMES BIT(0)
159 #define AUTO_ACK_FRAMEPEND BIT(0)
165 #define MAX_FRAME_RETRIES(x) ((x) & 0xF)
166 #define MAX_CCA_RETRIES(x) (((x) & 0x7) << 4)
169 #define CSMA_MAX_BE(x) ((x) & 0xF)
170 #define CSMA_MIN_BE(x) (((x) & 0xF) << 4)
172 #define CMD_SPI_NOP 0xFF /* No operation. Use for dummy writes */
173 #define CMD_SPI_PKT_WR 0x10 /* Write telegram to the Packet RAM
177 #define CMD_SPI_PKT_RD 0x30 /* Read telegram from the Packet RAM
181 #define CMD_SPI_MEM_WR(x) (0x18 + (x >> 8)) /* Write data to MCR or
184 #define CMD_SPI_MEM_RD(x) (0x38 + (x >> 8)) /* Read data from MCR or
187 #define CMD_SPI_MEMR_WR(x) (0x08 + (x >> 8)) /* Write data to MCR or Packet
190 #define CMD_SPI_MEMR_RD(x) (0x28 + (x >> 8)) /* Read data from MCR or
193 #define CMD_SPI_PRAM_WR 0x1E /* Write data sequentially to current
196 #define CMD_SPI_PRAM_RD 0x3E /* Read data sequentially from current
199 #define CMD_RC_SLEEP 0xB1 /* Invoke transition of radio controller
202 #define CMD_RC_IDLE 0xB2 /* Invoke transition of radio controller
205 #define CMD_RC_PHY_RDY 0xB3 /* Invoke transition of radio controller
208 #define CMD_RC_RX 0xB4 /* Invoke transition of radio controller
211 #define CMD_RC_TX 0xB5 /* Invoke transition of radio controller
214 #define CMD_RC_MEAS 0xB6 /* Invoke transition of radio controller
217 #define CMD_RC_CCA 0xB7 /* Invoke Clear channel assessment */
218 #define CMD_RC_CSMACA 0xC1 /* initiates CSMA-CA channel access
221 #define CMD_RC_PC_RESET 0xC7 /* Program counter reset */
222 #define CMD_RC_RESET 0xC8 /* Resets the ADF7242 and puts it in
238 #define RC_STATUS_MASK 0xF
242 #define SUCCESS 0
246 #define AUTO_STATUS_MASK 0x3
252 #define IRQ_CCA_COMPLETE BIT(0)
264 #define FLAG_XMIT 0
267 #define ADF7242_REPORT_CSMA_CA_STAT 0 /* framework doesn't handle yet */
318 int cnt = 0, ret = 0; in adf7242_wait_status()
334 ret = 0; in adf7242_wait_status()
337 if (ret < 0) in adf7242_wait_status()
339 "%s:line %d Timeout status 0x%x (%d)\n", in adf7242_wait_status()
382 buf[0] = CMD_SPI_PKT_WR; in adf7242_write_fbuf()
415 buf[0] = CMD_SPI_PKT_RD; in adf7242_read_fbuf()
417 buf[2] = 0; /* PHR */ in adf7242_read_fbuf()
419 buf[0] = CMD_SPI_PRAM_RD; in adf7242_read_fbuf()
420 buf[1] = 0; in adf7242_read_fbuf()
445 lp->buf_read_tx[0] = CMD_SPI_MEM_RD(addr); in adf7242_read_reg()
462 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", __func__, in adf7242_read_reg()
475 lp->buf_reg_tx[0] = CMD_SPI_MEM_WR(addr); in adf7242_write_reg()
481 dev_vdbg(&lp->spi->dev, "%s : REG 0x%X, VAL 0x%X\n", in adf7242_write_reg()
491 dev_vdbg(&lp->spi->dev, "%s : CMD=0x%X\n", __func__, cmd); in adf7242_cmd()
508 int status, i, page = 0; in adf7242_upload_firmware()
516 buf[0] = CMD_SPI_PRAM_WR; in adf7242_upload_firmware()
517 buf[1] = 0; in adf7242_upload_firmware()
523 for (i = len; i >= 0; i -= PRAM_PAGESIZE) { in adf7242_upload_firmware()
549 for (page = 0, i = len; i >= 0; i -= PRAM_PAGESIZE, page++) { in adf7242_verify_firmware()
555 for (j = 0; j < nb; j++) { in adf7242_verify_firmware()
564 return 0; in adf7242_verify_firmware()
623 tmp &= ~PA_BRIDGE_DBIAS(~0); in adf7242_set_txpower()
628 tmp &= ~PA_BIAS_CTRL(~0); in adf7242_set_txpower()
633 tmp &= ~PA_PWR(~0); in adf7242_set_txpower()
668 int ret = 0; in adf7242_set_frame_retries()
675 if (retries >= 0) in adf7242_set_frame_retries()
694 return 0; in adf7242_ed()
729 WARN_ON(page != 0); in adf7242_channel()
753 dev_dbg(&lp->spi->dev, "%s :Changed=0x%lX\n", __func__, changed); in adf7242_set_hw_addr_filt()
762 for (i = 0; i < 8; i++) in adf7242_set_hw_addr_filt()
789 return 0; in adf7242_set_hw_addr_filt()
801 adf7242_write_reg(lp, REG_AUTO_CFG, 0); in adf7242_set_promiscuous_mode()
854 if (ret < 0) in adf7242_xmit()
856 if (ret == 0) { in adf7242_xmit()
864 "Error xmit: Retry count exceeded Status=0x%x\n", in adf7242_xmit()
868 ret = 0; in adf7242_xmit()
885 ret = adf7242_read_reg(lp, 0, &len_u8); in adf7242_rx()
905 if (ret < 0) { in adf7242_rx()
965 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", in adf7242_debug()
966 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", in adf7242_debug()
967 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", in adf7242_debug()
968 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", in adf7242_debug()
969 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); in adf7242_debug()
983 dev_err(&lp->spi->dev, "%s :ERROR IRQ1 = 0x%X\n", in adf7242_isr()
1020 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X\n", in adf7242_isr()
1030 dev_dbg(&lp->spi->dev, "%s:%d : ERROR IRQ1 = 0x%X, xmit %d\n", in adf7242_isr()
1062 return 0; in adf7242_soft_reset()
1115 adf7242_write_reg(lp, REG_EXTPA_MSC, 0xF1); in adf7242_hw_init()
1116 adf7242_write_reg(lp, REG_RXFE_CFG, 0x1D); in adf7242_hw_init()
1118 adf7242_write_reg(lp, REG_IRQ1_EN0, 0); in adf7242_hw_init()
1122 adf7242_write_reg(lp, REG_IRQ1_SRC0, 0xFF); in adf7242_hw_init()
1126 return 0; in adf7242_hw_init()
1152 (stat & 0xf) == RC_STATUS_IDLE ? "RC_STATUS_IDLE" : "", in adf7242_stats_show()
1153 (stat & 0xf) == RC_STATUS_MEAS ? "RC_STATUS_MEAS" : "", in adf7242_stats_show()
1154 (stat & 0xf) == RC_STATUS_PHY_RDY ? "RC_STATUS_PHY_RDY" : "", in adf7242_stats_show()
1155 (stat & 0xf) == RC_STATUS_RX ? "RC_STATUS_RX" : "", in adf7242_stats_show()
1156 (stat & 0xf) == RC_STATUS_TX ? "RC_STATUS_TX" : ""); in adf7242_stats_show()
1160 return 0; in adf7242_stats_show()
1177 500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
1212 hw->extra_tx_headroom = 0; in adf7242_probe()
1215 hw->phy->supported.channels[0] = 0x7FFF800; in adf7242_probe()
1236 hw->phy->supported.min_minbe = 0; in adf7242_probe()
1242 hw->phy->supported.min_frame_retries = 0; in adf7242_probe()
1245 hw->phy->supported.min_csma_backoffs = 0; in adf7242_probe()