17 #define PHY_ID_ADIN1100				0x0283bc81
18 #define PHY_ID_ADIN1110				0x0283bc91
19 #define PHY_ID_ADIN2111				0x0283bca1
21 #define ADIN_FORCED_MODE			0x8000
22 #define   ADIN_FORCED_MODE_EN			BIT(0)
24 #define ADIN_CRSM_SFT_RST			0x8810
25 #define   ADIN_CRSM_SFT_RST_EN			BIT(0)
27 #define ADIN_CRSM_SFT_PD_CNTRL			0x8812
28 #define   ADIN_CRSM_SFT_PD_CNTRL_EN		BIT(0)
30 #define ADIN_AN_PHY_INST_STATUS			0x8030
34 #define ADIN_CRSM_STAT				0x8818
36 #define   ADIN_CRSM_SYS_RDY			BIT(0)
38 #define ADIN_MSE_VAL				0x830B
48 	{ 0x0A74, 0xFFFF },
49 	{ 0x084E, 0x0A74 },
50 	{ 0x0698, 0x084E },
51 	{ 0x053D, 0x0698 },
52 	{ 0x0429, 0x053D },
53 	{ 0x034E, 0x0429 },
54 	{ 0x02A0, 0x034E },
55 	{ 0x0000, 0x02A0 },
79 	if (ret < 0)  in adin_read_status()
88 	return 0;  in adin_read_status()
98 		if (ret < 0)  in adin_config_aneg()
107 		if (ret < 0)  in adin_config_aneg()
115 	if (ret < 0)  in adin_config_aneg()
123 		if (ret < 0)  in adin_config_aneg()
132 		if (ret < 0)  in adin_config_aneg()
144 	val = en ? ADIN_CRSM_SFT_PD_CNTRL_EN : 0;  in adin_set_powerdown_mode()
147 	if (ret < 0)  in adin_set_powerdown_mode()
181 	if (ret < 0)  in adin_soft_reset()
197 	if (ret < 0)  in adin_get_features()
209 		if (ret < 0)  in adin_get_features()
231 	if (ret < 0)  in adin_get_sqi()
234 		return 0;  in adin_get_sqi()
237 	if (ret < 0)  in adin_get_sqi()
240 	mse_val = 0xFFFF & ret;  in adin_get_sqi()
241 	for (sqi = 0; sqi < ARRAY_SIZE(adin_mse_sqi_map); sqi++) {  in adin_get_sqi()
265 	return 0;  in adin_probe()
271 		.phy_id_mask		= 0xffffffcf,