Lines Matching +full:pcie +full:- +full:5
1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
67 (GENMASK(7, 5) << ((b) * 8))
69 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
76 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
117 (((aperture) - 2) << ((bar) * 8))
144 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
147 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
149 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
157 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
161 /* Region r Outbound PCIe Descriptor Register 0 */
177 /* Region r Outbound PCIe Descriptor Register 1 */
187 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
189 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
195 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */
198 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
200 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
216 RP_BAR_UNDEFINED = -1,
230 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
237 #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
239 (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
279 int (*start_link)(struct cdns_pcie *pcie);
280 void (*stop_link)(struct cdns_pcie *pcie);
281 bool (*link_up)(struct cdns_pcie *pcie);
282 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
286 * struct cdns_pcie - private data for Cadence PCIe controller drivers
289 * @dev: PCIe controller
290 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
294 * @ops: Platform-specific ops to control various inputs from Cadence PCIe
309 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
310 * @pcie: Cadence PCIe controller
311 * @dev: pointer to PCIe device
320 * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2
324 struct cdns_pcie pcie; member
335 * struct cdns_pcie_epf - Structure to hold info about endpoint function
345 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
346 * @pcie: Cadence PCIe controller
354 * IRQ) TLP through the PCIe bus.
360 * @lock: spin lock to disable interrupts while modifying PCIe controller
368 struct cdns_pcie pcie; member
386 static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) in cdns_pcie_writel() argument
388 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
391 static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) in cdns_pcie_readl() argument
393 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
410 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); in cdns_pcie_read_sz()
430 mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); in cdns_pcie_write_sz()
437 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, in cdns_pcie_rp_writeb() argument
440 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writeb()
445 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, in cdns_pcie_rp_writew() argument
448 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writew()
453 static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) in cdns_pcie_rp_readw() argument
455 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_readw()
461 static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writeb() argument
464 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writeb()
469 static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writew() argument
472 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writew()
477 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writel() argument
480 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writel()
483 static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) in cdns_pcie_ep_fn_readw() argument
485 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_readw()
490 static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) in cdns_pcie_ep_fn_readl() argument
492 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_readl()
495 static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) in cdns_pcie_start_link() argument
497 if (pcie->ops->start_link) in cdns_pcie_start_link()
498 return pcie->ops->start_link(pcie); in cdns_pcie_start_link()
503 static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) in cdns_pcie_stop_link() argument
505 if (pcie->ops->stop_link) in cdns_pcie_stop_link()
506 pcie->ops->stop_link(pcie); in cdns_pcie_stop_link()
509 static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) in cdns_pcie_link_up() argument
511 if (pcie->ops->link_up) in cdns_pcie_link_up()
512 return pcie->ops->link_up(pcie); in cdns_pcie_link_up()
555 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
557 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
561 void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
565 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
566 void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
567 int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
568 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);