Lines Matching +full:pci +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
23 #include <linux/pci.h>
32 #include <linux/phy/phy.h>
36 #include "pcie-designware.h"
45 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
77 struct dw_pcie *pci; member
99 /* power domain for pcie phy */
101 struct phy *phy; member
105 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
109 /* PCIe Port Logic registers (memory-mapped) */
122 /* PHY registers (not memory-mapped) */
136 /* iMX7 PCIe PHY registers */
159 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && in imx6_pcie_grp_offset()
160 imx6_pcie->drvdata->variant != IMX8MQ_EP && in imx6_pcie_grp_offset()
161 imx6_pcie->drvdata->variant != IMX8MM && in imx6_pcie_grp_offset()
162 imx6_pcie->drvdata->variant != IMX8MM_EP && in imx6_pcie_grp_offset()
163 imx6_pcie->drvdata->variant != IMX8MP && in imx6_pcie_grp_offset()
164 imx6_pcie->drvdata->variant != IMX8MP_EP); in imx6_pcie_grp_offset()
165 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; in imx6_pcie_grp_offset()
172 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) in imx6_pcie_configure_type()
177 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_configure_type()
180 if (imx6_pcie->controller_id == 1) { in imx6_pcie_configure_type()
195 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); in imx6_pcie_configure_type()
200 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_poll_ack() local
206 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & in pcie_phy_poll_ack()
216 return -ETIMEDOUT; in pcie_phy_poll_ack()
221 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_wait_ack() local
226 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); in pcie_phy_wait_ack()
229 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); in pcie_phy_wait_ack()
236 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); in pcie_phy_wait_ack()
241 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
244 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_read() local
254 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); in pcie_phy_read()
260 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); in pcie_phy_read()
263 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); in pcie_phy_read()
270 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_write() local
281 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); in pcie_phy_write()
285 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); in pcie_phy_write()
293 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); in pcie_phy_write()
295 /* wait for ack de-assertion */ in pcie_phy_write()
302 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); in pcie_phy_write()
311 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); in pcie_phy_write()
313 /* wait for ack de-assertion */ in pcie_phy_write()
318 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); in pcie_phy_write()
325 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_init_phy()
331 * The PHY initialization had been done in the PHY in imx6_pcie_init_phy()
341 regmap_update_bits(imx6_pcie->iomuxc_gpr, in imx6_pcie_init_phy()
350 if (imx6_pcie->vph && in imx6_pcie_init_phy()
351 regulator_get_voltage(imx6_pcie->vph) > 3000000) in imx6_pcie_init_phy()
352 regmap_update_bits(imx6_pcie->iomuxc_gpr, in imx6_pcie_init_phy()
358 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
362 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
367 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
370 /* configure constant input signal to the pcie ctrl and phy */ in imx6_pcie_init_phy()
371 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
374 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
376 imx6_pcie->tx_deemph_gen1 << 0); in imx6_pcie_init_phy()
377 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
379 imx6_pcie->tx_deemph_gen2_3p5db << 6); in imx6_pcie_init_phy()
380 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
382 imx6_pcie->tx_deemph_gen2_6db << 12); in imx6_pcie_init_phy()
383 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
385 imx6_pcie->tx_swing_full << 18); in imx6_pcie_init_phy()
386 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
388 imx6_pcie->tx_swing_low << 25); in imx6_pcie_init_phy()
398 struct device *dev = imx6_pcie->pci->dev; in imx7d_pcie_wait_for_phy_pll_lock()
400 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, in imx7d_pcie_wait_for_phy_pll_lock()
415 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) in imx6_setup_phy_mpll()
418 for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) in imx6_setup_phy_mpll()
419 if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) in imx6_setup_phy_mpll()
420 phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); in imx6_setup_phy_mpll()
438 dev_err(imx6_pcie->pci->dev, in imx6_setup_phy_mpll()
439 "Unsupported PHY reference clock rate %lu\n", phy_rate); in imx6_setup_phy_mpll()
440 return -EINVAL; in imx6_setup_phy_mpll()
464 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) in imx6_pcie_reset_phy()
481 /* Added for PCI abort handling */
491 * make it look like it read all-ones. in imx6q_pcie_abort_handler()
499 val = -1; in imx6q_pcie_abort_handler()
501 regs->uregs[reg] = val; in imx6q_pcie_abort_handler()
502 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
507 regs->uregs[reg] = -1; in imx6q_pcie_abort_handler()
508 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
522 if (dev->pm_domain) in imx6_pcie_attach_pd()
525 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); in imx6_pcie_attach_pd()
526 if (IS_ERR(imx6_pcie->pd_pcie)) in imx6_pcie_attach_pd()
527 return PTR_ERR(imx6_pcie->pd_pcie); in imx6_pcie_attach_pd()
529 if (!imx6_pcie->pd_pcie) in imx6_pcie_attach_pd()
531 link = device_link_add(dev, imx6_pcie->pd_pcie, in imx6_pcie_attach_pd()
537 return -EINVAL; in imx6_pcie_attach_pd()
540 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); in imx6_pcie_attach_pd()
541 if (IS_ERR(imx6_pcie->pd_pcie_phy)) in imx6_pcie_attach_pd()
542 return PTR_ERR(imx6_pcie->pd_pcie_phy); in imx6_pcie_attach_pd()
544 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, in imx6_pcie_attach_pd()
550 return -EINVAL; in imx6_pcie_attach_pd()
561 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_enable_ref_clk()
563 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_enable_ref_clk()
568 /* power up core phy and enable ref clock */ in imx6_pcie_enable_ref_clk()
569 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_enable_ref_clk()
578 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_enable_ref_clk()
594 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, in imx6_pcie_enable_ref_clk()
597 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, in imx6_pcie_enable_ref_clk()
608 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_disable_ref_clk()
611 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_disable_ref_clk()
613 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_disable_ref_clk()
618 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_disable_ref_clk()
629 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_clk_enable() local
630 struct device *dev = pci->dev; in imx6_pcie_clk_enable()
633 ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); in imx6_pcie_clk_enable()
648 clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); in imx6_pcie_clk_enable()
656 clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); in imx6_pcie_clk_disable()
661 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_assert_core_reset()
665 reset_control_assert(imx6_pcie->pciephy_reset); in imx6_pcie_assert_core_reset()
671 reset_control_assert(imx6_pcie->apps_reset); in imx6_pcie_assert_core_reset()
674 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_assert_core_reset()
677 /* Force PCIe PHY reset */ in imx6_pcie_assert_core_reset()
678 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, in imx6_pcie_assert_core_reset()
683 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
688 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
690 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
696 if (gpio_is_valid(imx6_pcie->reset_gpio)) in imx6_pcie_assert_core_reset()
697 gpio_set_value_cansleep(imx6_pcie->reset_gpio, in imx6_pcie_assert_core_reset()
698 imx6_pcie->gpio_active_high); in imx6_pcie_assert_core_reset()
703 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_deassert_core_reset() local
704 struct device *dev = pci->dev; in imx6_pcie_deassert_core_reset()
706 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_deassert_core_reset()
709 reset_control_deassert(imx6_pcie->pciephy_reset); in imx6_pcie_deassert_core_reset()
712 reset_control_deassert(imx6_pcie->pciephy_reset); in imx6_pcie_deassert_core_reset()
714 /* Workaround for ERR010728, failure of PCI-e PLL VCO to in imx6_pcie_deassert_core_reset()
715 * oscillate, especially when cold. This turns off "Duty-cycle in imx6_pcie_deassert_core_reset()
718 if (likely(imx6_pcie->phy_base)) { in imx6_pcie_deassert_core_reset()
719 /* De-assert DCC_FB_EN */ in imx6_pcie_deassert_core_reset()
721 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); in imx6_pcie_deassert_core_reset()
725 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); in imx6_pcie_deassert_core_reset()
728 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); in imx6_pcie_deassert_core_reset()
730 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); in imx6_pcie_deassert_core_reset()
736 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, in imx6_pcie_deassert_core_reset()
740 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_deassert_core_reset()
754 if (gpio_is_valid(imx6_pcie->reset_gpio)) { in imx6_pcie_deassert_core_reset()
756 gpio_set_value_cansleep(imx6_pcie->reset_gpio, in imx6_pcie_deassert_core_reset()
757 !imx6_pcie->gpio_active_high); in imx6_pcie_deassert_core_reset()
767 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_wait_for_speed_change() local
768 struct device *dev = pci->dev; in imx6_pcie_wait_for_speed_change()
773 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); in imx6_pcie_wait_for_speed_change()
781 return -ETIMEDOUT; in imx6_pcie_wait_for_speed_change()
788 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_ltssm_enable()
792 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_ltssm_enable()
803 reset_control_deassert(imx6_pcie->apps_reset); in imx6_pcie_ltssm_enable()
812 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_ltssm_disable()
816 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_ltssm_disable()
826 reset_control_assert(imx6_pcie->apps_reset); in imx6_pcie_ltssm_disable()
831 static int imx6_pcie_start_link(struct dw_pcie *pci) in imx6_pcie_start_link() argument
833 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); in imx6_pcie_start_link()
834 struct device *dev = pci->dev; in imx6_pcie_start_link()
835 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); in imx6_pcie_start_link()
844 dw_pcie_dbi_ro_wr_en(pci); in imx6_pcie_start_link()
845 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); in imx6_pcie_start_link()
848 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); in imx6_pcie_start_link()
849 dw_pcie_dbi_ro_wr_dis(pci); in imx6_pcie_start_link()
854 ret = dw_pcie_wait_for_link(pci); in imx6_pcie_start_link()
858 if (pci->link_gen > 1) { in imx6_pcie_start_link()
860 dw_pcie_dbi_ro_wr_en(pci); in imx6_pcie_start_link()
861 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); in imx6_pcie_start_link()
863 tmp |= pci->link_gen; in imx6_pcie_start_link()
864 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); in imx6_pcie_start_link()
870 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); in imx6_pcie_start_link()
872 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); in imx6_pcie_start_link()
873 dw_pcie_dbi_ro_wr_dis(pci); in imx6_pcie_start_link()
875 if (imx6_pcie->drvdata->flags & in imx6_pcie_start_link()
880 * occurs and we go Gen1 -> yep, Gen1. The difference in imx6_pcie_start_link()
894 ret = dw_pcie_wait_for_link(pci); in imx6_pcie_start_link()
901 imx6_pcie->link_is_up = true; in imx6_pcie_start_link()
902 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); in imx6_pcie_start_link()
907 imx6_pcie->link_is_up = false; in imx6_pcie_start_link()
908 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", in imx6_pcie_start_link()
909 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), in imx6_pcie_start_link()
910 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); in imx6_pcie_start_link()
915 static void imx6_pcie_stop_link(struct dw_pcie *pci) in imx6_pcie_stop_link() argument
917 struct device *dev = pci->dev; in imx6_pcie_stop_link()
925 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in imx6_pcie_host_init() local
926 struct device *dev = pci->dev; in imx6_pcie_host_init()
927 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); in imx6_pcie_host_init()
930 if (imx6_pcie->vpcie) { in imx6_pcie_host_init()
931 ret = regulator_enable(imx6_pcie->vpcie); in imx6_pcie_host_init()
948 if (imx6_pcie->phy) { in imx6_pcie_host_init()
949 ret = phy_init(imx6_pcie->phy); in imx6_pcie_host_init()
951 dev_err(dev, "pcie PHY power up failed\n"); in imx6_pcie_host_init()
956 if (imx6_pcie->phy) { in imx6_pcie_host_init()
957 ret = phy_power_on(imx6_pcie->phy); in imx6_pcie_host_init()
959 dev_err(dev, "waiting for PHY ready timeout!\n"); in imx6_pcie_host_init()
975 phy_power_off(imx6_pcie->phy); in imx6_pcie_host_init()
977 phy_exit(imx6_pcie->phy); in imx6_pcie_host_init()
981 if (imx6_pcie->vpcie) in imx6_pcie_host_init()
982 regulator_disable(imx6_pcie->vpcie); in imx6_pcie_host_init()
988 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in imx6_pcie_host_exit() local
989 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); in imx6_pcie_host_exit()
991 if (imx6_pcie->phy) { in imx6_pcie_host_exit()
992 if (phy_power_off(imx6_pcie->phy)) in imx6_pcie_host_exit()
993 dev_err(pci->dev, "unable to power off PHY\n"); in imx6_pcie_host_exit()
994 phy_exit(imx6_pcie->phy); in imx6_pcie_host_exit()
998 if (imx6_pcie->vpcie) in imx6_pcie_host_exit()
999 regulator_disable(imx6_pcie->vpcie); in imx6_pcie_host_exit()
1015 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in imx6_pcie_ep_init() local
1018 dw_pcie_ep_reset_bar(pci, bar); in imx6_pcie_ep_init()
1025 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in imx6_pcie_ep_raise_irq() local
1035 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in imx6_pcie_ep_raise_irq()
1036 return -EINVAL; in imx6_pcie_ep_raise_irq()
1069 struct dw_pcie *pci = imx6_pcie->pci; in imx6_add_pcie_ep() local
1070 struct dw_pcie_rp *pp = &pci->pp; in imx6_add_pcie_ep()
1071 struct device *dev = pci->dev; in imx6_add_pcie_ep()
1074 ep = &pci->ep; in imx6_add_pcie_ep()
1075 ep->ops = &pcie_ep_ops; in imx6_add_pcie_ep()
1077 switch (imx6_pcie->drvdata->variant) { in imx6_add_pcie_ep()
1087 pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; in imx6_add_pcie_ep()
1090 return -EINVAL; in imx6_add_pcie_ep()
1092 ep->phys_base = res->start; in imx6_add_pcie_ep()
1093 ep->addr_size = resource_size(res); in imx6_add_pcie_ep()
1094 ep->page_size = SZ_64K; in imx6_add_pcie_ep()
1109 struct device *dev = imx6_pcie->pci->dev; in imx6_pcie_pm_turnoff()
1112 if (imx6_pcie->turnoff_reset) { in imx6_pcie_pm_turnoff()
1113 reset_control_assert(imx6_pcie->turnoff_reset); in imx6_pcie_pm_turnoff()
1114 reset_control_deassert(imx6_pcie->turnoff_reset); in imx6_pcie_pm_turnoff()
1119 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_pm_turnoff()
1122 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_pm_turnoff()
1125 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_pm_turnoff()
1137 * The standard recommends a 1-10ms timeout after which to in imx6_pcie_pm_turnoff()
1148 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_msi_save_restore() local
1151 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); in imx6_pcie_msi_save_restore()
1153 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); in imx6_pcie_msi_save_restore()
1154 imx6_pcie->msi_ctrl = val; in imx6_pcie_msi_save_restore()
1156 dw_pcie_dbi_ro_wr_en(pci); in imx6_pcie_msi_save_restore()
1157 val = imx6_pcie->msi_ctrl; in imx6_pcie_msi_save_restore()
1158 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); in imx6_pcie_msi_save_restore()
1159 dw_pcie_dbi_ro_wr_dis(pci); in imx6_pcie_msi_save_restore()
1167 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; in imx6_pcie_suspend_noirq()
1169 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx6_pcie_suspend_noirq()
1174 imx6_pcie_stop_link(imx6_pcie->pci); in imx6_pcie_suspend_noirq()
1184 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; in imx6_pcie_resume_noirq()
1186 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx6_pcie_resume_noirq()
1195 if (imx6_pcie->link_is_up) in imx6_pcie_resume_noirq()
1196 imx6_pcie_start_link(imx6_pcie->pci); in imx6_pcie_resume_noirq()
1208 struct device *dev = &pdev->dev; in imx6_pcie_probe()
1209 struct dw_pcie *pci; in imx6_pcie_probe() local
1213 struct device_node *node = dev->of_node; in imx6_pcie_probe()
1220 return -ENOMEM; in imx6_pcie_probe()
1222 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); in imx6_pcie_probe()
1223 if (!pci) in imx6_pcie_probe()
1224 return -ENOMEM; in imx6_pcie_probe()
1226 pci->dev = dev; in imx6_pcie_probe()
1227 pci->ops = &dw_pcie_ops; in imx6_pcie_probe()
1228 pci->pp.ops = &imx6_pcie_host_ops; in imx6_pcie_probe()
1230 imx6_pcie->pci = pci; in imx6_pcie_probe()
1231 imx6_pcie->drvdata = of_device_get_match_data(dev); in imx6_pcie_probe()
1233 /* Find the PHY if one is defined, only imx7d uses it */ in imx6_pcie_probe()
1234 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); in imx6_pcie_probe()
1240 dev_err(dev, "Unable to map PCIe PHY\n"); in imx6_pcie_probe()
1243 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); in imx6_pcie_probe()
1244 if (IS_ERR(imx6_pcie->phy_base)) in imx6_pcie_probe()
1245 return PTR_ERR(imx6_pcie->phy_base); in imx6_pcie_probe()
1248 pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); in imx6_pcie_probe()
1249 if (IS_ERR(pci->dbi_base)) in imx6_pcie_probe()
1250 return PTR_ERR(pci->dbi_base); in imx6_pcie_probe()
1253 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); in imx6_pcie_probe()
1254 imx6_pcie->gpio_active_high = of_property_read_bool(node, in imx6_pcie_probe()
1255 "reset-gpio-active-high"); in imx6_pcie_probe()
1256 if (gpio_is_valid(imx6_pcie->reset_gpio)) { in imx6_pcie_probe()
1257 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, in imx6_pcie_probe()
1258 imx6_pcie->gpio_active_high ? in imx6_pcie_probe()
1266 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { in imx6_pcie_probe()
1267 return imx6_pcie->reset_gpio; in imx6_pcie_probe()
1270 if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS) in imx6_pcie_probe()
1271 return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); in imx6_pcie_probe()
1273 for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) in imx6_pcie_probe()
1274 imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; in imx6_pcie_probe()
1277 ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); in imx6_pcie_probe()
1281 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_probe()
1284 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) in imx6_pcie_probe()
1285 imx6_pcie->controller_id = 1; in imx6_pcie_probe()
1288 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, in imx6_pcie_probe()
1290 if (IS_ERR(imx6_pcie->pciephy_reset)) { in imx6_pcie_probe()
1292 return PTR_ERR(imx6_pcie->pciephy_reset); in imx6_pcie_probe()
1295 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, in imx6_pcie_probe()
1297 if (IS_ERR(imx6_pcie->apps_reset)) { in imx6_pcie_probe()
1299 return PTR_ERR(imx6_pcie->apps_reset); in imx6_pcie_probe()
1306 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, in imx6_pcie_probe()
1308 if (IS_ERR(imx6_pcie->apps_reset)) in imx6_pcie_probe()
1309 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), in imx6_pcie_probe()
1312 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); in imx6_pcie_probe()
1313 if (IS_ERR(imx6_pcie->phy)) in imx6_pcie_probe()
1314 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), in imx6_pcie_probe()
1315 "failed to get pcie phy\n"); in imx6_pcie_probe()
1323 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); in imx6_pcie_probe()
1324 if (IS_ERR(imx6_pcie->turnoff_reset)) { in imx6_pcie_probe()
1326 return PTR_ERR(imx6_pcie->turnoff_reset); in imx6_pcie_probe()
1330 imx6_pcie->iomuxc_gpr = in imx6_pcie_probe()
1331 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); in imx6_pcie_probe()
1332 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { in imx6_pcie_probe()
1334 return PTR_ERR(imx6_pcie->iomuxc_gpr); in imx6_pcie_probe()
1337 /* Grab PCIe PHY Tx Settings */ in imx6_pcie_probe()
1338 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", in imx6_pcie_probe()
1339 &imx6_pcie->tx_deemph_gen1)) in imx6_pcie_probe()
1340 imx6_pcie->tx_deemph_gen1 = 0; in imx6_pcie_probe()
1342 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", in imx6_pcie_probe()
1343 &imx6_pcie->tx_deemph_gen2_3p5db)) in imx6_pcie_probe()
1344 imx6_pcie->tx_deemph_gen2_3p5db = 0; in imx6_pcie_probe()
1346 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", in imx6_pcie_probe()
1347 &imx6_pcie->tx_deemph_gen2_6db)) in imx6_pcie_probe()
1348 imx6_pcie->tx_deemph_gen2_6db = 20; in imx6_pcie_probe()
1350 if (of_property_read_u32(node, "fsl,tx-swing-full", in imx6_pcie_probe()
1351 &imx6_pcie->tx_swing_full)) in imx6_pcie_probe()
1352 imx6_pcie->tx_swing_full = 127; in imx6_pcie_probe()
1354 if (of_property_read_u32(node, "fsl,tx-swing-low", in imx6_pcie_probe()
1355 &imx6_pcie->tx_swing_low)) in imx6_pcie_probe()
1356 imx6_pcie->tx_swing_low = 127; in imx6_pcie_probe()
1359 pci->link_gen = 1; in imx6_pcie_probe()
1360 of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); in imx6_pcie_probe()
1362 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); in imx6_pcie_probe()
1363 if (IS_ERR(imx6_pcie->vpcie)) { in imx6_pcie_probe()
1364 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) in imx6_pcie_probe()
1365 return PTR_ERR(imx6_pcie->vpcie); in imx6_pcie_probe()
1366 imx6_pcie->vpcie = NULL; in imx6_pcie_probe()
1369 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); in imx6_pcie_probe()
1370 if (IS_ERR(imx6_pcie->vph)) { in imx6_pcie_probe()
1371 if (PTR_ERR(imx6_pcie->vph) != -ENODEV) in imx6_pcie_probe()
1372 return PTR_ERR(imx6_pcie->vph); in imx6_pcie_probe()
1373 imx6_pcie->vph = NULL; in imx6_pcie_probe()
1382 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { in imx6_pcie_probe()
1387 ret = dw_pcie_host_init(&pci->pp); in imx6_pcie_probe()
1392 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); in imx6_pcie_probe()
1394 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); in imx6_pcie_probe()
1396 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); in imx6_pcie_probe()
1422 .gpr = "fsl,imx6q-iomuxc-gpr",
1431 .gpr = "fsl,imx6q-iomuxc-gpr",
1441 .gpr = "fsl,imx6q-iomuxc-gpr",
1448 .gpr = "fsl,imx7d-iomuxc-gpr",
1454 .gpr = "fsl,imx8mq-iomuxc-gpr",
1461 .gpr = "fsl,imx8mm-iomuxc-gpr",
1468 .gpr = "fsl,imx8mp-iomuxc-gpr",
1475 .gpr = "fsl,imx8mq-iomuxc-gpr",
1482 .gpr = "fsl,imx8mm-iomuxc-gpr",
1489 .gpr = "fsl,imx8mp-iomuxc-gpr",
1496 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1497 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1498 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1499 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1500 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1501 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1502 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
1503 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
1504 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
1505 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
1511 .name = "imx6q-pcie",
1523 struct pci_bus *bus = dev->bus; in imx6_pcie_quirk()
1524 struct dw_pcie_rp *pp = bus->sysdata; in imx6_pcie_quirk()
1526 /* Bus parent is the PCI bridge, its parent is this platform driver */ in imx6_pcie_quirk()
1527 if (!bus->dev.parent || !bus->dev.parent->parent) in imx6_pcie_quirk()
1531 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) in imx6_pcie_quirk()
1535 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in imx6_pcie_quirk() local
1536 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); in imx6_pcie_quirk()
1542 if (imx6_pcie->drvdata->dbi_length) { in imx6_pcie_quirk()
1543 dev->cfg_size = imx6_pcie->drvdata->dbi_length; in imx6_pcie_quirk()
1544 dev_info(&dev->dev, "Limiting cfg_size to %d\n", in imx6_pcie_quirk()
1545 dev->cfg_size); in imx6_pcie_quirk()
1559 return -ENODEV; in imx6_pcie_init()
1565 * by kernel and since imx6q_pcie_abort_handler() is a no-op, in imx6_pcie_init()
1570 "external abort on non-linefetch"); in imx6_pcie_init()