Lines Matching +full:pcie +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
20 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
32 /* PCIe core registers */
33 #define PCIE_CORE_DEV_ID_REG 0x0
34 #define PCIE_CORE_CMD_STATUS_REG 0x4
35 #define PCIE_CORE_DEV_REV_REG 0x8
36 #define PCIE_CORE_SSDEV_ID_REG 0x2c
37 #define PCIE_CORE_PCIEXP_CAP 0xc0
38 #define PCIE_CORE_PCIERR_CAP 0x100
39 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
45 #define PIO_BASE_ADDR 0x4000
46 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
47 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
49 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
52 #define PIO_COMPLETION_STATUS_OK 0
58 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
59 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
60 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
61 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
62 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
63 #define PIO_START (PIO_BASE_ADDR + 0x1c)
64 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
65 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
68 #define CONTROL_BASE_ADDR 0x4800
69 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
70 #define PCIE_GEN_SEL_MSK 0x3
71 #define PCIE_GEN_SEL_SHIFT 0x0
72 #define SPEED_GEN_1 0
77 #define LANE_CNT_MSK 0x18
78 #define LANE_CNT_SHIFT 0x3
79 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
88 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
89 #define HOT_RESET_GEN BIT(0)
90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
91 #define PCIE_CORE_CTRL2_RESERVED 0x7
96 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
99 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
100 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
102 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
110 #define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
111 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
112 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
116 #define PCIE_ISR1_ALL_MASK GENMASK(31, 0)
117 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
118 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
119 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
120 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
121 #define PCIE_MSI_ALL_MASK GENMASK(31, 0)
122 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
123 #define PCIE_MSI_DATA_MASK GENMASK(15, 0)
125 /* PCIe window configuration */
126 #define OB_WIN_BASE_ADDR 0x4c00
127 #define OB_WIN_BLOCK_SIZE 0x20
132 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
133 #define OB_WIN_ENABLE BIT(0)
134 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
135 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
136 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
137 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
138 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
139 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
157 #define OB_WIN_TYPE_MASK GENMASK(3, 0)
158 #define OB_WIN_TYPE_SHIFT 0
159 #define OB_WIN_TYPE_MEM 0x0
160 #define OB_WIN_TYPE_IO 0x4
161 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8
162 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9
163 #define OB_WIN_TYPE_MSG 0xc
166 #define LMI_BASE_ADDR 0x6000
167 #define CFG_REG (LMI_BASE_ADDR + 0x0)
169 #define LTSSM_MASK 0x3f
170 #define RC_BAR_CONFIG 0x300
174 LTSSM_DETECT_QUIET = 0x0,
175 LTSSM_DETECT_ACTIVE = 0x1,
176 LTSSM_POLLING_ACTIVE = 0x2,
177 LTSSM_POLLING_COMPLIANCE = 0x3,
178 LTSSM_POLLING_CONFIGURATION = 0x4,
179 LTSSM_CONFIG_LINKWIDTH_START = 0x5,
180 LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6,
181 LTSSM_CONFIG_LANENUM_ACCEPT = 0x7,
182 LTSSM_CONFIG_LANENUM_WAIT = 0x8,
183 LTSSM_CONFIG_COMPLETE = 0x9,
184 LTSSM_CONFIG_IDLE = 0xa,
185 LTSSM_RECOVERY_RCVR_LOCK = 0xb,
186 LTSSM_RECOVERY_SPEED = 0xc,
187 LTSSM_RECOVERY_RCVR_CFG = 0xd,
188 LTSSM_RECOVERY_IDLE = 0xe,
189 LTSSM_L0 = 0x10,
190 LTSSM_RX_L0S_ENTRY = 0x11,
191 LTSSM_RX_L0S_IDLE = 0x12,
192 LTSSM_RX_L0S_FTS = 0x13,
193 LTSSM_TX_L0S_ENTRY = 0x14,
194 LTSSM_TX_L0S_IDLE = 0x15,
195 LTSSM_TX_L0S_FTS = 0x16,
196 LTSSM_L1_ENTRY = 0x17,
197 LTSSM_L1_IDLE = 0x18,
198 LTSSM_L2_IDLE = 0x19,
199 LTSSM_L2_TRANSMIT_WAKE = 0x1a,
200 LTSSM_DISABLED = 0x20,
201 LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
202 LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
203 LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
204 LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
205 LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
206 LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
207 LTSSM_HOT_RESET = 0x27,
208 LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28,
209 LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29,
210 LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a,
211 LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b,
214 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
216 /* PCIe core controller registers */
217 #define CTRL_CORE_BASE_ADDR 0x18000
218 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
219 #define CTRL_MODE_SHIFT 0x0
220 #define CTRL_MODE_MASK 0x1
221 #define PCIE_CORE_MODE_DIRECT 0x0
222 #define PCIE_CORE_MODE_COMMAND 0x1
224 /* PCIe Central Interrupts Registers */
225 #define CENTRAL_INT_BASE_ADDR 0x1b000
226 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
227 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
228 #define PCIE_IRQ_CMDQ_INT BIT(0)
246 #define PCIE_IRQ_ALL_MASK GENMASK(31, 0)
250 #define PCIE_CONFIG_RD_TYPE0 0x8
251 #define PCIE_CONFIG_RD_TYPE1 0x9
252 #define PCIE_CONFIG_WR_TYPE0 0xa
253 #define PCIE_CONFIG_WR_TYPE1 0xb
266 #define CFG_RD_CRS_VAL 0xffff0001
293 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
295 writel(val, pcie->base + reg); in advk_writel()
298 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
300 return readl(pcie->base + reg); in advk_readl()
303 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
308 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
313 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
315 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
316 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_up()
320 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) in advk_pcie_link_active() argument
323 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
330 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_active()
334 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) in advk_pcie_link_training() argument
337 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
341 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_training()
348 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) in advk_pcie_wait_for_link() argument
353 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { in advk_pcie_wait_for_link()
354 if (advk_pcie_link_up(pcie)) in advk_pcie_wait_for_link()
355 return 0; in advk_pcie_wait_for_link()
360 return -ETIMEDOUT; in advk_pcie_wait_for_link()
363 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) in advk_pcie_wait_for_retrain() argument
367 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { in advk_pcie_wait_for_retrain()
368 if (advk_pcie_link_training(pcie)) in advk_pcie_wait_for_retrain()
374 static void advk_pcie_issue_perst(struct advk_pcie *pcie) in advk_pcie_issue_perst() argument
376 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
380 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
381 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
383 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
386 static void advk_pcie_train_link(struct advk_pcie *pcie) in advk_pcie_train_link() argument
388 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
393 * Setup PCIe rev / gen compliance based on device tree property in advk_pcie_train_link()
394 * 'max-link-speed' which also forces maximal link speed. in advk_pcie_train_link()
396 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
398 if (pcie->link_gen == 3) in advk_pcie_train_link()
400 else if (pcie->link_gen == 2) in advk_pcie_train_link()
404 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
407 * Set maximal link speed value also into PCIe Link Control 2 register. in advk_pcie_train_link()
411 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
413 if (pcie->link_gen == 3) in advk_pcie_train_link()
415 else if (pcie->link_gen == 2) in advk_pcie_train_link()
419 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
421 /* Enable link training after selecting PCIe generation */ in advk_pcie_train_link()
422 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
424 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
427 * Reset PCIe card via PERST# signal. Some cards are not detected in advk_pcie_train_link()
428 * during link training when they are in some non-initial state. in advk_pcie_train_link()
430 advk_pcie_issue_perst(pcie); in advk_pcie_train_link()
440 * So wait until PCIe link is up. Function advk_pcie_wait_for_link() in advk_pcie_train_link()
443 ret = advk_pcie_wait_for_link(pcie); in advk_pcie_train_link()
444 if (ret < 0) in advk_pcie_train_link()
451 * Set PCIe address window register which could be used for memory
454 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, in advk_pcie_set_ob_win() argument
458 advk_writel(pcie, OB_WIN_ENABLE | in advk_pcie_set_ob_win()
460 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); in advk_pcie_set_ob_win()
461 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); in advk_pcie_set_ob_win()
462 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); in advk_pcie_set_ob_win()
463 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); in advk_pcie_set_ob_win()
464 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); in advk_pcie_set_ob_win()
465 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); in advk_pcie_set_ob_win()
468 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) in advk_pcie_disable_ob_win() argument
470 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); in advk_pcie_disable_ob_win()
471 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); in advk_pcie_disable_ob_win()
472 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); in advk_pcie_disable_ob_win()
473 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); in advk_pcie_disable_ob_win()
474 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); in advk_pcie_disable_ob_win()
475 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); in advk_pcie_disable_ob_win()
476 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); in advk_pcie_disable_ob_win()
479 static void advk_pcie_setup_hw(struct advk_pcie *pcie) in advk_pcie_setup_hw() argument
486 * Configure PCIe Reference clock. Direction is from the PCIe in advk_pcie_setup_hw()
488 * Reference clock differential signal off-chip and disable in advk_pcie_setup_hw()
489 * receiving off-chip differential signal. in advk_pcie_setup_hw()
491 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
494 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
497 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
500 advk_writel(pcie, reg, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
503 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
505 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
508 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. in advk_pcie_setup_hw()
511 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround in advk_pcie_setup_hw()
515 advk_writel(pcie, reg, VENDOR_ID_REG); in advk_pcie_setup_hw()
518 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), in advk_pcie_setup_hw()
519 * because the default value is Mass storage controller (0x010400). in advk_pcie_setup_hw()
524 * available in internal Aardvark registers starting at offset 0x0 in advk_pcie_setup_hw()
525 * and is reported as Type 0. In range 0x10 - 0x34 it has totally in advk_pcie_setup_hw()
532 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
533 reg &= ~0xffffff00; in advk_pcie_setup_hw()
535 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
538 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
540 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
547 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); in advk_pcie_setup_hw()
549 /* Set PCIe Device Control register */ in advk_pcie_setup_hw()
550 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
557 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
559 /* Program PCIe Control 2 to disable strict ordering */ in advk_pcie_setup_hw()
562 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
565 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
568 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
571 msi_addr = virt_to_phys(pcie); in advk_pcie_setup_hw()
572 advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG); in advk_pcie_setup_hw()
573 advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG); in advk_pcie_setup_hw()
576 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
578 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
581 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); in advk_pcie_setup_hw()
582 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_setup_hw()
583 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_setup_hw()
584 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_setup_hw()
587 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
588 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_setup_hw()
589 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); in advk_pcie_setup_hw()
592 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
594 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
597 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
599 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
603 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); in advk_pcie_setup_hw()
608 * configurations (Default User Field: 0xD0074CFC) in advk_pcie_setup_hw()
610 * the outbound transactions. Thus, PCIe address in advk_pcie_setup_hw()
615 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
617 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
621 * is not required to configure PCIe address for in advk_pcie_setup_hw()
624 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); in advk_pcie_setup_hw()
632 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
634 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_setup_hw()
637 * Configure PCIe address windows for non-memory or in advk_pcie_setup_hw()
638 * non-transparent access as by default PCIe uses in advk_pcie_setup_hw()
641 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
642 advk_pcie_set_ob_win(pcie, i, in advk_pcie_setup_hw()
643 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
644 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
646 /* Disable remaining PCIe outbound windows */ in advk_pcie_setup_hw()
647 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
648 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_setup_hw()
650 advk_pcie_train_link(pcie); in advk_pcie_setup_hw()
653 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) in advk_pcie_check_pio_status() argument
655 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
661 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
672 * a read value of 0xFFFFFFFF. in advk_pcie_check_pio_status()
675 * with a read value of 0xFFFF0001. in advk_pcie_check_pio_status()
684 ret = -EFAULT; in advk_pcie_check_pio_status()
689 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
692 ret = 0; in advk_pcie_check_pio_status()
696 ret = -EOPNOTSUPP; in advk_pcie_check_pio_status()
700 /* PCIe r4.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
706 * read-data value of 0001h for the Vendor ID field and in advk_pcie_check_pio_status()
714 ret = 0; in advk_pcie_check_pio_status()
717 /* PCIe r4.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
719 * must re-issue the Configuration Request as a new Request. in advk_pcie_check_pio_status()
722 * the Root Complex must re-issue the Configuration Request as in advk_pcie_check_pio_status()
730 * So return -EAGAIN and caller (pci-aardvark.c driver) will in advk_pcie_check_pio_status()
731 * re-issue request again up to the PIO_RETRY_CNT retries. in advk_pcie_check_pio_status()
734 ret = -EAGAIN; in advk_pcie_check_pio_status()
738 ret = -ECANCELED; in advk_pcie_check_pio_status()
742 ret = -EINVAL; in advk_pcie_check_pio_status()
750 str_posted = "Non-posted"; in advk_pcie_check_pio_status()
755 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
760 static int advk_pcie_wait_pio(struct advk_pcie *pcie) in advk_pcie_wait_pio() argument
762 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
768 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
769 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
776 return -ETIMEDOUT; in advk_pcie_wait_pio()
783 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_read() local
787 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
796 __le32 *cfgspace = (__le32 *)&bridge->conf; in advk_pci_bridge_emul_base_conf_read()
798 if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK) in advk_pci_bridge_emul_base_conf_read()
802 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
819 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_write() local
823 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_write()
828 * According to Figure 6-3: Pseudo Logic Diagram for Error in advk_pci_bridge_emul_base_conf_write()
829 * Message Controls in PCIe base specification, SERR# Enable bit in advk_pci_bridge_emul_base_conf_write()
833 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_base_conf_write()
838 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_base_conf_write()
841 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
846 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
859 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read() local
871 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
873 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0. in advk_pci_bridge_emul_pcie_conf_read()
884 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
886 if (advk_pcie_link_training(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
888 if (advk_pcie_link_active(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
900 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
913 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write() local
917 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
919 advk_pcie_wait_for_retrain(pcie); in advk_pci_bridge_emul_pcie_conf_write()
923 u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl); in advk_pci_bridge_emul_pcie_conf_write()
926 bridge->pcie_conf.rootctl = cpu_to_le16(rootctl); in advk_pci_bridge_emul_pcie_conf_write()
939 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
951 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_ext_conf_read() local
954 case 0: in advk_pci_bridge_emul_ext_conf_read()
955 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_read()
958 * PCI_EXT_CAP_NEXT bits are set to offset 0x150, but Armada in advk_pci_bridge_emul_ext_conf_read()
967 *value &= 0x000fffff; in advk_pci_bridge_emul_ext_conf_read()
976 case PCI_ERR_HEADER_LOG + 0: in advk_pci_bridge_emul_ext_conf_read()
983 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_read()
995 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_ext_conf_write() local
1009 case PCI_ERR_HEADER_LOG + 0: in advk_pci_bridge_emul_ext_conf_write()
1015 advk_writel(pcie, new, PCIE_CORE_PCIERR_CAP + reg); in advk_pci_bridge_emul_ext_conf_write()
1033 * Initialize the configuration space of the PCI-to-PCI bridge
1034 * associated with the given PCIe interface.
1036 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) in advk_sw_pci_bridge_init() argument
1038 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
1040 bridge->conf.vendor = in advk_sw_pci_bridge_init()
1041 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
1042 bridge->conf.device = in advk_sw_pci_bridge_init()
1043 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
1044 bridge->conf.class_revision = in advk_sw_pci_bridge_init()
1045 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
1048 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
1049 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
1052 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
1053 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
1056 bridge->conf.intpin = PCI_INTERRUPT_INTA; in advk_sw_pci_bridge_init()
1059 * Aardvark HW provides PCIe Capability structure in version 2 and in advk_sw_pci_bridge_init()
1062 bridge->pcie_conf.cap = cpu_to_le16(2 | PCI_EXP_FLAGS_SLOT); in advk_sw_pci_bridge_init()
1074 bridge->pcie_conf.slotcap = cpu_to_le32(FIELD_PREP(PCI_EXP_SLTCAP_PSN, in advk_sw_pci_bridge_init()
1076 bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); in advk_sw_pci_bridge_init()
1079 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); in advk_sw_pci_bridge_init()
1081 bridge->subsystem_vendor_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) & 0xffff; in advk_sw_pci_bridge_init()
1082 bridge->subsystem_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) >> 16; in advk_sw_pci_bridge_init()
1083 bridge->has_pcie = true; in advk_sw_pci_bridge_init()
1084 bridge->pcie_start = PCIE_CORE_PCIEXP_CAP; in advk_sw_pci_bridge_init()
1085 bridge->data = pcie; in advk_sw_pci_bridge_init()
1086 bridge->ops = &advk_pci_bridge_emul_ops; in advk_sw_pci_bridge_init()
1088 return pci_bridge_emul_init(bridge, 0); in advk_sw_pci_bridge_init()
1091 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, in advk_pcie_valid_device() argument
1094 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0) in advk_pcie_valid_device()
1098 * If the link goes down after we check for link-up, we have a problem: in advk_pcie_valid_device()
1099 * if a PIO request is executed while link-down, the whole controller in advk_pcie_valid_device()
1100 * gets stuck in a non-functional state, and even after link comes up in advk_pcie_valid_device()
1101 * again, PIO requests won't work anymore, and a reset of the whole PCIe in advk_pcie_valid_device()
1105 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) in advk_pcie_valid_device()
1111 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) in advk_pcie_pio_is_running() argument
1113 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
1119 * SError Interrupt on CPU0, code 0xbf000002 -- SError in advk_pcie_pio_is_running()
1120 * Kernel panic - not syncing: Asynchronous SError Interrupt in advk_pcie_pio_is_running()
1129 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: in advk_pcie_pio_is_running()
1130 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 in advk_pcie_pio_is_running()
1132 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1143 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf() local
1149 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_rd_conf()
1153 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
1162 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
1165 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_rd_conf()
1169 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1171 if (pci_is_root_bus(bus->parent)) in advk_pcie_rd_conf()
1175 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_rd_conf()
1178 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); in advk_pcie_rd_conf()
1179 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_rd_conf()
1180 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_rd_conf()
1183 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); in advk_pcie_rd_conf()
1185 retry_count = 0; in advk_pcie_rd_conf()
1188 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_rd_conf()
1189 advk_writel(pcie, 1, PIO_START); in advk_pcie_rd_conf()
1191 ret = advk_pcie_wait_pio(pcie); in advk_pcie_rd_conf()
1192 if (ret < 0) in advk_pcie_rd_conf()
1198 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); in advk_pcie_rd_conf()
1199 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_rd_conf()
1201 if (ret < 0) in advk_pcie_rd_conf()
1205 *val = (*val >> (8 * (where & 3))) & 0xff; in advk_pcie_rd_conf()
1207 *val = (*val >> (8 * (where & 3))) & 0xffff; in advk_pcie_rd_conf()
1222 *val = 0xffffffff; in advk_pcie_rd_conf()
1229 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf() local
1231 u32 data_strobe = 0x0; in advk_pcie_wr_conf()
1236 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_wr_conf()
1240 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1246 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_wr_conf()
1250 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1252 if (pci_is_root_bus(bus->parent)) in advk_pcie_wr_conf()
1256 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_wr_conf()
1259 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); in advk_pcie_wr_conf()
1260 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_wr_conf()
1261 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_wr_conf()
1264 offset = where & 0x3; in advk_pcie_wr_conf()
1266 data_strobe = GENMASK(size - 1, 0) << offset; in advk_pcie_wr_conf()
1269 advk_writel(pcie, reg, PIO_WR_DATA); in advk_pcie_wr_conf()
1272 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); in advk_pcie_wr_conf()
1274 retry_count = 0; in advk_pcie_wr_conf()
1277 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_wr_conf()
1278 advk_writel(pcie, 1, PIO_START); in advk_pcie_wr_conf()
1280 ret = advk_pcie_wait_pio(pcie); in advk_pcie_wr_conf()
1281 if (ret < 0) in advk_pcie_wr_conf()
1286 ret = advk_pcie_check_pio_status(pcie, false, NULL); in advk_pcie_wr_conf()
1287 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_wr_conf()
1289 return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL; in advk_pcie_wr_conf()
1300 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); in advk_msi_irq_compose_msi_msg() local
1301 phys_addr_t msi_addr = virt_to_phys(pcie); in advk_msi_irq_compose_msi_msg()
1303 msg->address_lo = lower_32_bits(msi_addr); in advk_msi_irq_compose_msi_msg()
1304 msg->address_hi = upper_32_bits(msi_addr); in advk_msi_irq_compose_msi_msg()
1305 msg->data = data->hwirq; in advk_msi_irq_compose_msi_msg()
1311 return -EINVAL; in advk_msi_set_affinity()
1316 struct advk_pcie *pcie = d->domain->host_data; in advk_msi_irq_mask() local
1321 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); in advk_msi_irq_mask()
1322 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_msi_irq_mask()
1324 advk_writel(pcie, mask, PCIE_MSI_MASK_REG); in advk_msi_irq_mask()
1325 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); in advk_msi_irq_mask()
1330 struct advk_pcie *pcie = d->domain->host_data; in advk_msi_irq_unmask() local
1335 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags); in advk_msi_irq_unmask()
1336 mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_msi_irq_unmask()
1338 advk_writel(pcie, mask, PCIE_MSI_MASK_REG); in advk_msi_irq_unmask()
1339 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags); in advk_msi_irq_unmask()
1366 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc() local
1369 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1370 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1372 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1373 if (hwirq < 0) in advk_msi_irq_domain_alloc()
1374 return -ENOSPC; in advk_msi_irq_domain_alloc()
1376 for (i = 0; i < nr_irqs; i++) in advk_msi_irq_domain_alloc()
1379 domain->host_data, handle_simple_irq, in advk_msi_irq_domain_alloc()
1382 return 0; in advk_msi_irq_domain_alloc()
1389 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free() local
1391 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1392 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); in advk_msi_irq_domain_free()
1393 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1403 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask() local
1408 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1409 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1411 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1412 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1417 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask() local
1422 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1423 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1425 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1426 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1432 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map() local
1435 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1437 irq_set_chip_data(virq, pcie); in advk_pcie_irq_map()
1439 return 0; in advk_pcie_irq_map()
1448 .name = "advk-MSI",
1459 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_msi_irq_domain() argument
1461 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1463 raw_spin_lock_init(&pcie->msi_irq_lock); in advk_pcie_init_msi_irq_domain()
1464 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1466 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1468 &advk_msi_domain_ops, pcie); in advk_pcie_init_msi_irq_domain()
1469 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1470 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1472 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1475 pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1476 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1477 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1478 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1481 return 0; in advk_pcie_init_msi_irq_domain()
1484 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_msi_irq_domain() argument
1486 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1487 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1490 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_irq_domain() argument
1492 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1493 struct device_node *node = dev->of_node; in advk_pcie_init_irq_domain()
1496 int ret = 0; in advk_pcie_init_irq_domain()
1498 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1502 dev_err(dev, "No PCIe Intc node found\n"); in advk_pcie_init_irq_domain()
1503 return -ENODEV; in advk_pcie_init_irq_domain()
1506 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1508 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", in advk_pcie_init_irq_domain()
1510 if (!irq_chip->name) { in advk_pcie_init_irq_domain()
1511 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1515 irq_chip->irq_mask = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1516 irq_chip->irq_unmask = advk_pcie_irq_unmask; in advk_pcie_init_irq_domain()
1518 pcie->irq_domain = in advk_pcie_init_irq_domain()
1520 &advk_pcie_irq_domain_ops, pcie); in advk_pcie_init_irq_domain()
1521 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1523 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1532 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_irq_domain() argument
1534 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1538 .name = "advk-RP",
1544 struct advk_pcie *pcie = h->host_data; in advk_pcie_rp_irq_map() local
1547 irq_set_chip_data(virq, pcie); in advk_pcie_rp_irq_map()
1549 return 0; in advk_pcie_rp_irq_map()
1557 static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_rp_irq_domain() argument
1559 pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1, in advk_pcie_init_rp_irq_domain()
1561 pcie); in advk_pcie_init_rp_irq_domain()
1562 if (!pcie->rp_irq_domain) { in advk_pcie_init_rp_irq_domain()
1563 dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n"); in advk_pcie_init_rp_irq_domain()
1564 return -ENOMEM; in advk_pcie_init_rp_irq_domain()
1567 return 0; in advk_pcie_init_rp_irq_domain()
1570 static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_rp_irq_domain() argument
1572 irq_domain_remove(pcie->rp_irq_domain); in advk_pcie_remove_rp_irq_domain()
1575 static void advk_pcie_handle_pme(struct advk_pcie *pcie) in advk_pcie_handle_pme() argument
1577 u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16; in advk_pcie_handle_pme()
1579 advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG); in advk_pcie_handle_pme()
1586 if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) { in advk_pcie_handle_pme()
1587 pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME); in advk_pcie_handle_pme()
1591 * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0. in advk_pcie_handle_pme()
1593 if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE)) in advk_pcie_handle_pme()
1596 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) in advk_pcie_handle_pme()
1597 dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); in advk_pcie_handle_pme()
1601 static void advk_pcie_handle_msi(struct advk_pcie *pcie) in advk_pcie_handle_msi() argument
1605 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1606 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1609 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { in advk_pcie_handle_msi()
1613 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1614 if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL) in advk_pcie_handle_msi()
1615 dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx); in advk_pcie_handle_msi()
1618 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, in advk_pcie_handle_msi()
1622 static void advk_pcie_handle_int(struct advk_pcie *pcie) in advk_pcie_handle_int() argument
1628 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1629 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1632 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1633 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1638 advk_pcie_handle_pme(pcie); in advk_pcie_handle_int()
1642 advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG); in advk_pcie_handle_int()
1646 * PCIe interrupt 0 in advk_pcie_handle_int()
1648 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL) in advk_pcie_handle_int()
1649 dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n"); in advk_pcie_handle_int()
1654 advk_pcie_handle_msi(pcie); in advk_pcie_handle_int()
1657 for (i = 0; i < PCI_NUM_INTX; i++) { in advk_pcie_handle_int()
1661 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), in advk_pcie_handle_int()
1664 if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL) in advk_pcie_handle_int()
1665 dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n", in advk_pcie_handle_int()
1672 struct advk_pcie *pcie = arg; in advk_pcie_irq_handler() local
1675 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1679 advk_pcie_handle_int(pcie); in advk_pcie_irq_handler()
1682 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1689 struct advk_pcie *pcie = dev->bus->sysdata; in advk_pcie_map_irq() local
1696 if (pci_is_root_bus(dev->bus)) in advk_pcie_map_irq()
1697 return irq_create_mapping(pcie->rp_irq_domain, pin - 1); in advk_pcie_map_irq()
1702 static void advk_pcie_disable_phy(struct advk_pcie *pcie) in advk_pcie_disable_phy() argument
1704 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1705 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1708 static int advk_pcie_enable_phy(struct advk_pcie *pcie) in advk_pcie_enable_phy() argument
1712 if (!pcie->phy) in advk_pcie_enable_phy()
1713 return 0; in advk_pcie_enable_phy()
1715 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1719 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1721 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1725 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1727 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1731 return 0; in advk_pcie_enable_phy()
1734 static int advk_pcie_setup_phy(struct advk_pcie *pcie) in advk_pcie_setup_phy() argument
1736 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1737 struct device_node *node = dev->of_node; in advk_pcie_setup_phy()
1738 int ret = 0; in advk_pcie_setup_phy()
1740 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1741 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1742 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1745 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1746 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1747 pcie->phy = NULL; in advk_pcie_setup_phy()
1748 return 0; in advk_pcie_setup_phy()
1751 ret = advk_pcie_enable_phy(pcie); in advk_pcie_setup_phy()
1760 struct device *dev = &pdev->dev; in advk_pcie_probe()
1761 struct advk_pcie *pcie; in advk_pcie_probe() local
1768 return -ENOMEM; in advk_pcie_probe()
1770 pcie = pci_host_bridge_priv(bridge); in advk_pcie_probe()
1771 pcie->pdev = pdev; in advk_pcie_probe()
1772 platform_set_drvdata(pdev, pcie); in advk_pcie_probe()
1774 resource_list_for_each_entry(entry, &bridge->windows) { in advk_pcie_probe()
1775 resource_size_t start = entry->res->start; in advk_pcie_probe()
1776 resource_size_t size = resource_size(entry->res); in advk_pcie_probe()
1777 unsigned long type = resource_type(entry->res); in advk_pcie_probe()
1781 * Aardvark hardware allows to configure also PCIe window in advk_pcie_probe()
1782 * for config type 0 and type 1 mapping, but driver uses in advk_pcie_probe()
1784 * not use PCIe window configuration. in advk_pcie_probe()
1794 if (type == IORESOURCE_MEM && entry->offset == 0) in advk_pcie_probe()
1798 * The n-th PCIe window is configured by tuple (match, remap, mask) in advk_pcie_probe()
1801 * So every PCIe window size must be a power of two and every start in advk_pcie_probe()
1806 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1808 win_size = (1ULL << (fls64(size)-1)) | in advk_pcie_probe()
1809 (start ? (1ULL << __ffs64(start)) : 0); in advk_pcie_probe()
1811 if (win_size < 0x10000) in advk_pcie_probe()
1815 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", in advk_pcie_probe()
1816 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1820 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1821 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1823 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1824 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1826 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1827 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1829 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1833 size -= win_size; in advk_pcie_probe()
1834 pcie->wins_count++; in advk_pcie_probe()
1837 if (size > 0) { in advk_pcie_probe()
1838 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1839 "Invalid PCIe region [0x%llx-0x%llx]\n", in advk_pcie_probe()
1840 (unsigned long long)entry->res->start, in advk_pcie_probe()
1841 (unsigned long long)entry->res->end + 1); in advk_pcie_probe()
1842 return -EINVAL; in advk_pcie_probe()
1846 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1847 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1848 return PTR_ERR(pcie->base); in advk_pcie_probe()
1850 irq = platform_get_irq(pdev, 0); in advk_pcie_probe()
1851 if (irq < 0) in advk_pcie_probe()
1855 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", in advk_pcie_probe()
1856 pcie); in advk_pcie_probe()
1862 pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); in advk_pcie_probe()
1863 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1865 if (ret != -EPROBE_DEFER) in advk_pcie_probe()
1866 dev_err(dev, "Failed to get reset-gpio: %i\n", ret); in advk_pcie_probe()
1870 ret = gpiod_set_consumer_name(pcie->reset_gpio, "pcie1-reset"); in advk_pcie_probe()
1876 ret = of_pci_get_max_link_speed(dev->of_node); in advk_pcie_probe()
1877 if (ret <= 0 || ret > 3) in advk_pcie_probe()
1878 pcie->link_gen = 3; in advk_pcie_probe()
1880 pcie->link_gen = ret; in advk_pcie_probe()
1882 ret = advk_pcie_setup_phy(pcie); in advk_pcie_probe()
1886 advk_pcie_setup_hw(pcie); in advk_pcie_probe()
1888 ret = advk_sw_pci_bridge_init(pcie); in advk_pcie_probe()
1894 ret = advk_pcie_init_irq_domain(pcie); in advk_pcie_probe()
1900 ret = advk_pcie_init_msi_irq_domain(pcie); in advk_pcie_probe()
1903 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1907 ret = advk_pcie_init_rp_irq_domain(pcie); in advk_pcie_probe()
1910 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1911 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1915 bridge->sysdata = pcie; in advk_pcie_probe()
1916 bridge->ops = &advk_pcie_ops; in advk_pcie_probe()
1917 bridge->map_irq = advk_pcie_map_irq; in advk_pcie_probe()
1920 if (ret < 0) { in advk_pcie_probe()
1921 advk_pcie_remove_rp_irq_domain(pcie); in advk_pcie_probe()
1922 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1923 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1927 return 0; in advk_pcie_probe()
1932 struct advk_pcie *pcie = platform_get_drvdata(pdev); in advk_pcie_remove() local
1933 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in advk_pcie_remove()
1939 pci_stop_root_bus(bridge->bus); in advk_pcie_remove()
1940 pci_remove_root_bus(bridge->bus); in advk_pcie_remove()
1944 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_remove()
1946 advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_remove()
1949 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_remove()
1951 advk_writel(pcie, val, PCIE_CORE_CTRL2_REG); in advk_pcie_remove()
1954 advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG); in advk_pcie_remove()
1955 advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG); in advk_pcie_remove()
1958 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); in advk_pcie_remove()
1959 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG); in advk_pcie_remove()
1960 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_remove()
1961 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG); in advk_pcie_remove()
1964 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); in advk_pcie_remove()
1965 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_remove()
1966 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_remove()
1967 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_remove()
1970 advk_pcie_remove_rp_irq_domain(pcie); in advk_pcie_remove()
1971 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_remove()
1972 advk_pcie_remove_irq_domain(pcie); in advk_pcie_remove()
1975 pci_bridge_emul_cleanup(&pcie->bridge); in advk_pcie_remove()
1977 /* Assert PERST# signal which prepares PCIe card for power down */ in advk_pcie_remove()
1978 if (pcie->reset_gpio) in advk_pcie_remove()
1979 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_remove()
1982 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_remove()
1984 advk_writel(pcie, val, PCIE_CORE_CTRL0_REG); in advk_pcie_remove()
1987 for (i = 0; i < OB_WIN_COUNT; i++) in advk_pcie_remove()
1988 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_remove()
1991 advk_pcie_disable_phy(pcie); in advk_pcie_remove()
1995 { .compatible = "marvell,armada-3700-pcie", },
2002 .name = "advk-pcie",
2010 MODULE_DESCRIPTION("Aardvark PCIe controller");