1258 	pcie->pex_clk = devm_clk_get(dev, "pex");  in tegra_pcie_clocks_get()
1283 	pcie->pex_rst = devm_reset_control_get_exclusive(dev, "pex");  in tegra_pcie_resets_get()
1982 	pcie->supplies[0].supply = "pex-clk";  in tegra_pcie_get_legacy_regulators()
2015 		pcie->supplies[i++].supply = "dvdd-pex";  in tegra_pcie_get_regulators()
2016 		pcie->supplies[i++].supply = "hvdd-pex-pll";  in tegra_pcie_get_regulators()
2017 		pcie->supplies[i++].supply = "hvdd-pex";  in tegra_pcie_get_regulators()
2028 		pcie->supplies[i++].supply = "hvddio-pex";  in tegra_pcie_get_regulators()
2029 		pcie->supplies[i++].supply = "dvddio-pex";  in tegra_pcie_get_regulators()
2030 		pcie->supplies[i++].supply = "vddio-pex-ctl";  in tegra_pcie_get_regulators()
2040 		pcie->supplies[i++].supply = "avddio-pex";  in tegra_pcie_get_regulators()
2041 		pcie->supplies[i++].supply = "dvddio-pex";  in tegra_pcie_get_regulators()
2042 		pcie->supplies[i++].supply = "hvdd-pex";  in tegra_pcie_get_regulators()
2043 		pcie->supplies[i++].supply = "vddio-pex-ctl";  in tegra_pcie_get_regulators()
2064 		pcie->supplies[i++].supply = "avdd-pex-pll";  in tegra_pcie_get_regulators()
2065 		pcie->supplies[i++].supply = "hvdd-pex";  in tegra_pcie_get_regulators()
2066 		pcie->supplies[i++].supply = "vddio-pex-ctl";  in tegra_pcie_get_regulators()
2087 		pcie->supplies[0].supply = "avdd-pex";  in tegra_pcie_get_regulators()
2088 		pcie->supplies[1].supply = "vdd-pex";  in tegra_pcie_get_regulators()
2089 		pcie->supplies[2].supply = "avdd-pex-pll";  in tegra_pcie_get_regulators()
2091 		pcie->supplies[4].supply = "vddio-pex-clk";  in tegra_pcie_get_regulators()
2191 		label = devm_kasprintf(dev, GFP_KERNEL, "pex-reset-%u", index);  in tegra_pcie_parse_dt()
2766 		dev_err(dev, "failed to enable PEX clock: %d\n", err);  in tegra_pcie_pm_resume()