Lines Matching full:pcie
40 /* Broadcom STB PCIe Register Offsets */
147 /* PCIe parameters */
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
221 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
222 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
248 /* Internal PCIe Host Controller Information.*/
265 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
266 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
271 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
273 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
342 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
348 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
353 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
366 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
378 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
380 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
381 u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
384 writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
387 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
390 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
400 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
401 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
407 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
412 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
414 if (is_bmips(pcie)) in brcm_pcie_set_outbound_win()
422 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
425 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
428 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
431 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
435 .name = "BRCM STB PCIe MSI",
584 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
586 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
615 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
619 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
633 msi->base = pcie->base; in brcm_pcie_enable_msi()
634 msi->np = pcie->np; in brcm_pcie_enable_msi()
635 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
637 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
662 pcie->msi = msi; in brcm_pcie_enable_msi()
668 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
670 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
676 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
678 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
688 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus() local
689 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
697 if (!brcm_pcie_link_up(pcie)) in brcm_pcie_map_bus()
702 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
709 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus() local
710 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
718 if (!brcm_pcie_link_up(pcie)) in brcm7425_pcie_map_bus()
723 writel(idx, base + IDX_ADDR(pcie)); in brcm7425_pcie_map_bus()
724 return base + DATA_ADDR(pcie); in brcm7425_pcie_map_bus()
727 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
732 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
734 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
737 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
742 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
744 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
747 static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_4908() argument
749 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
753 reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
755 reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
758 static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
763 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
765 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
768 static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
772 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
774 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
777 static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, in brcm_pcie_get_rc_bar2_size_and_offset() argument
781 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_rc_bar2_size_and_offset()
783 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
801 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
806 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
807 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
809 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
813 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
814 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
816 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
826 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_rc_bar2_size_and_offset()
831 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_rc_bar2_size_and_offset()
834 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
845 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
864 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
867 void __iomem *base = pcie->base; in brcm_pcie_setup()
875 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
878 if (pcie->type == BCM2711) in brcm_pcie_setup()
879 pcie->perst_set(pcie, 1); in brcm_pcie_setup()
884 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
887 if (is_bmips(pcie)) in brcm_pcie_setup()
900 if (is_bmips(pcie)) in brcm_pcie_setup()
902 else if (pcie->type == BCM2711) in brcm_pcie_setup()
904 else if (pcie->type == BCM7278) in brcm_pcie_setup()
921 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, in brcm_pcie_setup()
934 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
935 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
954 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
956 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
958 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
959 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
963 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
968 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
975 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
984 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
991 bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
999 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1003 if (is_bmips(pcie)) { in brcm_pcie_setup()
1007 /* bmips PCIe outbound windows have a 128MB max size */ in brcm_pcie_setup()
1011 brcm_pcie_set_outbound_win(pcie, j, start, in brcm_pcie_setup()
1016 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1022 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1031 static int brcm_pcie_start_link(struct brcm_pcie *pcie) in brcm_pcie_start_link() argument
1033 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1034 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1041 pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1044 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification in brcm_pcie_start_link()
1045 * sections 2.2, PCIe r5.0, 6.6.1. in brcm_pcie_start_link()
1054 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1057 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_start_link()
1062 if (pcie->gen) in brcm_pcie_start_link()
1063 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1065 if (pcie->ssc) { in brcm_pcie_start_link()
1066 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_start_link()
1116 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus() local
1131 pcie->sr = sr; in brcm_pcie_add_bus()
1136 pcie->sr = NULL; in brcm_pcie_add_bus()
1144 pcie->sr = NULL; in brcm_pcie_add_bus()
1149 brcm_pcie_start_link(pcie); in brcm_pcie_add_bus()
1155 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus() local
1156 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1165 pcie->sr = NULL; in brcm_pcie_remove_bus()
1168 /* L23 is a low-power PCIe link state */
1169 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1171 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1191 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1194 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1208 void __iomem *base = pcie->base; in brcm_phy_cntl()
1225 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1230 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1232 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1235 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1237 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1240 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1242 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1245 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1246 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1248 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1260 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1261 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1277 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend_noirq() local
1278 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_suspend_noirq()
1281 brcm_pcie_turn_off(pcie); in brcm_pcie_suspend_noirq()
1287 if (brcm_phy_stop(pcie)) in brcm_pcie_suspend_noirq()
1290 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1296 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1302 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1304 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1305 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1306 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1307 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1310 reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1315 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1322 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume_noirq() local
1327 base = pcie->base; in brcm_pcie_resume_noirq()
1328 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1332 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1336 ret = brcm_phy_start(pcie); in brcm_pcie_resume_noirq()
1341 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1351 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume_noirq()
1355 if (pcie->sr) { in brcm_pcie_resume_noirq()
1356 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1363 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1365 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1366 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1374 ret = brcm_pcie_start_link(pcie); in brcm_pcie_resume_noirq()
1378 if (pcie->msi) in brcm_pcie_resume_noirq()
1379 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1384 if (pcie->sr) in brcm_pcie_resume_noirq()
1385 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1387 reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1389 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1393 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1395 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1396 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1397 if (brcm_phy_stop(pcie)) in __brcm_pcie_remove()
1398 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1399 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1400 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1401 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1406 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1407 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1411 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1475 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1476 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1477 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1478 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1479 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1480 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1481 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1482 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1507 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1510 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1520 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1521 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1522 pcie->np = np; in brcm_pcie_probe()
1523 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1524 pcie->type = data->type; in brcm_pcie_probe()
1525 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1526 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1528 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1529 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1530 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1532 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1533 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1534 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1537 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1539 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1541 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1546 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1547 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1548 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1549 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1551 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1552 if (IS_ERR(pcie->perst_reset)) { in brcm_pcie_probe()
1553 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1554 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1557 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1561 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1563 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1564 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1568 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1572 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1573 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1574 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1580 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1582 if (msi_np == pcie->np) in brcm_pcie_probe()
1583 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1588 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1593 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1594 bridge->sysdata = pcie; in brcm_pcie_probe()
1596 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1599 if (!ret && !brcm_pcie_link_up(pcie)) in brcm_pcie_probe()
1610 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1625 .name = "brcm-pcie",
1633 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");