Lines Matching +full:pcie +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
38 #define BRCM_PCIE_CAP_REGS 0x00ac
40 /* Broadcom STB PCIe Register Offsets */
41 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
43 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
45 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
46 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
48 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
49 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
51 #define PCIE_RC_DL_MDIO_ADDR 0x1100
52 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
53 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
55 #define PCIE_MISC_MISC_CTRL 0x4008
56 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
57 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
58 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
59 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
60 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
62 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
63 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
64 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
67 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
71 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
75 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
76 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
78 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
79 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
80 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
82 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
83 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
85 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
86 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
88 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
89 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
90 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
92 #define PCIE_MISC_PCIE_CTRL 0x4064
93 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
94 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
96 #define PCIE_MISC_PCIE_STATUS 0x4068
97 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
98 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
99 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
100 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
102 #define PCIE_MISC_REVISION 0x406c
103 #define BRCM_PCIE_HW_REV_33 0x0303
104 #define BRCM_PCIE_HW_REV_3_20 0x0320
106 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
107 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
108 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
112 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
113 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
117 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
118 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
122 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
123 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
124 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
125 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
128 #define PCIE_INTR2_CPU_BASE 0x4300
129 #define PCIE_MSI_INTR2_BASE 0x4500
131 #define MSI_INT_STATUS 0x0
132 #define MSI_INT_CLR 0x8
133 #define MSI_INT_MASK_SET 0x10
134 #define MSI_INT_MASK_CLR 0x14
136 #define PCIE_EXT_CFG_DATA 0x8000
137 #define PCIE_EXT_CFG_INDEX 0x9000
139 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
140 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
142 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
143 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
144 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
145 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
147 /* PCIe parameters */
148 #define BRCM_NUM_PCIE_OUT_WINS 0x4
151 #define BRCM_INT_PCI_MSI_SHIFT 0
152 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
154 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
157 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
158 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
161 #define MDIO_PORT0 0x0
162 #define MDIO_DATA_MASK 0x7fffffff
163 #define MDIO_PORT_MASK 0xf0000
164 #define MDIO_REGAD_MASK 0xffff
165 #define MDIO_CMD_MASK 0xfff00000
166 #define MDIO_CMD_READ 0x1
167 #define MDIO_CMD_WRITE 0x0
168 #define MDIO_DATA_DONE_MASK 0x80000000
169 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
170 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
171 #define SSC_REGS_ADDR 0x1100
172 #define SET_ADDR_OFFSET 0x1f
173 #define SSC_CNTL_OFFSET 0x2
174 #define SSC_CNTL_OVRD_EN_MASK 0x8000
175 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
176 #define SSC_STATUS_OFFSET 0x1
177 #define SSC_STATUS_SSC_MASK 0x400
178 #define SSC_STATUS_PLL_LOCK_MASK 0x800
181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
186 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
187 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
188 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
189 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
190 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
191 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
192 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
193 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
221 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
222 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
248 /* Internal PCIe Host Controller Information.*/
265 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
266 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
271 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
273 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
278 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
286 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
289 return log2_in - 15; in brcm_pcie_encode_ibar_size()
291 return 0; in brcm_pcie_encode_ibar_size()
296 u32 pkt = 0; in brcm_pcie_mdio_form_pkt()
342 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
348 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
350 if (ret < 0) in brcm_pcie_set_ssc()
353 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
355 if (ret < 0) in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
362 if (ret < 0) in brcm_pcie_set_ssc()
366 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
368 if (ret < 0) in brcm_pcie_set_ssc()
374 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
378 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
380 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
381 u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
384 writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
386 lnkctl2 = (lnkctl2 & ~0xf) | gen; in brcm_pcie_set_gen()
387 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
390 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
400 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
401 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
405 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
407 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
412 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
414 if (is_bmips(pcie)) in brcm_pcie_set_outbound_win()
422 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
425 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
428 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
431 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
435 .name = "BRCM STB PCIe MSI",
457 dev = msi->dev; in brcm_pcie_msi_isr()
459 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
460 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
462 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
464 ret = generic_handle_domain_irq(msi->inner_domain, bit); in brcm_pcie_msi_isr()
476 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
477 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
478 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
484 return -EINVAL; in brcm_msi_set_affinity()
490 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
492 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
507 mutex_lock(&msi->lock); in brcm_msi_alloc()
508 hwirq = bitmap_find_free_region(msi->used, msi->nr, in brcm_msi_alloc()
510 mutex_unlock(&msi->lock); in brcm_msi_alloc()
518 mutex_lock(&msi->lock); in brcm_msi_free()
519 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs)); in brcm_msi_free()
520 mutex_unlock(&msi->lock); in brcm_msi_free()
526 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc()
531 if (hwirq < 0) in brcm_irq_domain_alloc()
534 for (i = 0; i < nr_irqs; i++) in brcm_irq_domain_alloc()
536 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
538 return 0; in brcm_irq_domain_alloc()
547 brcm_msi_free(msi, d->hwirq, nr_irqs); in brcm_irq_domain_free()
557 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); in brcm_allocate_domains()
558 struct device *dev = msi->dev; in brcm_allocate_domains()
560 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); in brcm_allocate_domains()
561 if (!msi->inner_domain) { in brcm_allocate_domains()
563 return -ENOMEM; in brcm_allocate_domains()
566 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in brcm_allocate_domains()
568 msi->inner_domain); in brcm_allocate_domains()
569 if (!msi->msi_domain) { in brcm_allocate_domains()
571 irq_domain_remove(msi->inner_domain); in brcm_allocate_domains()
572 return -ENOMEM; in brcm_allocate_domains()
575 return 0; in brcm_allocate_domains()
580 irq_domain_remove(msi->msi_domain); in brcm_free_domains()
581 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
584 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
586 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
590 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in brcm_msi_remove()
596 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK : in brcm_msi_set_regs()
599 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
600 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
603 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI in brcm_msi_set_regs()
606 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
607 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
608 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
609 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
611 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
612 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
615 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
619 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
621 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
622 if (irq <= 0) { in brcm_pcie_enable_msi()
624 return -ENODEV; in brcm_pcie_enable_msi()
629 return -ENOMEM; in brcm_pcie_enable_msi()
631 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
632 msi->dev = dev; in brcm_pcie_enable_msi()
633 msi->base = pcie->base; in brcm_pcie_enable_msi()
634 msi->np = pcie->np; in brcm_pcie_enable_msi()
635 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
636 msi->irq = irq; in brcm_pcie_enable_msi()
637 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
645 if (msi->legacy) { in brcm_pcie_enable_msi()
646 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE; in brcm_pcie_enable_msi()
647 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
648 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
650 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
651 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
652 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
659 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
662 pcie->msi = msi; in brcm_pcie_enable_msi()
664 return 0; in brcm_pcie_enable_msi()
668 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
670 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
676 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
678 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
688 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus() local
689 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
696 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm_pcie_map_bus()
697 if (!brcm_pcie_link_up(pcie)) in brcm_pcie_map_bus()
701 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
702 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_bus()
709 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus() local
710 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
717 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm7425_pcie_map_bus()
718 if (!brcm_pcie_link_up(pcie)) in brcm7425_pcie_map_bus()
722 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where); in brcm7425_pcie_map_bus()
723 writel(idx, base + IDX_ADDR(pcie)); in brcm7425_pcie_map_bus()
724 return base + DATA_ADDR(pcie); in brcm7425_pcie_map_bus()
727 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
732 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
734 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
737 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
742 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
744 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
747 static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_4908() argument
749 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
753 reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
755 reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
758 static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
762 /* Perst bit has moved and assert value is 0 */ in brcm_pcie_perst_set_7278()
763 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
765 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
768 static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
772 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
774 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
777 static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, in brcm_pcie_get_rc_bar2_size_and_offset() argument
781 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_rc_bar2_size_and_offset()
783 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
784 u64 lowest_pcie_addr = ~(u64)0; in brcm_pcie_get_rc_bar2_size_and_offset()
785 int ret, i = 0; in brcm_pcie_get_rc_bar2_size_and_offset()
786 u64 size = 0; in brcm_pcie_get_rc_bar2_size_and_offset()
788 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_rc_bar2_size_and_offset()
789 u64 pcie_beg = entry->res->start - entry->offset; in brcm_pcie_get_rc_bar2_size_and_offset()
791 size += entry->res->end - entry->res->start + 1; in brcm_pcie_get_rc_bar2_size_and_offset()
796 if (lowest_pcie_addr == ~(u64)0) { in brcm_pcie_get_rc_bar2_size_and_offset()
797 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_rc_bar2_size_and_offset()
798 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
801 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
804 if (ret <= 0) { in brcm_pcie_get_rc_bar2_size_and_offset()
806 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
807 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
809 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
813 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
814 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
816 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
819 *rc_bar2_size = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
823 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_rc_bar2_size_and_offset()
825 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_rc_bar2_size_and_offset()
826 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_rc_bar2_size_and_offset()
827 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_rc_bar2_size_and_offset()
828 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_rc_bar2_size_and_offset()
831 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_rc_bar2_size_and_offset()
834 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
836 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_rc_bar2_size_and_offset()
837 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_rc_bar2_size_and_offset()
844 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
845 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
849 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
850 * region at location 0 (since we have to allow some space for in brcm_pcie_get_rc_bar2_size_and_offset()
854 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || in brcm_pcie_get_rc_bar2_size_and_offset()
856 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", in brcm_pcie_get_rc_bar2_size_and_offset()
858 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
861 return 0; in brcm_pcie_get_rc_bar2_size_and_offset()
864 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
867 void __iomem *base = pcie->base; in brcm_pcie_setup()
871 int num_out_wins = 0; in brcm_pcie_setup()
875 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
878 if (pcie->type == BCM2711) in brcm_pcie_setup()
879 pcie->perst_set(pcie, 1); in brcm_pcie_setup()
884 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
887 if (is_bmips(pcie)) in brcm_pcie_setup()
897 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it in brcm_pcie_setup()
898 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. in brcm_pcie_setup()
900 if (is_bmips(pcie)) in brcm_pcie_setup()
901 burst = 0x1; /* 256 bytes */ in brcm_pcie_setup()
902 else if (pcie->type == BCM2711) in brcm_pcie_setup()
903 burst = 0x0; /* 128 bytes */ in brcm_pcie_setup()
904 else if (pcie->type == BCM7278) in brcm_pcie_setup()
905 burst = 0x3; /* 512 bytes */ in brcm_pcie_setup()
907 burst = 0x2; /* 512 bytes */ in brcm_pcie_setup()
921 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, in brcm_pcie_setup()
934 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
935 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
937 if (memc == 0) in brcm_pcie_setup()
938 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); in brcm_pcie_setup()
951 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
954 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
956 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
958 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
959 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
960 return -EINVAL; in brcm_pcie_setup()
963 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
968 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
973 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
975 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
984 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
987 u32p_replace_bits(&tmp, 0x060400, in brcm_pcie_setup()
991 bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
992 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
993 struct resource *res = entry->res; in brcm_pcie_setup()
999 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1000 return -EINVAL; in brcm_pcie_setup()
1003 if (is_bmips(pcie)) { in brcm_pcie_setup()
1004 u64 start = res->start; in brcm_pcie_setup()
1007 /* bmips PCIe outbound windows have a 128MB max size */ in brcm_pcie_setup()
1010 for (j = 0; j < nwins; j++, start += SZ_128M) in brcm_pcie_setup()
1011 brcm_pcie_set_outbound_win(pcie, j, start, in brcm_pcie_setup()
1012 start - entry->offset, in brcm_pcie_setup()
1016 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1017 res->start - entry->offset, in brcm_pcie_setup()
1022 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1028 return 0; in brcm_pcie_setup()
1031 static int brcm_pcie_start_link(struct brcm_pcie *pcie) in brcm_pcie_start_link() argument
1033 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1034 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1041 pcie->perst_set(pcie, 0); in brcm_pcie_start_link()
1044 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification in brcm_pcie_start_link()
1045 * sections 2.2, PCIe r5.0, 6.6.1. in brcm_pcie_start_link()
1051 * configure RC. Intermittently check status for link-up, up to a in brcm_pcie_start_link()
1054 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1057 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_start_link()
1059 return -ENODEV; in brcm_pcie_start_link()
1062 if (pcie->gen) in brcm_pcie_start_link()
1063 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1065 if (pcie->ssc) { in brcm_pcie_start_link()
1066 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_start_link()
1067 if (ret == 0) in brcm_pcie_start_link()
1088 return 0; in brcm_pcie_start_link()
1106 sr->num_supplies = ARRAY_SIZE(supplies); in alloc_subdev_regulators()
1107 for (i = 0; i < ARRAY_SIZE(supplies); i++) in alloc_subdev_regulators()
1108 sr->supplies[i].supply = supplies[i]; in alloc_subdev_regulators()
1116 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus() local
1117 struct device *dev = &bus->dev; in brcm_pcie_add_bus()
1121 if (!bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_add_bus()
1122 return 0; in brcm_pcie_add_bus()
1124 if (dev->of_node) { in brcm_pcie_add_bus()
1131 pcie->sr = sr; in brcm_pcie_add_bus()
1133 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1136 pcie->sr = NULL; in brcm_pcie_add_bus()
1140 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1143 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1144 pcie->sr = NULL; in brcm_pcie_add_bus()
1149 brcm_pcie_start_link(pcie); in brcm_pcie_add_bus()
1150 return 0; in brcm_pcie_add_bus()
1155 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus() local
1156 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1157 struct device *dev = &bus->dev; in brcm_pcie_remove_bus()
1159 if (!sr || !bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_remove_bus()
1162 if (regulator_bulk_disable(sr->num_supplies, sr->supplies)) in brcm_pcie_remove_bus()
1164 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_remove_bus()
1165 pcie->sr = NULL; in brcm_pcie_remove_bus()
1168 /* L23 is a low-power PCIe link state */
1169 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1171 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1183 for (i = 0; i < 15 && !l23; i++) { in brcm_pcie_enter_l23()
1191 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1194 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1204 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1205 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1206 u32 tmp, combined_mask = 0; in brcm_phy_cntl()
1208 void __iomem *base = pcie->base; in brcm_phy_cntl()
1211 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1212 val = start ? BIT_MASK(shifts[i]) : 0; in brcm_phy_cntl()
1221 val = start ? combined_mask : 0; in brcm_phy_cntl()
1223 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1225 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1230 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1232 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1235 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1237 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1240 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1242 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1245 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1246 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1248 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1252 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); in brcm_pcie_turn_off()
1260 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1261 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1268 if (device_may_wakeup(&dev->dev)) { in pci_dev_may_wakeup()
1270 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n"); in pci_dev_may_wakeup()
1277 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend_noirq() local
1278 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_suspend_noirq()
1281 brcm_pcie_turn_off(pcie); in brcm_pcie_suspend_noirq()
1287 if (brcm_phy_stop(pcie)) in brcm_pcie_suspend_noirq()
1290 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1296 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1299 * downstream device is enabled as a wake-up source, do not in brcm_pcie_suspend_noirq()
1302 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1303 pci_walk_bus(bridge->bus, pci_dev_may_wakeup, in brcm_pcie_suspend_noirq()
1304 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1305 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1306 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1307 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1310 reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1315 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1317 return 0; in brcm_pcie_suspend_noirq()
1322 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume_noirq() local
1327 base = pcie->base; in brcm_pcie_resume_noirq()
1328 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1332 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1336 ret = brcm_phy_start(pcie); in brcm_pcie_resume_noirq()
1341 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1343 /* SERDES_IDDQ = 0 */ in brcm_pcie_resume_noirq()
1345 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); in brcm_pcie_resume_noirq()
1351 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume_noirq()
1355 if (pcie->sr) { in brcm_pcie_resume_noirq()
1356 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1363 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1365 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1366 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1374 ret = brcm_pcie_start_link(pcie); in brcm_pcie_resume_noirq()
1378 if (pcie->msi) in brcm_pcie_resume_noirq()
1379 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1381 return 0; in brcm_pcie_resume_noirq()
1384 if (pcie->sr) in brcm_pcie_resume_noirq()
1385 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1387 reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1389 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1393 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1395 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1396 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1397 if (brcm_phy_stop(pcie)) in __brcm_pcie_remove()
1398 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1399 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1400 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1401 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1406 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1407 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1409 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1410 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1411 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1415 [RGR1_SW_INIT_1] = 0x9210,
1416 [EXT_CFG_INDEX] = 0x9000,
1417 [EXT_CFG_DATA] = 0x9004,
1421 [RGR1_SW_INIT_1] = 0x8010,
1422 [EXT_CFG_INDEX] = 0x8300,
1423 [EXT_CFG_DATA] = 0x8304,
1455 [RGR1_SW_INIT_1] = 0xc010,
1456 [EXT_CFG_INDEX] = 0x9000,
1457 [EXT_CFG_DATA] = 0x9004,
1475 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1476 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1477 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1478 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1479 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1480 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1481 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1482 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1504 struct device_node *np = pdev->dev.of_node; in brcm_pcie_probe()
1507 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1510 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1512 return -ENOMEM; in brcm_pcie_probe()
1514 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1517 return -EINVAL; in brcm_pcie_probe()
1520 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1521 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1522 pcie->np = np; in brcm_pcie_probe()
1523 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1524 pcie->type = data->type; in brcm_pcie_probe()
1525 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1526 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1528 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1529 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1530 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1532 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1533 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1534 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1537 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1539 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1541 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1543 dev_err(&pdev->dev, "could not enable clock\n"); in brcm_pcie_probe()
1546 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1547 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1548 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1549 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1551 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1552 if (IS_ERR(pcie->perst_reset)) { in brcm_pcie_probe()
1553 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1554 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1557 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1559 dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1561 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1563 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1564 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1568 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1572 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1573 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1574 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1575 ret = -ENODEV; in brcm_pcie_probe()
1580 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1582 if (msi_np == pcie->np) in brcm_pcie_probe()
1583 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1588 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1593 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops; in brcm_pcie_probe()
1594 bridge->sysdata = pcie; in brcm_pcie_probe()
1596 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1599 if (!ret && !brcm_pcie_link_up(pcie)) in brcm_pcie_probe()
1600 ret = -ENODEV; in brcm_pcie_probe()
1607 return 0; in brcm_pcie_probe()
1610 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1625 .name = "brcm-pcie",
1633 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");