Lines Matching +full:broken +full:- +full:prefetch +full:- +full:cmd
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
84 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); in pci_dev_d3_sleep()
97 return dev->reset_methods[0] != 0; in pci_reset_supported()
116 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
127 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
144 * measured in 32-bit words, not bytes.
186 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
197 max = bus->busn_res.end; in pci_bus_max_busnr()
198 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
208 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
220 return -EIO; in pci_status_get_and_clear_errors()
234 struct resource *res = &pdev->resource[bar]; in __pci_ioremap_resource()
235 resource_size_t start = res->start; in __pci_ioremap_resource()
241 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in __pci_ioremap_resource()
266 * pci_dev_str_match_path - test if a path string matches a device
277 * A path for a device can be obtained using 'lspci -t'. Using a path
294 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
296 return -ENOMEM; in pci_dev_str_match_path()
304 ret = -EINVAL; in pci_dev_str_match_path()
308 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
334 ret = -EINVAL; in pci_dev_str_match_path()
339 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
340 bus == dev->bus->number && in pci_dev_str_match_path()
341 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
349 * pci_dev_str_match - test if a string matches a device
366 * through the use of 'lspci -t'.
371 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
393 return -EINVAL; in pci_dev_str_match()
401 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
402 (!device || device == dev->device) && in pci_dev_str_match()
404 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
406 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
436 while ((*ttl)--) { in __pci_find_next_cap_ttl()
462 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
488 * pci_find_capability - query for devices' capabilities
503 * %PCI_CAP_ID_PCIX PCI-X
510 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
512 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
519 * pci_bus_find_capability - query for devices' capabilities
546 * pci_find_next_ext_capability - Find an extended capability
554 * vendor-specific capability, and this provides a way to find them all.
563 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
565 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
581 while (ttl-- > 0) { in pci_find_next_ext_capability()
598 * pci_find_ext_capability - Find an extended capability
618 * pci_get_dsn - Read and return the 8-byte Device Serial Number
661 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
671 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
680 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
689 * NB. To be 100% safe against broken PCI devices, the caller should take
699 * pci_find_ht_capability - query a device's HyperTransport capabilities
713 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
722 * pci_find_vsec_capability - Find a vendor-specific extended capability
725 * @cap: Vendor-specific capability ID
737 if (vendor != dev->vendor) in pci_find_vsec_capability()
755 * pci_find_dvsec_capability - Find DVSEC for vendor
758 * @dvsec: Designated Vendor-specific capability ID
787 * pci_find_parent_resource - return resource region of parent bus of given
798 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
810 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
811 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
816 * be both a positively-decoded aperture and a in pci_find_parent_resource()
817 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
818 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
830 * pci_find_resource - Return matching PCI device resource
843 struct resource *r = &dev->resource[i]; in pci_find_resource()
845 if (r->start && resource_contains(r, res)) in pci_find_resource()
854 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
869 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
882 * pci_request_acs - ask for ACS to be enabled if supported
892 * pci_disable_acs_redir - disable ACS redirect capabilities
933 pos = dev->acs_cap; in pci_disable_acs_redir()
950 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
959 pos = dev->acs_cap; in pci_std_enable_acs()
979 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_std_enable_acs()
986 * pci_enable_acs - enable ACS if hardware support it
1011 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1089 * pci_update_current_state - Read power state of given device and cache it
1103 dev->current_state = PCI_D3cold; in pci_update_current_state()
1104 } else if (dev->pm_cap) { in pci_update_current_state()
1107 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1109 dev->current_state = PCI_D3cold; in pci_update_current_state()
1112 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_update_current_state()
1114 dev->current_state = state; in pci_update_current_state()
1119 * pci_refresh_power_state - Refresh the given device's power state data
1128 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1132 * pci_platform_power_transition - Use platform to change device power state
1143 else if (!dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1144 dev->current_state = PCI_D0; in pci_platform_power_transition()
1152 pm_request_resume(&pci_dev->dev); in pci_resume_one()
1157 * pci_resume_bus - Walk given bus and runtime resume devices on it
1186 * Wait for the device to return a non-CRS completion. Read the in pci_dev_wait()
1195 return -ENOTTY; in pci_dev_wait()
1204 delay - 1, reset_type); in pci_dev_wait()
1205 return -ENOTTY; in pci_dev_wait()
1217 delay - 1, reset_type); in pci_dev_wait()
1225 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1232 * pci_power_up - Put the given device into D0
1240 * put the device in D0 via non-PCI means.
1250 if (!dev->pm_cap) { in pci_power_up()
1253 dev->current_state = PCI_D0; in pci_power_up()
1255 dev->current_state = state; in pci_power_up()
1257 return -EIO; in pci_power_up()
1260 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_power_up()
1263 pci_power_name(dev->current_state)); in pci_power_up()
1264 dev->current_state = PCI_D3cold; in pci_power_up()
1265 return -EIO; in pci_power_up()
1270 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) && in pci_power_up()
1280 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0); in pci_power_up()
1289 dev->current_state = PCI_D0; in pci_power_up()
1297 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1316 if (dev->current_state == PCI_D0) in pci_set_full_power_state()
1322 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_full_power_state()
1323 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_full_power_state()
1324 if (dev->current_state != PCI_D0) { in pci_set_full_power_state()
1326 pci_power_name(dev->current_state)); in pci_set_full_power_state()
1344 if (dev->bus->self) in pci_set_full_power_state()
1345 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_full_power_state()
1351 * __pci_dev_set_current_state - Set current state of a PCI device
1359 dev->current_state = state; in __pci_dev_set_current_state()
1364 * pci_bus_set_current_state - Walk given bus and set current state of devices
1386 * pci_set_low_power_state - Put a PCI device into a low-power state.
1391 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1394 * -EINVAL if the requested state is invalid.
1395 * -EIO if device does not support PCI PM or its PM capabilities register has a
1404 if (!dev->pm_cap) in pci_set_low_power_state()
1405 return -EIO; in pci_set_low_power_state()
1409 * we're already in a low-power state, we can only go deeper. E.g., in pci_set_low_power_state()
1413 if (dev->current_state <= PCI_D3cold && dev->current_state > state) { in pci_set_low_power_state()
1415 pci_power_name(dev->current_state), in pci_set_low_power_state()
1417 return -EINVAL; in pci_set_low_power_state()
1421 if ((state == PCI_D1 && !dev->d1_support) in pci_set_low_power_state()
1422 || (state == PCI_D2 && !dev->d2_support)) in pci_set_low_power_state()
1423 return -EIO; in pci_set_low_power_state()
1425 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1428 pci_power_name(dev->current_state), in pci_set_low_power_state()
1430 dev->current_state = PCI_D3cold; in pci_set_low_power_state()
1431 return -EIO; in pci_set_low_power_state()
1438 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_set_low_power_state()
1446 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1447 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_low_power_state()
1448 if (dev->current_state != state) in pci_set_low_power_state()
1450 pci_power_name(dev->current_state), in pci_set_low_power_state()
1453 if (dev->bus->self) in pci_set_low_power_state()
1454 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_low_power_state()
1479 if (dev->current_state == state) in __pci_set_power_state()
1489 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in __pci_set_power_state()
1503 if (dev->current_state == PCI_D3cold) in __pci_set_power_state()
1504 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold, locked); in __pci_set_power_state()
1516 * pci_set_power_state - Set the power state of a PCI device
1524 * -EINVAL if the requested state is invalid.
1525 * -EIO if device does not support PCI PM or its PM capabilities register has a
1553 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1554 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1582 return -ENOMEM; in pci_save_pcie_state()
1585 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1604 if (bridge && bridge->ltr_path) { in pci_bridge_reconfigure_ltr()
1607 pci_dbg(bridge, "re-enabling LTR\n"); in pci_bridge_reconfigure_ltr()
1627 * Check and re-configure the bit here before restoring device. in pci_restore_pcie_state()
1632 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1654 return -ENOMEM; in pci_save_pcix_state()
1658 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1673 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1697 /* Some broken devices only support dword access to LTR */ in pci_save_ltr_state()
1698 cap = &save_state->cap.data[0]; in pci_save_ltr_state()
1713 /* Some broken devices only support dword access to LTR */ in pci_restore_ltr_state()
1714 cap = &save_state->cap.data[0]; in pci_restore_ltr_state()
1719 * pci_save_state - save the PCI configuration space of a device before
1728 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1730 i * 4, dev->saved_config_space[i]); in pci_save_state()
1732 dev->state_saved = true; in pci_save_state()
1760 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n", in pci_restore_config_dword()
1763 if (retry-- <= 0) in pci_restore_config_dword()
1780 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1782 pdev->saved_config_space[index], in pci_restore_config_space_range()
1788 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1793 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1797 * Force rewriting of prefetch registers to avoid S3 resume in pci_restore_config_space()
1827 res = pdev->resource + bar_idx; in pci_restore_rebar_state()
1836 * pci_restore_state - Restore the saved state of a PCI device
1841 if (!dev->state_saved) in pci_restore_state()
1871 dev->state_saved = false; in pci_restore_state()
1881 * pci_store_saved_state - Allocate and return an opaque struct containing
1894 if (!dev->state_saved) in pci_store_saved_state()
1899 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1900 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1906 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1907 sizeof(state->config_space)); in pci_store_saved_state()
1909 cap = state->cap; in pci_store_saved_state()
1910 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1911 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1912 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
1922 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1931 dev->state_saved = false; in pci_load_saved_state()
1936 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
1937 sizeof(state->config_space)); in pci_load_saved_state()
1939 cap = state->cap; in pci_load_saved_state()
1940 while (cap->size) { in pci_load_saved_state()
1943 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
1944 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
1945 return -EINVAL; in pci_load_saved_state()
1947 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
1949 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
1952 dev->state_saved = true; in pci_load_saved_state()
1958 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1982 u16 cmd; in do_pci_enable_device() local
1986 if (err < 0 && err != -EIO) in do_pci_enable_device()
1998 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
2003 pci_read_config_word(dev, PCI_COMMAND, &cmd); in do_pci_enable_device()
2004 if (cmd & PCI_COMMAND_INTX_DISABLE) in do_pci_enable_device()
2006 cmd & ~PCI_COMMAND_INTX_DISABLE); in do_pci_enable_device()
2013 * pci_reenable_device - Resume abandoned device
2022 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
2037 if (!dev->is_busmaster) in pci_enable_bridge()
2061 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
2063 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
2072 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2075 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2080 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
2085 * pci_enable_device_io - Initialize a device for use with IO space
2088 * Initialize device before it's used by a driver. Ask low-level code
2099 * pci_enable_device_mem - Initialize a device for use with Memory space
2102 * Initialize device before it's used by a driver. Ask low-level code
2113 * pci_enable_device - Initialize device before it's used by a driver.
2116 * Initialize device before it's used by a driver. Ask low-level code
2130 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2131 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2151 if (this->region_mask & (1 << i)) in pcim_release()
2154 if (this->mwi) in pcim_release()
2157 if (this->restore_intx) in pcim_release()
2158 pci_intx(dev, this->orig_intx); in pcim_release()
2160 if (this->enabled && !this->pinned) in pcim_release()
2168 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); in get_pci_dr()
2175 return devres_get(&pdev->dev, new_dr, NULL, NULL); in get_pci_dr()
2181 return devres_find(&pdev->dev, pcim_release, NULL, NULL); in find_pci_dr()
2186 * pcim_enable_device - Managed pci_enable_device()
2198 return -ENOMEM; in pcim_enable_device()
2199 if (dr->enabled) in pcim_enable_device()
2204 pdev->is_managed = 1; in pcim_enable_device()
2205 dr->enabled = 1; in pcim_enable_device()
2212 * pcim_pin_device - Pin managed PCI device
2224 WARN_ON(!dr || !dr->enabled); in pcim_pin_device()
2226 dr->pinned = 1; in pcim_pin_device()
2231 * pcibios_device_add - provide arch specific hooks when adding device dev
2244 * pcibios_release_device - provide arch specific hooks when releasing
2255 * pcibios_disable_device - disable arch specific PCI resources for device dev
2265 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2269 * Permits the platform to provide architecture-specific functionality when
2289 * pci_disable_enabled_device - Disable device without updating enable_cnt
2302 * pci_disable_device - Disable PCI device after use
2306 * anymore. This only involves disabling PCI bus-mastering, if active.
2317 dr->enabled = 0; in pci_disable_device()
2319 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2320 "disabling already-disabled device"); in pci_disable_device()
2322 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2327 dev->is_busmaster = 0; in pci_disable_device()
2332 * pcibios_set_pcie_reset_state - set reset state for device dev
2342 return -EINVAL; in pcibios_set_pcie_reset_state()
2346 * pci_set_pcie_reset_state - set reset state for device dev
2369 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2378 * pci_check_pme_status - Check if given device has generated PME.
2391 if (!dev->pm_cap) in pci_check_pme_status()
2394 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2413 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2422 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2423 dev->pme_poll = false; in pci_pme_wakeup()
2427 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2433 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2444 * pci_pme_capable - check the capability of PCI device to generate PME#
2450 if (!dev->pm_cap) in pci_pme_capable()
2453 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2463 struct pci_dev *pdev = pme_dev->dev; in pci_pme_list_scan()
2465 if (pdev->pme_poll) { in pci_pme_list_scan()
2466 struct pci_dev *bridge = pdev->bus->self; in pci_pme_list_scan()
2467 struct device *dev = &pdev->dev; in pci_pme_list_scan()
2468 struct device *bdev = bridge ? &bridge->dev : NULL; in pci_pme_list_scan()
2482 if (bridge->current_state != PCI_D0) in pci_pme_list_scan()
2492 pdev->current_state != PCI_D3cold) in pci_pme_list_scan()
2499 list_del(&pme_dev->list); in pci_pme_list_scan()
2513 if (!dev->pme_support) in __pci_pme_active()
2516 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2522 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2526 * pci_pme_restore - Restore PME configuration after config space restore.
2533 if (!dev->pme_support) in pci_pme_restore()
2536 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2537 if (dev->wakeup_prepared) { in pci_pme_restore()
2544 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2548 * pci_pme_active - enable or disable PCI device's PME# function
2570 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2579 if (dev->pme_poll) { in pci_pme_active()
2588 pme_dev->dev = dev; in pci_pme_active()
2590 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2599 if (pme_dev->dev == dev) { in pci_pme_active()
2600 list_del(&pme_dev->list); in pci_pme_active()
2614 * __pci_enable_wake - enable PCI device as wakeup event source
2620 * When such events involves platform-specific hooks, those hooks are
2628 * -EINVAL is returned if device is not supposed to wake up the system
2630 * the native mechanism fail to enable the generation of wake-up events
2637 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2640 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2647 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2653 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2674 dev->wakeup_prepared = true; in __pci_enable_wake()
2678 dev->wakeup_prepared = false; in __pci_enable_wake()
2685 * pci_enable_wake - change wakeup settings for a PCI device
2695 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2696 return -EINVAL; in pci_enable_wake()
2703 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2705 * @enable: True to enable wake-up event generation; false to disable
2708 * and this function allows them to set that up cleanly - pci_enable_wake()
2709 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2714 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2725 * pci_target_state - find an appropriate low power state for a given PCI dev
2756 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2757 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2760 if (dev->current_state == PCI_D3cold) in pci_target_state()
2762 else if (!dev->pm_cap) in pci_target_state()
2765 if (wakeup && dev->pme_support) { in pci_target_state()
2772 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2773 state--; in pci_target_state()
2777 else if (dev->pme_support & 1) in pci_target_state()
2785 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2795 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep()
2800 return -EIO; in pci_prepare_to_sleep()
2814 * pci_back_from_sleep - turn PCI device on during system-wide transition
2818 * Disable device's system wake-up capability and put it into D0.
2833 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2836 * Prepare @dev to generate wake-up events at run time and put it into a low
2844 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2846 return -EIO; in pci_finish_runtime_suspend()
2859 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2862 * Return true if the device itself is capable of generating wake-up events
2864 * PME and one of its upstream bridges can generate wake-up events.
2868 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2870 if (!dev->pme_support) in pci_dev_run_wake()
2873 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2877 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2880 while (bus->parent) { in pci_dev_run_wake()
2881 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2883 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2886 bus = bus->parent; in pci_dev_run_wake()
2890 if (bus->bridge) in pci_dev_run_wake()
2891 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2898 * pci_dev_need_resume - Check if it is necessary to resume the device.
2901 * Return 'true' if the device is not runtime-suspended or it has to be
2904 * (system-wide) transition.
2908 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2921 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2923 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2927 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2939 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2941 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2944 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
2947 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2951 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2954 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2960 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
2965 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2967 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2970 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2974 * pci_choose_state - Choose the power state of a PCI device.
2991 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
2992 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2998 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
3007 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
3013 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
3014 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
3030 .ident = "X299 DESIGNARE EX-CF",
3033 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
3051 * https://gitlab.freedesktop.org/drm/amd/-/issues/3229
3053 .ident = "Hewlett-Packard HP Pavilion 17 Notebook PC/1972",
3055 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
3065 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3085 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
3087 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
3094 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
3106 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
3129 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
3132 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
3144 * pci_bridge_d3_update - Update bridge D3 capabilities
3153 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
3165 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
3185 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
3186 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
3189 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
3190 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
3197 * pci_d3cold_enable - Enable D3cold for device
3206 if (dev->no_d3cold) { in pci_d3cold_enable()
3207 dev->no_d3cold = false; in pci_d3cold_enable()
3214 * pci_d3cold_disable - Disable D3cold for device
3223 if (!dev->no_d3cold) { in pci_d3cold_disable()
3224 dev->no_d3cold = true; in pci_d3cold_disable()
3231 * pci_pm_init - Initialize PM functions of given PCI device
3240 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3241 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3242 pm_runtime_enable(&dev->dev); in pci_pm_init()
3243 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3244 dev->wakeup_prepared = false; in pci_pm_init()
3246 dev->pm_cap = 0; in pci_pm_init()
3247 dev->pme_support = 0; in pci_pm_init()
3262 dev->pm_cap = pm; in pci_pm_init()
3263 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3264 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3265 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3266 dev->d3cold_allowed = true; in pci_pm_init()
3268 dev->d1_support = false; in pci_pm_init()
3269 dev->d2_support = false; in pci_pm_init()
3272 dev->d1_support = true; in pci_pm_init()
3274 dev->d2_support = true; in pci_pm_init()
3276 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3278 dev->d1_support ? " D1" : "", in pci_pm_init()
3279 dev->d2_support ? " D2" : ""); in pci_pm_init()
3290 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; in pci_pm_init()
3291 dev->pme_poll = true; in pci_pm_init()
3293 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3296 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3303 dev->imm_ready = 1; in pci_pm_init()
3333 return &dev->resource[bei]; in pci_ea_get_resource()
3337 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3338 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3341 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3399 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3408 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3418 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3440 if (ent_size != ent_offset - offset) { in pci_ea_read()
3442 ent_size, ent_offset - offset); in pci_ea_read()
3446 res->name = pci_name(dev); in pci_ea_read()
3447 res->start = start; in pci_ea_read()
3448 res->end = end; in pci_ea_read()
3449 res->flags = flags; in pci_ea_read()
3459 bei - PCI_EA_BEI_VF_BAR0, res, prop); in pci_ea_read()
3482 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3489 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3500 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3504 * _pci_add_cap_save_buffer - allocate buffer for saving given
3527 return -ENOMEM; in _pci_add_cap_save_buffer()
3529 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3530 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3531 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3548 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3562 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3577 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3582 * pci_configure_ari - enable or disable ARI forwarding
3593 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3596 bridge = dev->bus->self; in pci_configure_ari()
3607 bridge->ari_enabled = 1; in pci_configure_ari()
3611 bridge->ari_enabled = 0; in pci_configure_ari()
3620 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3627 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3637 * pci_acs_enabled - test ACS against required flags for a given device
3647 * opportunity for peer-to-peer access. We therefore return 'true'
3661 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3670 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3672 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3686 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3687 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3694 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3703 if (!pdev->multifunction) in pci_acs_enabled()
3717 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3736 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3739 parent = pdev->bus->self; in pci_acs_path_enabled()
3746 * pci_acs_init - Initialize ACS if hardware supports it
3751 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3763 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3768 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3769 * Returns -ENOENT if no ctrl register for the BAR could be found.
3778 return -ENOTSUPP; in pci_rebar_find_pos()
3793 return -ENOENT; in pci_rebar_find_pos()
3797 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3817 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3826 * pci_rebar_get_current_size - get the current size of a BAR
3847 * pci_rebar_set_size - set a new size for a BAR
3872 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3881 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3886 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3895 if (dev->is_virtfn) in pci_enable_atomic_ops_to_root()
3896 return -EINVAL; in pci_enable_atomic_ops_to_root()
3899 return -EINVAL; in pci_enable_atomic_ops_to_root()
3905 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3914 return -EINVAL; in pci_enable_atomic_ops_to_root()
3917 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3918 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3927 return -EINVAL; in pci_enable_atomic_ops_to_root()
3933 return -EINVAL; in pci_enable_atomic_ops_to_root()
3942 return -EINVAL; in pci_enable_atomic_ops_to_root()
3945 bus = bus->parent; in pci_enable_atomic_ops_to_root()
3955 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3960 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3961 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3969 if (pci_ari_enabled(dev->bus)) in pci_swizzle_interrupt_pin()
3972 slot = PCI_SLOT(dev->devfn); in pci_swizzle_interrupt_pin()
3974 return (((pin - 1) + slot) % 4) + 1; in pci_swizzle_interrupt_pin()
3981 pin = dev->pin; in pci_get_interrupt_pin()
3983 return -1; in pci_get_interrupt_pin()
3985 while (!pci_is_root_bus(dev->bus)) { in pci_get_interrupt_pin()
3987 dev = dev->bus->self; in pci_get_interrupt_pin()
3994 * pci_common_swizzle - swizzle INTx all the way to root bridge
3998 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
4005 while (!pci_is_root_bus(dev->bus)) { in pci_common_swizzle()
4007 dev = dev->bus->self; in pci_common_swizzle()
4010 return PCI_SLOT(dev->devfn); in pci_common_swizzle()
4015 * pci_release_region - Release a PCI bar
4039 dr->region_mask &= ~(1 << bar); in pci_release_region()
4044 * __pci_request_region - Reserved PCI I/O and memory resource
4083 dr->region_mask |= 1 << bar; in __pci_request_region()
4089 &pdev->resource[bar]); in __pci_request_region()
4090 return -EBUSY; in __pci_request_region()
4094 * pci_request_region - Reserve PCI I/O and memory resource
4114 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4143 while (--i >= 0) in __pci_request_selected_regions()
4147 return -EBUSY; in __pci_request_selected_regions()
4152 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4173 * pci_release_regions - Release reserved PCI I/O and memory resources
4184 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
4189 * pci_request_regions - Reserve PCI I/O and memory resources
4204 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions()
4209 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4226 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions_exclusive()
4242 return -EINVAL; in pci_register_io_range()
4246 return -ENOMEM; in pci_register_io_range()
4248 range->fwnode = fwnode; in pci_register_io_range()
4249 range->size = size; in pci_register_io_range()
4250 range->hw_start = addr; in pci_register_io_range()
4251 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4258 if (ret == -EEXIST) in pci_register_io_range()
4282 return (unsigned long)-1; in pci_address_to_pio()
4289 * pci_remap_iospace - Remap the memory mapped I/O space
4302 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4304 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4305 return -EINVAL; in pci_remap_iospace()
4307 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4308 return -EINVAL; in pci_remap_iospace()
4318 return -ENODEV; in pci_remap_iospace()
4325 * pci_unmap_iospace - Unmap the memory mapped I/O space
4335 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4350 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4366 return -ENOMEM; in devm_pci_remap_iospace()
4381 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4411 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4425 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4440 return IOMEM_ERR_PTR(-EINVAL); in devm_pci_remap_cfg_resource()
4445 if (res->name) in devm_pci_remap_cfg_resource()
4447 res->name); in devm_pci_remap_cfg_resource()
4451 return IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4453 if (!devm_request_mem_region(dev, res->start, size, name)) { in devm_pci_remap_cfg_resource()
4455 return IOMEM_ERR_PTR(-EBUSY); in devm_pci_remap_cfg_resource()
4458 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); in devm_pci_remap_cfg_resource()
4461 devm_release_mem_region(dev, res->start, size); in devm_pci_remap_cfg_resource()
4462 dest_ptr = IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4471 u16 old_cmd, cmd; in __pci_set_master() local
4475 cmd = old_cmd | PCI_COMMAND_MASTER; in __pci_set_master()
4477 cmd = old_cmd & ~PCI_COMMAND_MASTER; in __pci_set_master()
4478 if (cmd != old_cmd) { in __pci_set_master()
4481 pci_write_config_word(dev, PCI_COMMAND, cmd); in __pci_set_master()
4483 dev->is_busmaster = enable; in __pci_set_master()
4487 * pcibios_setup - process "pci=" kernel boot arguments
4499 * pcibios_set_master - enable PCI bus-mastering for device dev
4502 * Enables PCI bus-mastering for the device. This is the default
4526 * pci_set_master - enables bus-mastering for device dev
4529 * Enables bus-mastering on the device and calls pcibios_set_master()
4540 * pci_clear_master - disables bus-mastering for device dev
4550 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4555 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4557 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4564 return -EINVAL; in pci_set_cacheline_size()
4583 return -EINVAL; in pci_set_cacheline_size()
4588 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4591 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4593 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4601 u16 cmd; in pci_set_mwi()
4607 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_set_mwi()
4608 if (!(cmd & PCI_COMMAND_INVALIDATE)) { in pci_set_mwi()
4609 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4610 cmd |= PCI_COMMAND_INVALIDATE; in pci_set_mwi()
4611 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_set_mwi()
4619 * pcim_set_mwi - a device-managed pci_set_mwi()
4624 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4632 return -ENOMEM; in pcim_set_mwi()
4634 dr->mwi = 1; in pcim_set_mwi()
4640 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4643 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4646 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4659 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4662 * Disables PCI Memory-Write-Invalidate transaction on the device
4667 u16 cmd; in pci_clear_mwi() local
4669 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_clear_mwi()
4670 if (cmd & PCI_COMMAND_INVALIDATE) { in pci_clear_mwi()
4671 cmd &= ~PCI_COMMAND_INVALIDATE; in pci_clear_mwi()
4672 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_clear_mwi()
4679 * pci_disable_parity - disable parity checking for device
4686 u16 cmd; in pci_disable_parity() local
4688 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_disable_parity()
4689 if (cmd & PCI_COMMAND_PARITY) { in pci_disable_parity()
4690 cmd &= ~PCI_COMMAND_PARITY; in pci_disable_parity()
4691 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_disable_parity()
4696 * pci_intx - enables/disables PCI INTx for device dev
4719 if (dr && !dr->restore_intx) { in pci_intx()
4720 dr->restore_intx = 1; in pci_intx()
4721 dr->orig_intx = !enable; in pci_intx()
4729 struct pci_bus *bus = dev->bus; in pci_check_and_set_intx_mask()
4745 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); in pci_check_and_set_intx_mask()
4764 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); in pci_check_and_set_intx_mask()
4773 * pci_check_and_mask_intx - mask INTx on pending interrupt
4786 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4800 * pci_wait_for_pending_transaction - wait for pending transaction
4816 * pcie_flr - initiate a PCIe function level reset
4829 if (dev->imm_ready) in pcie_flr()
4844 * pcie_reset_flr - initiate a PCIe function level reset
4852 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_reset_flr()
4853 return -ENOTTY; in pcie_reset_flr()
4855 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) in pcie_reset_flr()
4856 return -ENOTTY; in pcie_reset_flr()
4872 return -ENOTTY; in pci_af_flr()
4874 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4875 return -ENOTTY; in pci_af_flr()
4879 return -ENOTTY; in pci_af_flr()
4885 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4895 if (dev->imm_ready) in pci_af_flr()
4910 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4916 * PCI_D0. If that's the case and the device is not in a low-power state
4920 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4928 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4929 return -ENOTTY; in pci_pm_reset()
4931 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4933 return -ENOTTY; in pci_pm_reset()
4938 if (dev->current_state != PCI_D0) in pci_pm_reset()
4939 return -EINVAL; in pci_pm_reset()
4943 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4948 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4951 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
4955 * pcie_wait_for_link_status - Wait for link status change
4960 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
4981 return -ETIMEDOUT; in pcie_wait_for_link_status()
4985 * pcie_retrain_link - Request a link retrain and wait for it to complete
4993 * Return 0 if successful, or -ETIMEDOUT if training has not completed
5011 if (pdev->clear_retrain_link) { in pcie_retrain_link()
5032 * pcie_wait_for_link_delay - Wait until link is active or inactive
5048 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
5082 * pcie_wait_for_link - Wait until link is active or inactive
5106 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
5107 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
5108 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
5109 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
5110 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
5117 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
5119 * @reset_type: reset type in human-readable form
5129 * Return 0 on success or -ENOTTY if the first device on the secondary bus
5147 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
5151 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
5157 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
5163 child = pci_dev_get(list_first_entry(&dev->subordinate->devices, in pci_bridge_wait_for_secondary_bus()
5168 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
5185 * device that did not respond is a broken device. Also device can in pci_bridge_wait_for_secondary_bus()
5201 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay)) in pci_bridge_wait_for_secondary_bus()
5209 if (!dev->link_active_reporting) in pci_bridge_wait_for_secondary_bus()
5210 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5214 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5217 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT); in pci_bridge_wait_for_secondary_bus()
5225 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
5229 PCIE_RESET_READY_POLL_MS - delay); in pci_bridge_wait_for_secondary_bus()
5256 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5260 * Devices on the secondary bus are left in power-on state.
5274 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
5275 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
5276 return -ENOTTY; in pci_parent_bus_reset()
5278 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
5280 return -ENOTTY; in pci_parent_bus_reset()
5285 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
5290 int rc = -ENOTTY; in pci_reset_hotplug_slot()
5292 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
5295 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
5296 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
5298 module_put(hotplug->owner); in pci_reset_hotplug_slot()
5305 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
5306 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
5307 return -ENOTTY; in pci_dev_reset_slot_function()
5309 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
5317 if (rc != -ENOTTY) in pci_reset_bus_function()
5325 device_lock(&dev->dev); in pci_dev_lock()
5333 if (device_trylock(&dev->dev)) { in pci_dev_trylock()
5336 device_unlock(&dev->dev); in pci_dev_trylock()
5346 device_unlock(&dev->dev); in pci_dev_unlock()
5353 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
5356 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
5357 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5360 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5361 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5364 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5366 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5373 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5375 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5376 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5384 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5389 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5390 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5393 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5394 err_handler->reset_done(dev); in pci_dev_restore()
5397 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5416 m = pdev->reset_methods[i]; in reset_method_show()
5452 pdev->reset_methods[0] = 0; in reset_method_store()
5464 return -ENOMEM; in reset_method_store()
5485 if (n == PCI_NUM_RESET_METHODS - 1) { in reset_method_store()
5495 /* Warn if dev-specific supported but not highest priority */ in reset_method_store()
5498 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user"); in reset_method_store()
5499 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods)); in reset_method_store()
5506 return -EINVAL; in reset_method_store()
5523 return a->mode; in pci_dev_reset_method_attr_is_visible()
5532 * __pci_reset_function_locked - reset a PCI device function while holding
5558 * A reset method returns -ENOTTY if it doesn't support this device and in __pci_reset_function_locked()
5563 * mechanisms might be broken on the device. in __pci_reset_function_locked()
5566 m = dev->reset_methods[i]; in __pci_reset_function_locked()
5568 return -ENOTTY; in __pci_reset_function_locked()
5573 if (rc != -ENOTTY) in __pci_reset_function_locked()
5577 return -ENOTTY; in __pci_reset_function_locked()
5582 * pci_init_reset_methods - check whether device can be safely reset
5587 * other functions in the same device. The PCI device must be in D0-D3hot
5605 dev->reset_methods[i++] = m; in pci_init_reset_methods()
5606 else if (rc != -ENOTTY) in pci_init_reset_methods()
5610 dev->reset_methods[i] = 0; in pci_init_reset_methods()
5614 * pci_reset_function - quiesce and reset a PCI device function
5634 return -ENOTTY; in pci_reset_function()
5649 * pci_reset_function_locked - quiesce and reset a PCI device function
5670 return -ENOTTY; in pci_reset_function_locked()
5683 * pci_try_reset_function - quiesce and reset a PCI device function
5686 * Same as above, except return -EAGAIN if unable to lock device.
5693 return -ENOTTY; in pci_try_reset_function()
5696 return -EAGAIN; in pci_try_reset_function()
5713 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resettable()
5716 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resettable()
5717 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resettable()
5718 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_bus_resettable()
5730 pci_dev_lock(bus->self); in pci_bus_lock()
5731 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5732 if (dev->subordinate) in pci_bus_lock()
5733 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5744 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5745 if (dev->subordinate) in pci_bus_unlock()
5746 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5750 pci_dev_unlock(bus->self); in pci_bus_unlock()
5758 if (!pci_dev_trylock(bus->self)) in pci_bus_trylock()
5761 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5762 if (dev->subordinate) { in pci_bus_trylock()
5763 if (!pci_bus_trylock(dev->subordinate)) in pci_bus_trylock()
5771 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5772 if (dev->subordinate) in pci_bus_trylock()
5773 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5777 pci_dev_unlock(bus->self); in pci_bus_trylock()
5786 if (slot->bus->self && in pci_slot_resettable()
5787 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resettable()
5790 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resettable()
5791 if (!dev->slot || dev->slot != slot) in pci_slot_resettable()
5793 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resettable()
5794 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_slot_resettable()
5806 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5807 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5809 if (dev->subordinate) in pci_slot_lock()
5810 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5821 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5822 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5824 if (dev->subordinate) in pci_slot_unlock()
5825 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5836 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5837 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5839 if (dev->subordinate) { in pci_slot_trylock()
5840 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5851 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5852 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5854 if (dev->subordinate) in pci_slot_trylock()
5855 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5870 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5872 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5873 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5886 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5888 if (dev->subordinate) { in pci_bus_restore_locked()
5890 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5903 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5904 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5907 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5908 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5921 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5922 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5925 if (dev->subordinate) { in pci_slot_restore_locked()
5927 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5937 return -ENOTTY; in pci_slot_reset()
5944 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5953 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5965 * __pci_reset_slot - Try to reset a PCI slot
5977 * Same as above except return -EAGAIN if the slot cannot be locked
5990 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); in __pci_reset_slot()
5994 rc = -EAGAIN; in __pci_reset_slot()
6003 if (!bus->self || !pci_bus_resettable(bus)) in pci_bus_reset()
6004 return -ENOTTY; in pci_bus_reset()
6013 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
6021 * pci_bus_error_reset - reset the bridge's subordinate bus
6030 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
6034 return -ENOTTY; in pci_bus_error_reset()
6037 if (list_empty(&bus->slots)) in pci_bus_error_reset()
6040 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
6044 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
6052 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); in pci_bus_error_reset()
6056 * pci_probe_reset_bus - probe whether a PCI bus can be reset
6068 * __pci_reset_bus - Try to reset a PCI bus
6071 * Same as above except return -EAGAIN if the bus cannot be locked
6084 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
6088 rc = -EAGAIN; in __pci_reset_bus()
6094 * pci_reset_bus - Try to reset a PCI bus
6097 * Same as above except return -EAGAIN if the bus cannot be locked
6101 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
6102 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
6107 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
6120 return -EINVAL; in pcix_get_max_mmrbc()
6123 return -EINVAL; in pcix_get_max_mmrbc()
6130 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
6139 u16 cmd; in pcix_get_mmrbc() local
6143 return -EINVAL; in pcix_get_mmrbc()
6145 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) in pcix_get_mmrbc()
6146 return -EINVAL; in pcix_get_mmrbc()
6148 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); in pcix_get_mmrbc()
6153 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
6165 u16 cmd; in pcix_set_mmrbc() local
6168 return -EINVAL; in pcix_set_mmrbc()
6170 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
6174 return -EINVAL; in pcix_set_mmrbc()
6177 return -EINVAL; in pcix_set_mmrbc()
6180 return -E2BIG; in pcix_set_mmrbc()
6182 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) in pcix_set_mmrbc()
6183 return -EINVAL; in pcix_set_mmrbc()
6185 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; in pcix_set_mmrbc()
6187 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
6188 return -EIO; in pcix_set_mmrbc()
6190 cmd &= ~PCI_X_CMD_MAX_READ; in pcix_set_mmrbc()
6191 cmd |= v << 2; in pcix_set_mmrbc()
6192 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) in pcix_set_mmrbc()
6193 return -EIO; in pcix_set_mmrbc()
6200 * pcie_get_readrq - get PCI Express read request size
6216 * pcie_set_readrq - set PCI Express maximum memory read request
6227 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); in pcie_set_readrq()
6230 return -EINVAL; in pcie_set_readrq()
6244 v = (ffs(rq) - 8) << 12; in pcie_set_readrq()
6246 if (bridge->no_inc_mrrs) { in pcie_set_readrq()
6251 return -EINVAL; in pcie_set_readrq()
6263 * pcie_get_mps - get PCI Express maximum payload size
6279 * pcie_set_mps - set PCI Express maximum payload size
6292 return -EINVAL; in pcie_set_mps()
6294 v = ffs(mps) - 8; in pcie_set_mps()
6295 if (v > dev->pcie_mpss) in pcie_set_mps()
6296 return -EINVAL; in pcie_set_mps()
6307 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6364 * pcie_get_speed_cap - query for the PCI device's link speed capability
6385 /* PCIe r3.0-compliant */ in pcie_get_speed_cap()
6400 * pcie_get_width_cap - query for the PCI device's link width capability
6419 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6441 * __pcie_print_link_status - Report the PCI device's link speed and width
6474 * pcie_print_link_status - Report the PCI device's link speed and width
6486 * pci_select_bars - Make BAR mask from the type of resource
6520 * pci_set_vga_state - set VGA decode state on device and parents if requested
6532 u16 cmd; in pci_set_vga_state() local
6543 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_set_vga_state()
6545 cmd |= command_bits; in pci_set_vga_state()
6547 cmd &= ~command_bits; in pci_set_vga_state()
6548 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_set_vga_state()
6554 bus = dev->bus; in pci_set_vga_state()
6556 bridge = bus->self; in pci_set_vga_state()
6559 &cmd); in pci_set_vga_state()
6561 cmd |= PCI_BRIDGE_CTL_VGA; in pci_set_vga_state()
6563 cmd &= ~PCI_BRIDGE_CTL_VGA; in pci_set_vga_state()
6565 cmd); in pci_set_vga_state()
6567 bus = bus->parent; in pci_set_vga_state()
6580 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6584 return adev->power.flags.power_resources && in pci_pr3_present()
6585 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6591 * pci_add_dma_alias - Add a DMA devfn alias for a device
6596 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6597 * which is used to program permissible bus-devfn source addresses for DMA
6600 * from their logical bus-devfn. Examples include device quirks where the
6601 * device simply uses the wrong devfn, as well as non-transparent bridges
6615 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6616 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6618 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6619 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6620 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6625 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6638 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6639 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6640 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6641 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6654 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6660 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6662 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6665 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6670 * pci_real_dma_dev - Get PCI DMA device for PCI device
6673 * Permits the platform to provide architecture-specific functionality to
6690 * Arches that don't want to expose struct resource to userland as-is in
6697 *start = rsrc->start; in pci_resource_to_user()
6698 *end = rsrc->end; in pci_resource_to_user()
6705 * pci_specified_resource_alignment - get resource alignment specified by user.
6769 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6772 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6775 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6802 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6817 r->start = 0; in pci_request_resource_alignment()
6818 r->end = align - 1; in pci_request_resource_alignment()
6820 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6821 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6822 r->start = align; in pci_request_resource_alignment()
6823 r->end = r->start + size - 1; in pci_request_resource_alignment()
6825 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6832 * Later on, the kernel will assign page-aligned memory resource back
6844 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6846 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6849 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6857 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6858 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6875 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6877 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6878 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6880 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6881 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6882 r->start = 0; in pci_reassigndev_resource_alignment()
6905 if (count >= (PAGE_SIZE - 1)) in resource_alignment_store()
6906 return -EINVAL; in resource_alignment_store()
6910 return -ENOMEM; in resource_alignment_store()
6986 domain_nr = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
7004 if (bus->domain_nr < 0) in of_pci_bus_release_domain_nr()
7008 if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr) in of_pci_bus_release_domain_nr()
7009 ida_free(&pci_domain_nr_static_ida, bus->domain_nr); in of_pci_bus_release_domain_nr()
7011 ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr); in of_pci_bus_release_domain_nr()
7029 * pci_ext_cfg_avail - can we access extended PCI config space?