17 #define DDRC_PERF_CNT_OP_MODE_CTRL	0x8020
18 #define OP_MODE_CTRL_VAL_MANNUAL	0x1
21 #define DDRC_PERF_CNT_START_OP_CTRL	0x8028
22 #define START_OP_CTRL_VAL_START		0x1ULL
23 #define START_OP_CTRL_VAL_ACTIVE	0x2
26 #define DDRC_PERF_CNT_END_OP_CTRL	0x8030
27 #define END_OP_CTRL_VAL_END		0x1ULL
30 #define DDRC_PERF_CNT_END_STATUS		0x8038
31 #define END_STATUS_VAL_END_TIMER_MODE_END	0x1
34 #define DDRC_PERF_CFG_BASE		0x8040
105 #define DDRC_PERF_CNT_VALUE_BASE		0x8080
109 #define DDRC_PERF_CNT_FREERUN_EN	0x80C0
110 #define DDRC_PERF_FREERUN_WRITE_EN	0x1
111 #define DDRC_PERF_FREERUN_READ_EN	0x2
114 #define DDRC_PERF_CNT_FREERUN_CTRL	0x80C8
115 #define DDRC_FREERUN_WRITE_CNT_CLR	0x1
116 #define DDRC_FREERUN_READ_CNT_CLR	0x2
119 #define DDRC_PERF_CNT_VALUE_WR_OP	0x80D0
120 #define DDRC_PERF_CNT_VALUE_RD_OP	0x80D8
122 #define DDRC_PERF_CNT_MAX_VALUE		GENMASK_ULL(48, 0)
144 	return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);  in cn10k_ddr_pmu_event_show()
217 PMU_FORMAT_ATTR(event, "config:0-8");
279 		*event_bitmap = (0xFULL << (eventid - 1));  in ddr_perf_get_event_bitmap()
286 	return 0;  in ddr_perf_get_event_bitmap()
308 	for (i = 0; i < DDRC_PERF_NUM_GEN_COUNTERS; i++) {  in cn10k_ddr_perf_alloc_counter()
336 	if (event->cpu < 0) {  in cn10k_ddr_perf_event_init()
351 	return 0;  in cn10k_ddr_perf_event_init()
428 	local64_set(&hwc->prev_count, 0);  in cn10k_ddr_perf_event_start()
432 	hwc->state = 0;  in cn10k_ddr_perf_event_start()
445 	if (counter < 0)  in cn10k_ddr_perf_event_add()
478 	return 0;  in cn10k_ddr_perf_event_add()
508 	if (pmu->active_events == 0)  in cn10k_ddr_perf_event_del()
533 	for (i = 0; i < DDRC_PERF_NUM_GEN_COUNTERS; i++) {  in cn10k_ddr_perf_event_update_all()
541 	for (i = 0; i < DDRC_PERF_NUM_GEN_COUNTERS; i++) {  in cn10k_ddr_perf_event_update_all()
546 		local64_set(&hwc->prev_count, 0);  in cn10k_ddr_perf_event_update_all()
584 	for (i = 0; i < DDRC_PERF_NUM_GEN_COUNTERS; i++) {  in cn10k_ddr_pmu_overflow_handler()
621 		return 0;  in cn10k_ddr_pmu_offline_cpu()
625 		return 0;  in cn10k_ddr_pmu_offline_cpu()
629 	return 0;  in cn10k_ddr_pmu_offline_cpu()
647 	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in cn10k_ddr_perf_probe()
692 	return 0;  in cn10k_ddr_perf_probe()
709 	return 0;  in cn10k_ddr_perf_remove()
722 	{"MRVL000A", 0},