Lines Matching +full:ena +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
24 #include <linux/pinctrl/pinconf-generic.h>
29 #include "pinctrl-intel.h"
179 * Lynxpoint gpios are controlled through both bitmapped registers and
181 * 3 x 32bit registers to cover all 95 GPIOs
184 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
189 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
190 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
191 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
206 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
220 offset -= comm->pin_base; in lp_gpio_reg()
229 return comm->regs + reg_offset + reg; in lp_gpio_reg()
236 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); in lp_gpio_acpi_use()
251 return !!(value & BIT(offset - 8 + 0)); in lp_gpio_ioxapic_use()
253 return !!(value & BIT(offset - 13 + 3)); in lp_gpio_ioxapic_use()
255 return !!(value & BIT(offset - 45 + 5)); in lp_gpio_ioxapic_use()
264 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_pin_dbg_show()
265 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_dbg_show()
293 const struct intel_pingroup *grp = &lg->soc->groups[group]; in lp_pinmux_set_mux()
297 raw_spin_lock_irqsave(&lg->lock, flags); in lp_pinmux_set_mux()
300 for (i = 0; i < grp->grp.npins; i++) { in lp_pinmux_set_mux()
301 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1); in lp_pinmux_set_mux()
307 if (grp->modes) in lp_pinmux_set_mux()
308 value |= grp->modes[i]; in lp_pinmux_set_mux()
310 value |= grp->mode; in lp_pinmux_set_mux()
315 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_pinmux_set_mux()
335 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_gpio_request_enable()
336 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_gpio_request_enable()
340 pm_runtime_get(lg->dev); in lp_gpio_request_enable()
342 raw_spin_lock_irqsave(&lg->lock, flags); in lp_gpio_request_enable()
351 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); in lp_gpio_request_enable()
357 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_gpio_request_enable()
367 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_gpio_disable_free()
370 raw_spin_lock_irqsave(&lg->lock, flags); in lp_gpio_disable_free()
375 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_gpio_disable_free()
377 pm_runtime_put(lg->dev); in lp_gpio_disable_free()
385 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_gpio_set_direction()
389 raw_spin_lock_irqsave(&lg->lock, flags); in lp_gpio_set_direction()
402 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), in lp_gpio_set_direction()
407 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_gpio_set_direction()
426 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_config_get()
432 raw_spin_lock_irqsave(&lg->lock, flags); in lp_pin_config_get()
434 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_pin_config_get()
441 return -EINVAL; in lp_pin_config_get()
446 return -EINVAL; in lp_pin_config_get()
452 return -EINVAL; in lp_pin_config_get()
457 return -ENOTSUPP; in lp_pin_config_get()
469 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_config_set()
475 raw_spin_lock_irqsave(&lg->lock, flags); in lp_pin_config_set()
496 ret = -ENOTSUPP; in lp_pin_config_set()
506 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_pin_config_set()
536 raw_spin_lock_irqsave(&lg->lock, flags); in lp_gpio_set()
543 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_gpio_set()
548 return pinctrl_gpio_direction_input(chip->base + offset); in lp_gpio_direction_input()
556 return pinctrl_gpio_direction_output(chip->base + offset); in lp_gpio_direction_output()
575 void __iomem *reg, *ena; in lp_gpio_irq_handler() local
580 for (base = 0; base < lg->chip.ngpio; base += 32) { in lp_gpio_irq_handler()
581 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); in lp_gpio_irq_handler()
582 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); in lp_gpio_irq_handler()
585 pending = ioread32(reg) & ioread32(ena); in lp_gpio_irq_handler()
588 generic_handle_domain_irq(lg->chip.irq.domain, base + pin); in lp_gpio_irq_handler()
590 chip->irq_eoi(data); in lp_gpio_irq_handler()
598 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); in lp_irq_ack()
601 raw_spin_lock_irqsave(&lg->lock, flags); in lp_irq_ack()
603 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_irq_ack()
619 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); in lp_irq_enable()
624 raw_spin_lock_irqsave(&lg->lock, flags); in lp_irq_enable()
626 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_irq_enable()
634 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); in lp_irq_disable()
637 raw_spin_lock_irqsave(&lg->lock, flags); in lp_irq_disable()
639 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_irq_disable()
653 reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); in lp_irq_set_type()
655 return -EINVAL; in lp_irq_set_type()
659 dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq); in lp_irq_set_type()
660 return -EBUSY; in lp_irq_set_type()
663 raw_spin_lock_irqsave(&lg->lock, flags); in lp_irq_set_type()
689 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_irq_set_type()
695 .name = "LP-GPIO",
712 for (base = 0; base < lg->chip.ngpio; base += 32) { in lp_gpio_irq_init_hw()
714 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); in lp_gpio_irq_init_hw()
717 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); in lp_gpio_irq_init_hw()
727 struct device *dev = lg->dev; in lp_gpio_add_pin_ranges()
730 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); in lp_gpio_add_pin_ranges()
742 struct device *dev = &pdev->dev; in lp_gpio_probe()
750 return -ENODEV; in lp_gpio_probe()
754 return -ENOMEM; in lp_gpio_probe()
756 lg->dev = dev; in lp_gpio_probe()
757 lg->soc = soc; in lp_gpio_probe()
759 lg->ncommunities = lg->soc->ncommunities; in lp_gpio_probe()
760 lg->communities = devm_kcalloc(dev, lg->ncommunities, in lp_gpio_probe()
761 sizeof(*lg->communities), GFP_KERNEL); in lp_gpio_probe()
762 if (!lg->communities) in lp_gpio_probe()
763 return -ENOMEM; in lp_gpio_probe()
765 lg->pctldesc = lptlp_pinctrl_desc; in lp_gpio_probe()
766 lg->pctldesc.name = dev_name(dev); in lp_gpio_probe()
767 lg->pctldesc.pins = lg->soc->pins; in lp_gpio_probe()
768 lg->pctldesc.npins = lg->soc->npins; in lp_gpio_probe()
770 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); in lp_gpio_probe()
771 if (IS_ERR(lg->pctldev)) { in lp_gpio_probe()
773 return PTR_ERR(lg->pctldev); in lp_gpio_probe()
781 return -EINVAL; in lp_gpio_probe()
784 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); in lp_gpio_probe()
787 return -EBUSY; in lp_gpio_probe()
790 for (i = 0; i < lg->soc->ncommunities; i++) { in lp_gpio_probe()
791 struct intel_community *comm = &lg->communities[i]; in lp_gpio_probe()
793 *comm = lg->soc->communities[i]; in lp_gpio_probe()
795 comm->regs = regs; in lp_gpio_probe()
796 comm->pad_regs = regs + 0x100; in lp_gpio_probe()
799 raw_spin_lock_init(&lg->lock); in lp_gpio_probe()
801 gc = &lg->chip; in lp_gpio_probe()
802 gc->label = dev_name(dev); in lp_gpio_probe()
803 gc->owner = THIS_MODULE; in lp_gpio_probe()
804 gc->request = gpiochip_generic_request; in lp_gpio_probe()
805 gc->free = gpiochip_generic_free; in lp_gpio_probe()
806 gc->direction_input = lp_gpio_direction_input; in lp_gpio_probe()
807 gc->direction_output = lp_gpio_direction_output; in lp_gpio_probe()
808 gc->get = lp_gpio_get; in lp_gpio_probe()
809 gc->set = lp_gpio_set; in lp_gpio_probe()
810 gc->set_config = gpiochip_generic_config; in lp_gpio_probe()
811 gc->get_direction = lp_gpio_get_direction; in lp_gpio_probe()
812 gc->base = -1; in lp_gpio_probe()
813 gc->ngpio = LP_NUM_GPIO; in lp_gpio_probe()
814 gc->can_sleep = false; in lp_gpio_probe()
815 gc->add_pin_ranges = lp_gpio_add_pin_ranges; in lp_gpio_probe()
816 gc->parent = dev; in lp_gpio_probe()
823 girq = &gc->irq; in lp_gpio_probe()
825 girq->init_hw = lp_gpio_irq_init_hw; in lp_gpio_probe()
826 girq->parent_handler = lp_gpio_irq_handler; in lp_gpio_probe()
827 girq->num_parents = 1; in lp_gpio_probe()
828 girq->parents = devm_kcalloc(dev, girq->num_parents, in lp_gpio_probe()
829 sizeof(*girq->parents), in lp_gpio_probe()
831 if (!girq->parents) in lp_gpio_probe()
832 return -ENOMEM; in lp_gpio_probe()
833 girq->parents[0] = irq; in lp_gpio_probe()
834 girq->default_type = IRQ_TYPE_NONE; in lp_gpio_probe()
835 girq->handler = handle_bad_irq; in lp_gpio_probe()
840 dev_err(dev, "failed adding lp-gpio chip\n"); in lp_gpio_probe()
851 pm_runtime_disable(&pdev->dev); in lp_gpio_remove()
868 struct gpio_chip *chip = &lg->chip; in lp_gpio_resume()
872 /* on some hardware suspend clears input sensing, re-enable it here */ in lp_gpio_resume()