1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
15 #include <linux/pinctrl/pinconf-generic.h>
19 #include "../pinctrl-utils.h"
21 #include "pinctrl-lpass-lpi.h"
29 	struct pinctrl_dev *ctrl;  member
41 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,  in lpi_gpio_read()  argument
44 	return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);  in lpi_gpio_read()
47 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,  in lpi_gpio_write()  argument
50 	iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);  in lpi_gpio_write()
67 	return pctrl->data->nfunctions;  in lpi_gpio_get_functions_count()
75 	return pctrl->data->functions[function].name;  in lpi_gpio_get_function_name()
85 	*groups = pctrl->data->functions[function].groups;  in lpi_gpio_get_function_groups()
86 	*num_qgroups = pctrl->data->functions[function].ngroups;  in lpi_gpio_get_function_groups()
95 	const struct lpi_pingroup *g = &pctrl->data->groups[group];  in lpi_gpio_set_mux()
97 	int i, pin = g->pin;  in lpi_gpio_set_mux()  local
99 	for (i = 0; i < g->nfuncs; i++) {  in lpi_gpio_set_mux()
100 		if (g->funcs[i] == function)  in lpi_gpio_set_mux()
104 	if (WARN_ON(i == g->nfuncs))  in lpi_gpio_set_mux()
105 		return -EINVAL;  in lpi_gpio_set_mux()
107 	mutex_lock(&pctrl->lock);  in lpi_gpio_set_mux()
108 	val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);  in lpi_gpio_set_mux()
112 	 * output, make sure that we're not going to be glitching the pin  in lpi_gpio_set_mux()
113 	 * by reading the current state of the pin and setting it as the  in lpi_gpio_set_mux()
117 	    !test_and_set_bit(group, pctrl->ever_gpio)) {  in lpi_gpio_set_mux()
132 	lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);  in lpi_gpio_set_mux()
133 	mutex_unlock(&pctrl->lock);  in lpi_gpio_set_mux()
146 			  unsigned int pin, unsigned long *config)  in lpi_config_get()  argument
149 	struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);  in lpi_config_get()
155 	ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);  in lpi_config_get()
182 		return -EINVAL;  in lpi_config_get()
192 	struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);  in lpi_config_set()
200 	g = &pctrl->data->groups[group];  in lpi_config_set()
230 				dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",  in lpi_config_set()
232 				return -EINVAL;  in lpi_config_set()
235 			slew_offset = g->slew_offset;  in lpi_config_set()
239 			mutex_lock(&pctrl->lock);  in lpi_config_set()
241 			sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);  in lpi_config_set()
244 			iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);  in lpi_config_set()
246 			mutex_unlock(&pctrl->lock);  in lpi_config_set()
249 			return -EINVAL;  in lpi_config_set()
254 	 * As per Hardware Programming Guide, when configuring pin as output,  in lpi_config_set()
255 	 * set the pin value before setting output-enable (OE).  in lpi_config_set()
262 	mutex_lock(&pctrl->lock);  in lpi_config_set()
271 	mutex_unlock(&pctrl->lock);  in lpi_config_set()
282 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)  in lpi_gpio_direction_input()  argument
289 	return lpi_config_set(state->ctrl, pin, &config, 1);  in lpi_gpio_direction_input()
293 				     unsigned int pin, int val)  in lpi_gpio_direction_output()  argument
300 	return lpi_config_set(state->ctrl, pin, &config, 1);  in lpi_gpio_direction_output()
303 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)  in lpi_gpio_get()  argument
307 	return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &  in lpi_gpio_get()
311 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)  in lpi_gpio_set()  argument
318 	lpi_config_set(state->ctrl, pin, &config, 1);  in lpi_gpio_set()
350 	pctldev = pctldev ? : state->ctrl;  in lpi_gpio_dbg_show_one()
351 	pindesc = pctldev->desc->pins[offset];  in lpi_gpio_dbg_show_one()
359 	seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);  in lpi_gpio_dbg_show_one()
366 	unsigned int gpio = chip->base;  in lpi_gpio_dbg_show()
369 	for (i = 0; i < chip->ngpio; i++, gpio++) {  in lpi_gpio_dbg_show()
393 	for (i = 0; i < pctrl->data->npins; i++) {  in lpi_build_pin_desc_groups()
394 		const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;  in lpi_build_pin_desc_groups()
396 		ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,  in lpi_build_pin_desc_groups()
397 						  (int *)&pin_info->number, 1, NULL);  in lpi_build_pin_desc_groups()
405 	for (; i > 0; i--)  in lpi_build_pin_desc_groups()
406 		pinctrl_generic_remove_group(pctrl->ctrl, i - 1);  in lpi_build_pin_desc_groups()
414 	struct device *dev = &pdev->dev;  in lpi_pinctrl_probe()
420 		return -ENOMEM;  in lpi_pinctrl_probe()
426 		return -EINVAL;  in lpi_pinctrl_probe()
428 	if (WARN_ON(data->npins > MAX_NR_GPIO))  in lpi_pinctrl_probe()
429 		return -EINVAL;  in lpi_pinctrl_probe()
431 	pctrl->data = data;  in lpi_pinctrl_probe()
432 	pctrl->dev = &pdev->dev;  in lpi_pinctrl_probe()
434 	pctrl->clks[0].id = "core";  in lpi_pinctrl_probe()
435 	pctrl->clks[1].id = "audio";  in lpi_pinctrl_probe()
437 	pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);  in lpi_pinctrl_probe()
438 	if (IS_ERR(pctrl->tlmm_base))  in lpi_pinctrl_probe()
439 		return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),  in lpi_pinctrl_probe()
442 	pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);  in lpi_pinctrl_probe()
443 	if (IS_ERR(pctrl->slew_base))  in lpi_pinctrl_probe()
444 		return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),  in lpi_pinctrl_probe()
447 	ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);  in lpi_pinctrl_probe()
451 	ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);  in lpi_pinctrl_probe()
453 		return dev_err_probe(dev, ret, "Can't enable clocks\n");  in lpi_pinctrl_probe()
455 	pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;  in lpi_pinctrl_probe()
456 	pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;  in lpi_pinctrl_probe()
457 	pctrl->desc.confops = &lpi_gpio_pinconf_ops;  in lpi_pinctrl_probe()
458 	pctrl->desc.owner = THIS_MODULE;  in lpi_pinctrl_probe()
459 	pctrl->desc.name = dev_name(dev);  in lpi_pinctrl_probe()
460 	pctrl->desc.pins = data->pins;  in lpi_pinctrl_probe()
461 	pctrl->desc.npins = data->npins;  in lpi_pinctrl_probe()
462 	pctrl->chip = lpi_gpio_template;  in lpi_pinctrl_probe()
463 	pctrl->chip.parent = dev;  in lpi_pinctrl_probe()
464 	pctrl->chip.base = -1;  in lpi_pinctrl_probe()
465 	pctrl->chip.ngpio = data->npins;  in lpi_pinctrl_probe()
466 	pctrl->chip.label = dev_name(dev);  in lpi_pinctrl_probe()
467 	pctrl->chip.can_sleep = false;  in lpi_pinctrl_probe()
469 	mutex_init(&pctrl->lock);  in lpi_pinctrl_probe()
471 	pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);  in lpi_pinctrl_probe()
472 	if (IS_ERR(pctrl->ctrl)) {  in lpi_pinctrl_probe()
473 		ret = PTR_ERR(pctrl->ctrl);  in lpi_pinctrl_probe()
474 		dev_err(dev, "failed to add pin controller\n");  in lpi_pinctrl_probe()
482 	ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);  in lpi_pinctrl_probe()
484 		dev_err(pctrl->dev, "can't add gpio chip\n");  in lpi_pinctrl_probe()
491 	mutex_destroy(&pctrl->lock);  in lpi_pinctrl_probe()
492 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);  in lpi_pinctrl_probe()
503 	mutex_destroy(&pctrl->lock);  in lpi_pinctrl_remove()
504 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);  in lpi_pinctrl_remove()
506 	for (i = 0; i < pctrl->data->npins; i++)  in lpi_pinctrl_remove()
507 		pinctrl_generic_remove_group(pctrl->ctrl, i);  in lpi_pinctrl_remove()
513 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");