Lines Matching full:g
85 const struct msm_pingroup *g) \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
90 const struct msm_pingroup *g) \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
102 const struct msm_pingroup *g) in MSM_ACCESSOR()
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
106 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
189 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
194 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
195 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
197 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
198 if (g->funcs[i] == function) in msm_pinmux_set_mux()
202 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
221 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
229 if (i == gpio_func && (val & BIT(g->oe_bit)) && in msm_pinmux_set_mux()
231 u32 io_val = msm_readl_io(pctrl, g); in msm_pinmux_set_mux()
233 if (io_val & BIT(g->in_bit)) { in msm_pinmux_set_mux()
234 if (!(io_val & BIT(g->out_bit))) in msm_pinmux_set_mux()
235 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
237 if (io_val & BIT(g->out_bit)) in msm_pinmux_set_mux()
238 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
243 if (val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
244 val &= ~BIT(g->egpio_enable); in msm_pinmux_set_mux()
247 val |= i << g->mux_bit; in msm_pinmux_set_mux()
249 if (egpio_func && val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
250 val |= BIT(g->egpio_enable); in msm_pinmux_set_mux()
253 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
266 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
279 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio() local
282 if (!g->nfuncs) in msm_pinmux_request_gpio()
285 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
298 const struct msm_pingroup *g, in msm_config_reg() argument
308 *bit = g->pull_bit; in msm_config_reg()
310 if (g->i2c_pull_bit) in msm_config_reg()
311 *mask |= BIT(g->i2c_pull_bit) >> *bit; in msm_config_reg()
314 *bit = g->od_bit; in msm_config_reg()
318 *bit = g->drv_bit; in msm_config_reg()
324 *bit = g->oe_bit; in msm_config_reg()
350 const struct msm_pingroup *g; in msm_config_group_get() local
359 g = &pctrl->soc->groups[group]; in msm_config_group_get()
361 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
365 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
391 else if (arg & BIT(g->i2c_pull_bit)) in msm_config_group_get()
412 val = msm_readl_io(pctrl, g); in msm_config_group_get()
413 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
433 const struct msm_pingroup *g; in msm_config_group_set() local
444 g = &pctrl->soc->groups[group]; in msm_config_group_set()
450 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
471 else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) in msm_config_group_set()
472 arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; in msm_config_group_set()
489 val = msm_readl_io(pctrl, g); in msm_config_group_set()
491 val |= BIT(g->out_bit); in msm_config_group_set()
493 val &= ~BIT(g->out_bit); in msm_config_group_set()
494 msm_writel_io(val, pctrl, g); in msm_config_group_set()
544 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
547 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
562 const struct msm_pingroup *g; in msm_gpio_direction_input() local
567 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
571 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
572 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
573 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
582 const struct msm_pingroup *g; in msm_gpio_direction_output() local
587 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
591 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
593 val |= BIT(g->out_bit); in msm_gpio_direction_output()
595 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
596 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
598 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
599 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
600 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
610 const struct msm_pingroup *g; in msm_gpio_get_direction() local
613 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
615 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
617 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
623 const struct msm_pingroup *g; in msm_gpio_get() local
627 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
629 val = msm_readl_io(pctrl, g); in msm_gpio_get()
630 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
635 const struct msm_pingroup *g; in msm_gpio_set() local
640 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
644 val = msm_readl_io(pctrl, g); in msm_gpio_set()
646 val |= BIT(g->out_bit); in msm_gpio_set()
648 val &= ~BIT(g->out_bit); in msm_gpio_set()
649 msm_writel_io(val, pctrl, g); in msm_gpio_set()
662 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
688 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
689 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
690 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
692 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
693 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
694 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
695 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
697 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
698 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
701 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
703 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
706 seq_printf(s, " %-8s: egpio\n", g->grp.name); in msm_gpio_dbg_show_one()
710 seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
815 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
823 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
825 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
826 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
827 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
829 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
830 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
842 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
852 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
856 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
878 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
880 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
881 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
892 const struct msm_pingroup *g; in msm_gpio_irq_unmask() local
902 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
906 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
907 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
908 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
909 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
957 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent() local
963 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
976 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
994 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
1003 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
1007 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
1010 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
1039 const struct msm_pingroup *g; in msm_gpio_irq_init_valid_mask() local
1045 g = &pctrl->soc->groups[i]; in msm_gpio_irq_init_valid_mask()
1047 if (g->intr_detection_width != 1 && in msm_gpio_irq_init_valid_mask()
1048 g->intr_detection_width != 2) in msm_gpio_irq_init_valid_mask()
1057 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
1078 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1085 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
1094 if (g->intr_target_width) in msm_gpio_irq_set_type()
1095 intr_target_mask = GENMASK(g->intr_target_width - 1, 0); in msm_gpio_irq_set_type()
1098 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1102 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1103 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1111 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1112 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1113 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1114 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1122 val = oldval = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1123 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1124 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1125 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1126 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1129 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1130 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1133 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1134 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1137 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1138 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1143 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1146 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1147 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1148 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1151 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1152 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1155 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1158 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1159 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1164 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1170 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1180 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1183 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1281 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
1295 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1296 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1297 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()