Lines Matching +full:gpio +full:- +full:out +full:- +full:pol
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/gpio/driver.h>
24 #include <linux/pinctrl/pinconf-generic.h>
32 #include "../pinctrl-utils.h"
34 #include "pinctrl-msm.h"
41 * struct msm_pinctrl - state for a pinctrl-msm device
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
113 return pctrl->soc->ngroups; in msm_get_groups_count()
121 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
131 *pins = pctrl->soc->groups[group].grp.pins; in msm_get_group_pins()
132 *num_pins = pctrl->soc->groups[group].grp.npins; in msm_get_group_pins()
147 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
149 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; in msm_pinmux_request()
156 return pctrl->soc->nfunctions; in msm_get_functions_count()
164 return pctrl->soc->functions[function].name; in msm_get_function_name()
174 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
175 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
184 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
185 unsigned int irq = irq_find_mapping(gc->irq.domain, group); in msm_pinmux_set_mux()
187 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
188 unsigned int egpio_func = pctrl->soc->egpio_func; in msm_pinmux_set_mux()
194 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
195 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
197 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
198 if (g->funcs[i] == function) in msm_pinmux_set_mux()
202 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
203 return -EINVAL; in msm_pinmux_set_mux()
206 * If an GPIO interrupt is setup on this pin then we need special in msm_pinmux_set_mux()
216 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
219 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
224 * If this is the first time muxing to GPIO and the direction is in msm_pinmux_set_mux()
229 if (i == gpio_func && (val & BIT(g->oe_bit)) && in msm_pinmux_set_mux()
230 !test_and_set_bit(group, pctrl->ever_gpio)) { in msm_pinmux_set_mux()
233 if (io_val & BIT(g->in_bit)) { in msm_pinmux_set_mux()
234 if (!(io_val & BIT(g->out_bit))) in msm_pinmux_set_mux()
235 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
237 if (io_val & BIT(g->out_bit)) in msm_pinmux_set_mux()
238 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
243 if (val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
244 val &= ~BIT(g->egpio_enable); in msm_pinmux_set_mux()
247 val |= i << g->mux_bit; in msm_pinmux_set_mux()
249 if (egpio_func && val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
250 val |= BIT(g->egpio_enable); in msm_pinmux_set_mux()
255 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
258 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
260 * Clear interrupts detected while not GPIO since we only in msm_pinmux_set_mux()
263 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
279 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
282 if (!g->nfuncs) in msm_pinmux_request_gpio()
285 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
308 *bit = g->pull_bit; in msm_config_reg()
310 if (g->i2c_pull_bit) in msm_config_reg()
311 *mask |= BIT(g->i2c_pull_bit) >> *bit; in msm_config_reg()
314 *bit = g->od_bit; in msm_config_reg()
318 *bit = g->drv_bit; in msm_config_reg()
324 *bit = g->oe_bit; in msm_config_reg()
328 return -ENOTSUPP; in msm_config_reg()
359 g = &pctrl->soc->groups[group]; in msm_config_group_get()
372 return -EINVAL; in msm_config_group_get()
377 return -EINVAL; in msm_config_group_get()
381 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
382 return -ENOTSUPP; in msm_config_group_get()
385 return -EINVAL; in msm_config_group_get()
389 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
391 else if (arg & BIT(g->i2c_pull_bit)) in msm_config_group_get()
396 return -EINVAL; in msm_config_group_get()
399 /* Pin is not open-drain */ in msm_config_group_get()
401 return -EINVAL; in msm_config_group_get()
410 return -EINVAL; in msm_config_group_get()
413 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
417 return -EINVAL; in msm_config_group_get()
420 return -ENOTSUPP; in msm_config_group_get()
444 g = &pctrl->soc->groups[group]; in msm_config_group_set()
463 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
464 return -ENOTSUPP; in msm_config_group_set()
469 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
471 else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) in msm_config_group_set()
472 arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; in msm_config_group_set()
482 arg = -1; in msm_config_group_set()
484 arg = (arg / 2) - 1; in msm_config_group_set()
488 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
491 val |= BIT(g->out_bit); in msm_config_group_set()
493 val &= ~BIT(g->out_bit); in msm_config_group_set()
495 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
503 * actually be a no-op. in msm_config_group_set()
515 * no-op. However, for historical reasons and to in msm_config_group_set()
521 * that "input-enable" and "input-disable" in a device in msm_config_group_set()
532 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
534 return -EINVAL; in msm_config_group_set()
537 /* Range-check user-supplied value */ in msm_config_group_set()
539 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
540 return -EINVAL; in msm_config_group_set()
543 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
548 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
567 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
569 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
572 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
575 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
587 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
589 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
593 val |= BIT(g->out_bit); in msm_gpio_direction_output()
595 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
599 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
602 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
613 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
617 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
627 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
630 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
640 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
642 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
646 val |= BIT(g->out_bit); in msm_gpio_set()
648 val &= ~BIT(g->out_bit); in msm_gpio_set()
651 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
660 unsigned gpio) in msm_gpio_dbg_show_one() argument
688 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
692 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
693 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
694 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
695 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
697 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
698 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
701 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
703 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
706 seq_printf(s, " %-8s: egpio\n", g->grp.name); in msm_gpio_dbg_show_one()
710 seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
711 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); in msm_gpio_dbg_show_one()
713 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
722 unsigned gpio = chip->base; in msm_gpio_dbg_show() local
725 for (i = 0; i < chip->ngpio; i++, gpio++) in msm_gpio_dbg_show()
726 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); in msm_gpio_dbg_show()
740 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
743 /* Remove driver-provided reserved GPIOs from valid_mask */ in msm_gpio_init_valid_mask()
747 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
748 return -EINVAL; in msm_gpio_init_valid_mask()
757 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
762 return -EINVAL; in msm_gpio_init_valid_mask()
766 return -ENOMEM; in msm_gpio_init_valid_mask()
768 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
770 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
771 goto out; in msm_gpio_init_valid_mask()
778 out: in msm_gpio_init_valid_mask()
794 /* For dual-edge interrupts in software, since some hardware has no
798 * settings of both-edge irq lines to try and catch the next edge.
801 * - the status bit goes high, indicating that an edge was caught, or
802 * - the input value of the gpio doesn't change during the attempt.
807 * The do-loop tries to sledge-hammer closed the timing hole between
808 * the initial value-read and the polarity-write - if the line value changes
820 unsigned pol; in msm_gpio_update_dual_edge_pos() local
823 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
825 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
826 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
827 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
829 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
833 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_pos()
834 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
846 if (d->parent_data) in msm_gpio_irq_mask()
849 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
852 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
854 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
862 * for level type irq). The 'non-raw' status enable bit causes the in msm_gpio_irq_mask()
871 * enabled all the time causes level interrupts to re-latch into the in msm_gpio_irq_mask()
878 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
880 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
883 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
885 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
896 if (d->parent_data) in msm_gpio_irq_unmask()
899 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
902 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
904 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
907 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
908 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
911 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
913 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
921 gpiochip_enable_irq(gc, d->hwirq); in msm_gpio_irq_enable()
923 if (d->parent_data) in msm_gpio_irq_enable()
926 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
935 if (d->parent_data) in msm_gpio_irq_disable()
938 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
941 gpiochip_disable_irq(gc, d->hwirq); in msm_gpio_irq_disable()
945 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
957 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
963 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
976 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
986 } while (loop_limit-- > 0); in msm_gpio_update_dual_edge_parent()
987 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
997 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
998 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1003 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
1005 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
1009 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
1012 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
1017 d = d->parent_data; in msm_gpio_irq_eoi()
1020 d->chip->irq_eoi(d); in msm_gpio_irq_eoi()
1030 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
1031 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
1045 g = &pctrl->soc->groups[i]; in msm_gpio_irq_init_valid_mask()
1047 if (g->intr_detection_width != 1 && in msm_gpio_irq_init_valid_mask()
1048 g->intr_detection_width != 2) in msm_gpio_irq_init_valid_mask()
1063 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1069 if (d->parent_data) in msm_gpio_irq_set_type()
1072 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
1073 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1078 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1080 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1085 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
1086 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1088 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
1094 if (g->intr_target_width) in msm_gpio_irq_set_type()
1095 intr_target_mask = GENMASK(g->intr_target_width - 1, 0); in msm_gpio_irq_set_type()
1097 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
1098 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1102 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1103 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1107 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1109 d->hwirq); in msm_gpio_irq_set_type()
1112 val &= ~(intr_target_mask << g->intr_target_bit); in msm_gpio_irq_set_type()
1113 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1117 /* Update configuration for gpio. in msm_gpio_irq_set_type()
1118 * RAW_STATUS_EN is left on for all gpio irqs. Due to the in msm_gpio_irq_set_type()
1123 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1124 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1125 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1126 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1129 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1130 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1133 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1134 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1137 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1138 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1143 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1146 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1147 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1148 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1151 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1152 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1155 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1158 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1159 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1164 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1176 * also still have a non-matching interrupt latched, so clear whenever in msm_gpio_irq_set_type()
1182 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1185 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1203 * when TLMM is powered on. To allow that, enable the GPIO in msm_gpio_irq_set_wake()
1206 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1209 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1218 if (!try_module_get(gc->owner)) in msm_gpio_irq_reqres()
1219 return -ENODEV; in msm_gpio_irq_reqres()
1221 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1223 goto out; in msm_gpio_irq_reqres()
1224 msm_gpio_direction_input(gc, d->hwirq); in msm_gpio_irq_reqres()
1226 if (gpiochip_lock_as_irq(gc, d->hwirq)) { in msm_gpio_irq_reqres()
1227 dev_err(gc->parent, in msm_gpio_irq_reqres()
1229 d->hwirq); in msm_gpio_irq_reqres()
1230 ret = -EINVAL; in msm_gpio_irq_reqres()
1231 goto out; in msm_gpio_irq_reqres()
1235 * The disable / clear-enable workaround we do in msm_pinmux_set_mux() in msm_gpio_irq_reqres()
1239 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); in msm_gpio_irq_reqres()
1242 out: in msm_gpio_irq_reqres()
1243 module_put(gc->owner); in msm_gpio_irq_reqres()
1251 gpiochip_unlock_as_irq(gc, d->hwirq); in msm_gpio_irq_relres()
1252 module_put(gc->owner); in msm_gpio_irq_relres()
1261 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1264 return -EINVAL; in msm_gpio_irq_set_affinity()
1272 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1275 return -EINVAL; in msm_gpio_irq_set_vcpu_affinity()
1294 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1295 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1297 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()
1298 generic_handle_domain_irq(gc->irq.domain, i); in msm_gpio_irq_handler()
1323 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1324 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1325 if (map->gpio == child) { in msm_gpio_wakeirq()
1326 *parent = map->wakeirq; in msm_gpio_wakeirq()
1336 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1339 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1367 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init() local
1372 return -EINVAL; in msm_gpio_init()
1374 chip = &pctrl->chip; in msm_gpio_init()
1375 chip->base = -1; in msm_gpio_init()
1376 chip->ngpio = ngpio; in msm_gpio_init()
1377 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1378 chip->parent = pctrl->dev; in msm_gpio_init()
1379 chip->owner = THIS_MODULE; in msm_gpio_init()
1381 chip->init_valid_mask = msm_gpio_init_valid_mask; in msm_gpio_init()
1383 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1385 chip->irq.parent_domain = irq_find_matching_host(np, in msm_gpio_init()
1388 if (!chip->irq.parent_domain) in msm_gpio_init()
1389 return -EPROBE_DEFER; in msm_gpio_init()
1390 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; in msm_gpio_init()
1393 * is handling the direct connect IRQ of the GPIO. in msm_gpio_init()
1395 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); in msm_gpio_init()
1396 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1397 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1398 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1402 girq = &chip->irq; in msm_gpio_init()
1404 girq->parent_handler = msm_gpio_irq_handler; in msm_gpio_init()
1405 girq->fwnode = dev_fwnode(pctrl->dev); in msm_gpio_init()
1406 girq->num_parents = 1; in msm_gpio_init()
1407 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1409 if (!girq->parents) in msm_gpio_init()
1410 return -ENOMEM; in msm_gpio_init()
1411 girq->default_type = IRQ_TYPE_NONE; in msm_gpio_init()
1412 girq->handler = handle_bad_irq; in msm_gpio_init()
1413 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1414 girq->init_valid_mask = msm_gpio_irq_init_valid_mask; in msm_gpio_init()
1416 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1418 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1423 * For DeviceTree-supported systems, the gpio core checks the in msm_gpio_init()
1424 * pinctrl's device node for the "gpio-ranges" property. in msm_gpio_init()
1429 * files which don't set the "gpio-ranges" property or systems that in msm_gpio_init()
1432 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1433 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1434 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1436 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1437 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1447 struct msm_pinctrl *pctrl = data->cb_data; in msm_ps_hold_restart()
1449 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1468 const struct pinfunction *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1470 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1472 if (devm_register_sys_off_handler(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1477 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1489 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1496 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1512 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1514 return -ENOMEM; in msm_pinctrl_probe()
1516 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1517 pctrl->soc = soc_data; in msm_pinctrl_probe()
1518 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1519 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1520 pctrl->dev->of_node, in msm_pinctrl_probe()
1521 "qcom,ipq8064-pinctrl"); in msm_pinctrl_probe()
1523 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1525 if (soc_data->tiles) { in msm_pinctrl_probe()
1526 for (i = 0; i < soc_data->ntiles; i++) { in msm_pinctrl_probe()
1528 soc_data->tiles[i]); in msm_pinctrl_probe()
1529 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1530 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1531 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1534 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in msm_pinctrl_probe()
1535 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1536 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1538 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1543 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1544 if (pctrl->irq < 0) in msm_pinctrl_probe()
1545 return pctrl->irq; in msm_pinctrl_probe()
1547 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1548 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1549 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1550 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1551 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1552 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1553 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1555 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1556 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1557 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in msm_pinctrl_probe()
1558 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1567 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); in msm_pinctrl_probe()
1577 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()