Lines Matching +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <dt-bindings/power/px30-power.h>
22 #include <dt-bindings/power/rockchip,rv1126-power.h>
23 #include <dt-bindings/power/rk3036-power.h>
24 #include <dt-bindings/power/rk3066-power.h>
25 #include <dt-bindings/power/rk3128-power.h>
26 #include <dt-bindings/power/rk3188-power.h>
27 #include <dt-bindings/power/rk3228-power.h>
28 #include <dt-bindings/power/rk3288-power.h>
29 #include <dt-bindings/power/rk3328-power.h>
30 #include <dt-bindings/power/rk3366-power.h>
31 #include <dt-bindings/power/rk3368-power.h>
32 #include <dt-bindings/power/rk3399-power.h>
33 #include <dt-bindings/power/rk3568-power.h>
34 #include <dt-bindings/power/rk3588-power.h>
177 * Dynamic Memory Controller may need to coordinate with us -- see
180 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
211 mutex_lock(&pmu->mutex); in rockchip_pmu_block()
215 * enabled for the duration of power-domain transitions. Most in rockchip_pmu_block()
217 * particular, DRAM DVFS / memory-controller idle) must be handled by in rockchip_pmu_block()
223 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_block()
224 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
227 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pmu_block()
229 dev_err(pmu->dev, in rockchip_pmu_block()
231 genpd->name, ret); in rockchip_pmu_block()
240 for (i = i - 1; i >= 0; i--) { in rockchip_pmu_block()
241 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_block()
244 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_block()
247 mutex_unlock(&pmu->mutex); in rockchip_pmu_block()
264 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pmu_unblock()
265 genpd = pmu->genpd_data.domains[i]; in rockchip_pmu_unblock()
268 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pmu_unblock()
272 mutex_unlock(&pmu->mutex); in rockchip_pmu_unblock()
284 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_idle()
285 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_domain_is_idle()
288 regmap_read(pmu->regmap, pmu->info->idle_offset, &val); in rockchip_pmu_domain_is_idle()
289 return (val & pd_info->idle_mask) == pd_info->idle_mask; in rockchip_pmu_domain_is_idle()
296 regmap_read(pmu->regmap, pmu->info->ack_offset, &val); in rockchip_pmu_read_ack()
303 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_set_idle_request()
304 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_set_idle_request()
305 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_set_idle_request()
306 u32 pd_req_offset = pd_info->req_offset; in rockchip_pmu_set_idle_request()
312 if (pd_info->req_mask == 0) in rockchip_pmu_set_idle_request()
314 else if (pd_info->req_w_mask) in rockchip_pmu_set_idle_request()
315 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
316 idle ? (pd_info->req_mask | pd_info->req_w_mask) : in rockchip_pmu_set_idle_request()
317 pd_info->req_w_mask); in rockchip_pmu_set_idle_request()
319 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
320 pd_info->req_mask, idle ? -1U : 0); in rockchip_pmu_set_idle_request()
325 target_ack = idle ? pd_info->ack_mask : 0; in rockchip_pmu_set_idle_request()
327 (val & pd_info->ack_mask) == target_ack, in rockchip_pmu_set_idle_request()
330 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
332 genpd->name, val); in rockchip_pmu_set_idle_request()
339 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
341 genpd->name, is_idle); in rockchip_pmu_set_idle_request()
352 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_save_qos()
353 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
355 &pd->qos_save_regs[0][i]); in rockchip_pmu_save_qos()
356 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
358 &pd->qos_save_regs[1][i]); in rockchip_pmu_save_qos()
359 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
361 &pd->qos_save_regs[2][i]); in rockchip_pmu_save_qos()
362 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
364 &pd->qos_save_regs[3][i]); in rockchip_pmu_save_qos()
365 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
367 &pd->qos_save_regs[4][i]); in rockchip_pmu_save_qos()
376 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_restore_qos()
377 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
379 pd->qos_save_regs[0][i]); in rockchip_pmu_restore_qos()
380 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
382 pd->qos_save_regs[1][i]); in rockchip_pmu_restore_qos()
383 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
385 pd->qos_save_regs[2][i]); in rockchip_pmu_restore_qos()
386 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
388 pd->qos_save_regs[3][i]); in rockchip_pmu_restore_qos()
389 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
391 pd->qos_save_regs[4][i]); in rockchip_pmu_restore_qos()
399 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_on()
402 if (pd->info->repair_status_mask) { in rockchip_pmu_domain_is_on()
403 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val); in rockchip_pmu_domain_is_on()
405 return val & pd->info->repair_status_mask; in rockchip_pmu_domain_is_on()
408 /* check idle status for idle-only domains */ in rockchip_pmu_domain_is_on()
409 if (pd->info->status_mask == 0) in rockchip_pmu_domain_is_on()
412 regmap_read(pmu->regmap, pmu->info->status_offset, &val); in rockchip_pmu_domain_is_on()
415 return !(val & pd->info->status_mask); in rockchip_pmu_domain_is_on()
420 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_mem_on()
423 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_mem_on()
424 pmu->info->mem_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_mem_on()
427 return !(val & pd->info->mem_status_mask); in rockchip_pmu_domain_is_mem_on()
432 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_chain_on()
435 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_chain_on()
436 pmu->info->chain_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_chain_on()
439 return val & pd->info->mem_status_mask; in rockchip_pmu_domain_is_chain_on()
444 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_mem_reset()
445 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_domain_mem_reset()
452 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
454 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
460 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
461 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_pmu_domain_mem_reset()
467 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
469 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
473 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
474 pd->info->pwr_w_mask); in rockchip_pmu_domain_mem_reset()
480 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
482 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
492 struct rockchip_pmu *pmu = pd->pmu; in rockchip_do_pmu_set_power_domain()
493 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_do_pmu_set_power_domain()
494 u32 pd_pwr_offset = pd->info->pwr_offset; in rockchip_do_pmu_set_power_domain()
497 if (pd->info->pwr_mask == 0) in rockchip_do_pmu_set_power_domain()
500 if (on && pd->info->mem_status_mask) in rockchip_do_pmu_set_power_domain()
503 if (pd->info->pwr_w_mask) in rockchip_do_pmu_set_power_domain()
504 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
505 on ? pd->info->pwr_w_mask : in rockchip_do_pmu_set_power_domain()
506 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_do_pmu_set_power_domain()
508 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
509 pd->info->pwr_mask, on ? 0 : -1U); in rockchip_do_pmu_set_power_domain()
518 dev_err(pmu->dev, in rockchip_do_pmu_set_power_domain()
520 genpd->name, is_on); in rockchip_do_pmu_set_power_domain()
527 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pd_power()
530 mutex_lock(&pmu->mutex); in rockchip_pd_power()
533 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pd_power()
535 dev_err(pmu->dev, "failed to enable clocks\n"); in rockchip_pd_power()
536 mutex_unlock(&pmu->mutex); in rockchip_pd_power()
556 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pd_power()
559 mutex_unlock(&pmu->mutex); in rockchip_pd_power()
584 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); in rockchip_pd_attach_dev()
593 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { in rockchip_pd_attach_dev()
610 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); in rockchip_pd_detach_dev()
627 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
630 return -EINVAL; in rockchip_pm_add_one_domain()
633 if (id >= pmu->info->num_domains) { in rockchip_pm_add_one_domain()
634 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n", in rockchip_pm_add_one_domain()
636 return -EINVAL; in rockchip_pm_add_one_domain()
639 if (pmu->genpd_data.domains[id]) in rockchip_pm_add_one_domain()
642 pd_info = &pmu->info->domain_info[id]; in rockchip_pm_add_one_domain()
644 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n", in rockchip_pm_add_one_domain()
646 return -EINVAL; in rockchip_pm_add_one_domain()
649 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); in rockchip_pm_add_one_domain()
651 return -ENOMEM; in rockchip_pm_add_one_domain()
653 pd->info = pd_info; in rockchip_pm_add_one_domain()
654 pd->pmu = pmu; in rockchip_pm_add_one_domain()
656 pd->num_clks = of_clk_get_parent_count(node); in rockchip_pm_add_one_domain()
657 if (pd->num_clks > 0) { in rockchip_pm_add_one_domain()
658 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, in rockchip_pm_add_one_domain()
659 sizeof(*pd->clks), GFP_KERNEL); in rockchip_pm_add_one_domain()
660 if (!pd->clks) in rockchip_pm_add_one_domain()
661 return -ENOMEM; in rockchip_pm_add_one_domain()
663 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n", in rockchip_pm_add_one_domain()
664 node, pd->num_clks); in rockchip_pm_add_one_domain()
665 pd->num_clks = 0; in rockchip_pm_add_one_domain()
668 for (i = 0; i < pd->num_clks; i++) { in rockchip_pm_add_one_domain()
669 pd->clks[i].clk = of_clk_get(node, i); in rockchip_pm_add_one_domain()
670 if (IS_ERR(pd->clks[i].clk)) { in rockchip_pm_add_one_domain()
671 error = PTR_ERR(pd->clks[i].clk); in rockchip_pm_add_one_domain()
672 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
679 error = clk_bulk_prepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
683 pd->num_qos = of_count_phandle_with_args(node, "pm_qos", in rockchip_pm_add_one_domain()
686 if (pd->num_qos > 0) { in rockchip_pm_add_one_domain()
687 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos, in rockchip_pm_add_one_domain()
688 sizeof(*pd->qos_regmap), in rockchip_pm_add_one_domain()
690 if (!pd->qos_regmap) { in rockchip_pm_add_one_domain()
691 error = -ENOMEM; in rockchip_pm_add_one_domain()
696 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev, in rockchip_pm_add_one_domain()
697 pd->num_qos, in rockchip_pm_add_one_domain()
700 if (!pd->qos_save_regs[j]) { in rockchip_pm_add_one_domain()
701 error = -ENOMEM; in rockchip_pm_add_one_domain()
706 for (j = 0; j < pd->num_qos; j++) { in rockchip_pm_add_one_domain()
709 error = -ENODEV; in rockchip_pm_add_one_domain()
712 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node); in rockchip_pm_add_one_domain()
713 if (IS_ERR(pd->qos_regmap[j])) { in rockchip_pm_add_one_domain()
714 error = -ENODEV; in rockchip_pm_add_one_domain()
722 if (pd->info->name) in rockchip_pm_add_one_domain()
723 pd->genpd.name = pd->info->name; in rockchip_pm_add_one_domain()
725 pd->genpd.name = kbasename(node->full_name); in rockchip_pm_add_one_domain()
726 pd->genpd.power_off = rockchip_pd_power_off; in rockchip_pm_add_one_domain()
727 pd->genpd.power_on = rockchip_pd_power_on; in rockchip_pm_add_one_domain()
728 pd->genpd.attach_dev = rockchip_pd_attach_dev; in rockchip_pm_add_one_domain()
729 pd->genpd.detach_dev = rockchip_pd_detach_dev; in rockchip_pm_add_one_domain()
730 pd->genpd.flags = GENPD_FLAG_PM_CLK; in rockchip_pm_add_one_domain()
731 if (pd_info->active_wakeup) in rockchip_pm_add_one_domain()
732 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; in rockchip_pm_add_one_domain()
733 pm_genpd_init(&pd->genpd, NULL, in rockchip_pm_add_one_domain()
735 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); in rockchip_pm_add_one_domain()
737 pmu->genpd_data.domains[id] = &pd->genpd; in rockchip_pm_add_one_domain()
741 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
743 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
755 ret = pm_genpd_remove(&pd->genpd); in rockchip_pm_remove_one_domain()
757 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", in rockchip_pm_remove_one_domain()
758 pd->genpd.name, ret); in rockchip_pm_remove_one_domain()
760 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
761 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
763 /* protect the zeroing of pm->num_clks */ in rockchip_pm_remove_one_domain()
764 mutex_lock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
765 pd->num_clks = 0; in rockchip_pm_remove_one_domain()
766 mutex_unlock(&pd->pmu->mutex); in rockchip_pm_remove_one_domain()
777 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pm_domain_cleanup()
778 genpd = pmu->genpd_data.domains[i]; in rockchip_pm_domain_cleanup()
793 regmap_write(pmu->regmap, domain_reg_offset, count); in rockchip_configure_pd_cnt()
795 regmap_write(pmu->regmap, domain_reg_offset + 4, count); in rockchip_configure_pd_cnt()
810 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
815 parent_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
819 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n", in rockchip_pm_add_subdomain()
826 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
831 child_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
835 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n", in rockchip_pm_add_subdomain()
836 parent_domain->name, child_domain->name, error); in rockchip_pm_add_subdomain()
839 dev_dbg(pmu->dev, "%s add subdomain: %s\n", in rockchip_pm_add_subdomain()
840 parent_domain->name, child_domain->name); in rockchip_pm_add_subdomain()
855 struct device *dev = &pdev->dev; in rockchip_pm_domain_probe()
856 struct device_node *np = dev->of_node; in rockchip_pm_domain_probe()
866 return -ENODEV; in rockchip_pm_domain_probe()
869 match = of_match_device(dev->driver->of_match_table, dev); in rockchip_pm_domain_probe()
870 if (!match || !match->data) { in rockchip_pm_domain_probe()
872 return -EINVAL; in rockchip_pm_domain_probe()
875 pmu_info = match->data; in rockchip_pm_domain_probe()
878 struct_size(pmu, domains, pmu_info->num_domains), in rockchip_pm_domain_probe()
881 return -ENOMEM; in rockchip_pm_domain_probe()
883 pmu->dev = &pdev->dev; in rockchip_pm_domain_probe()
884 mutex_init(&pmu->mutex); in rockchip_pm_domain_probe()
886 pmu->info = pmu_info; in rockchip_pm_domain_probe()
888 pmu->genpd_data.domains = pmu->domains; in rockchip_pm_domain_probe()
889 pmu->genpd_data.num_domains = pmu_info->num_domains; in rockchip_pm_domain_probe()
891 parent = dev->parent; in rockchip_pm_domain_probe()
894 return -ENODEV; in rockchip_pm_domain_probe()
897 pmu->regmap = syscon_node_to_regmap(parent->of_node); in rockchip_pm_domain_probe()
898 if (IS_ERR(pmu->regmap)) { in rockchip_pm_domain_probe()
900 return PTR_ERR(pmu->regmap); in rockchip_pm_domain_probe()
907 if (pmu_info->core_power_transition_time) in rockchip_pm_domain_probe()
908 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, in rockchip_pm_domain_probe()
909 pmu_info->core_power_transition_time); in rockchip_pm_domain_probe()
910 if (pmu_info->gpu_pwrcnt_offset) in rockchip_pm_domain_probe()
911 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, in rockchip_pm_domain_probe()
912 pmu_info->gpu_power_transition_time); in rockchip_pm_domain_probe()
914 error = -ENODEV; in rockchip_pm_domain_probe()
945 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data); in rockchip_pm_domain_probe()
966 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
967 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
968 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
969 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
970 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
971 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
972 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
973 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
977 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
978 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
979 [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false),
980 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
981 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
982 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
983 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
984 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
988 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
989 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
990 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
991 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
992 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
993 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
994 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
998 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
999 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1000 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1001 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1002 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
1006 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
1007 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
1008 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
1009 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
1010 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
1014 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1015 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1016 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1017 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1018 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
1022 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
1023 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
1024 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
1025 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
1026 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
1027 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
1028 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
1029 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1030 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
1031 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
1032 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1036 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
1037 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
1038 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
1039 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
1043 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
1044 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
1045 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
1046 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
1047 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
1048 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1049 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
1050 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
1051 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
1055 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
1056 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
1057 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
1058 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
1059 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
1060 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
1061 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
1065 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
1066 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
1067 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
1068 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
1069 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1073 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
1074 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
1075 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
1076 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
1077 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
1078 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
1079 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
1080 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
1081 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
1082 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
1083 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
1084 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
1085 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
1086 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
1087 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
1088 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
1089 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
1090 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
1091 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
1092 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
1093 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
1094 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
1095 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
1096 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
1097 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
1098 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
1099 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1103 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
1104 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
1105 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false),
1106 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
1107 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1108 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1109 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1110 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
1111 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1115 …K3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0…
1116 …[RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, …
1117 …[RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0…
1118 …588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1…
1119 …K3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2…
1120 …K3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3…
1121 …3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4…
1122 …3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5…
1123 …88_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6…
1124 …88_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7…
1125 …K3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8…
1126 …[RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0,…
1127 …K3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9…
1128 …RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(1…
1129 …[RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, …
1130 …K3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(1…
1131 …3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(1…
1132 …OP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(1…
1133 …K3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(1…
1134 …K3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0…
1135 …3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1…
1136 …K3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5…
1137 …[RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, …
1138 …[RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, …
1139 …K3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2…
1140 …[RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, …
1141 …K3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3…
1142 …K3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4…
1143 …[RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0,…
1320 .compatible = "rockchip,px30-power-controller",
1324 .compatible = "rockchip,rk3036-power-controller",
1328 .compatible = "rockchip,rk3066-power-controller",
1332 .compatible = "rockchip,rk3128-power-controller",
1336 .compatible = "rockchip,rk3188-power-controller",
1340 .compatible = "rockchip,rk3228-power-controller",
1344 .compatible = "rockchip,rk3288-power-controller",
1348 .compatible = "rockchip,rk3328-power-controller",
1352 .compatible = "rockchip,rk3366-power-controller",
1356 .compatible = "rockchip,rk3368-power-controller",
1360 .compatible = "rockchip,rk3399-power-controller",
1364 .compatible = "rockchip,rk3568-power-controller",
1368 .compatible = "rockchip,rk3588-power-controller",
1372 .compatible = "rockchip,rv1126-power-controller",
1381 .name = "rockchip-pm-domain",