Lines Matching +full:tmr +full:- +full:manager +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
34 /*------------------------------------------------------------------------------
36 *----------------------------------------------------------------------------*/
51 #define AAC_INT_MODE_INTX (1<<0)
52 #define AAC_INT_MODE_MSI (1<<1)
53 #define AAC_INT_MODE_AIF (1<<2)
54 #define AAC_INT_MODE_SYNC (1<<3)
55 #define AAC_INT_MODE_MSIX (1<<16)
61 /* Bit definitions in IOA->Host Interrupt Register */
62 #define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
63 #define PMC_IOARCB_TRANSFER_FAILED (1<<28)
64 #define PMC_IOA_UNIT_CHECK (1<<27)
65 #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
66 #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
67 #define PMC_IOARRIN_LOST (1<<4)
68 #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
69 #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
70 #define PMC_HOST_RRQ_VALID (1<<1)
71 #define PMC_OPERATIONAL_STATUS (1<<31)
72 #define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
90 # define AAC_DRIVER_BRANCH "-custom"
95 #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
106 /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
119 #define SA_AIF_HOTPLUG (1<<1)
120 #define SA_AIF_HARDWARE (1<<2)
121 #define SA_AIF_PDEV_CHANGE (1<<4)
122 #define SA_AIF_LDEV_CHANGE (1<<5)
123 #define SA_AIF_BPSTAT_CHANGE (1<<30)
124 #define SA_AIF_BPCFG_CHANGE (1U<<31)
133 u32 addr_lo; /* Lower 32-bits of SGL element address */
134 u32 addr_hi; /* Upper 32-bits of SGL element address */
191 * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT
192 * [2] TYPE - 0=PCI, 1=DDR
193 * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled
200 /* Lower 32-bits of tweak value for crypto enabled IOs */
216 /* Lower 32-bits of reserved error data target location on the host */
219 /* Upper 32-bits of reserved error data target location on the host */
225 /* Upper 32-bits of tweak value for crypto enabled IOs */
232 * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE
258 /* Lower 32-bits of reserved error data target location on the host */
260 /* Upper 32-bits of reserved error data target location on the host */
268 /* 0 - reset specified device, 1 - reset all devices */
275 /* Lower 32-bits of reserved error data target location on the host */
277 /* Upper 32-bits of reserved error data target location on the host */
290 u8 datapres; /* [1:0] - data present, [7:2] - reserved */
300 struct aac_hba_tm_req tmr; member
301 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
316 u8 list_length[4]; /* LUN list length (N-7, big endian) */
325 } lun[1]; /* List of phys. devices */
413 #define NATIVE_CHANNEL (1)
423 #define aac_phys_to_logical(x) ((x)+1)
424 #define aac_logical_to_phys(x) ((x)?(x)-1:0)
430 #define AAC_CHARDEV_UNREGISTERED (-1)
431 #define AAC_CHARDEV_NEEDS_REINIT (-2)
450 #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
459 __le32 addr; /* 32-bit address. */
464 u32 addr; /* 32-bit address. */
469 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
474 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
505 * 32-bit addressing.
510 struct sgentry sg[1];
515 struct user_sgentry sg[1];
520 struct sgentry64 sg[1];
525 struct user_sgentry64 sg[1];
530 struct sgentryraw sg[1];
535 struct user_sgentryraw sg[1];
542 u8 via; /* e.g., 1 = FSU,
547 * unsigned Month :4; // 1 - 12
548 * unsigned Day :6; // 1 - 32
549 * unsigned Hour :6; // 0 - 23
550 * unsigned Minute :6; // 0 - 60
551 * unsigned Second :6; // 0 - 60
619 #define HostNormCmdQue 1 /* Change in host normal priority command queue */
678 #define FsaNormal 1
717 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
724 #define TestCommandResponse 1
785 HostOwned = (1<<0),
786 AdapterOwned = (1<<1),
787 FibInitialized = (1<<2),
788 FibEmpty = (1<<3),
789 AllocatedFromPool = (1<<4),
790 SentFromHost = (1<<5),
791 SentFromAdapter = (1<<6),
792 ResponseExpected = (1<<7),
793 NoResponseExpected = (1<<8),
794 AdapterProcessed = (1<<9),
795 HostProcessed = (1<<10),
796 HighPriority = (1<<11),
797 NormalPriority = (1<<12),
798 Async = (1<<13),
799 AsyncIo = (1<<13), // rpbfix: remove with new regime
800 PageFileIo = (1<<14), // rpbfix: remove with new regime
801 ShutdownRequest = (1<<15),
802 LazyWrite = (1<<16), // rpbfix: remove with new regime
803 AdapterMicroFib = (1<<17),
804 BIOSFibPath = (1<<18),
805 FastResponseCapable = (1<<19),
806 ApiFib = (1<<20), /* Its an API Fib */
808 NoMoreAifDataAvailable = (1<<21)
876 } rrq[1]; /* up to 64 RRQ addresses */
1022 __le32 reserved[10]; /* 00h-27h | Reserved */
1024 u8 reserved1[3]; /* 29h-2bh | Reserved */
1026 __le32 reserved2[26]; /* 30h-97h | Reserved */
1036 __le32 MAILBOX1; /* ach | Scratchpad 1 */
1045 __le32 reserved3[12]; /* d0h-ffh | reserved */
1046 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
1076 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
1080 #define SA_INIT_NUM_MSIXVECTORS 1
1083 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1084 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1085 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
1086 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
1140 struct rx_mu_registers MUnit; /* 1300h - 1347h */
1141 __le32 reserved1[2]; /* 1348h - 134ch */
1145 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
1146 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
1147 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
1148 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
1158 struct rkt_mu_registers MUnit; /* 1300h - 1347h */
1159 __le32 reserved1[1006]; /* 1348h - 22fch */
1160 struct rkt_inbound IndexRegs; /* 2300h - */
1163 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
1164 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
1165 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
1166 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
1177 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */
1198 struct src_mu_registers MUnit; /* 00h - cbh */
1201 __le32 reserved1[130786]; /* d8h - 7fc5fh */
1205 __le32 reserved1[970]; /* d8h - fffh */
1211 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
1212 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
1214 &((AEP)->regs.src.bar0->CSR))
1216 &((AEP)->regs.src.bar0->CSR))
1219 &((AEP)->regs.src.bar0->CSR))
1232 ulong jiffies; // used for cleanup - dmb changed to ulong
1242 u8 valid:1; /* A valid bit of one indicates that the information */
1244 * SCSI-2 Standard.
1248 u8 reserved:1;
1249 u8 ILI:1; /* Incorrect Length Indicator */
1250 u8 EOM:1; /* End Of Medium - reserved for random access devices */
1251 u8 filemark:1; /* Filemark - reserved for random access devices */
1253 u8 information[4]; /* for direct-access devices, contains the unsigned
1261 u8 FRUC; /* Field Replaceable Unit Code - not used */
1265 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
1269 u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
1270 * 0- illegal parameter in data.
1272 u8 SKSV:1;
1309 u32 done; /* gets set to 1 when fib is complete */
1328 #define AAC_RESCAN 1
1330 #define AAC_DEVTYPE_RAID_MEMBER 1
1339 s8 reset_state; /* 0 - no reset, 1..x - */
1379 u8 adapter_type_text[17+1];
1406 /* StructExpansion == 1 */
1412 u8 max_rrc_drives; /* max. number of ITP-RRC drives/pool */
1454 __le32 MethodId; /* 1 = SCSI Layer */
1475 #define AAC_BAT_REQ_PRESENT (1)
1483 #define AAC_CPU_SIMULATOR (1)
1490 #define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1491 #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1492 #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1493 #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1494 #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1495 #define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1496 #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1497 #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1498 #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1499 #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1500 #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1501 #define AAC_OPT_ALARM cpu_to_le32(1<<11)
1502 #define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1503 #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1504 #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1505 #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1506 #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1507 #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1508 #define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
1509 #define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25)
1510 #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1511 #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1512 #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1513 #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1516 #define AAC_COMM_MESSAGE 1
1521 #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
1522 #define AAC_EXTOPT_SOFT_RESET cpu_to_le32(1<<16)
1610 *This lock will protect the two 32-bit
1668 u32 max_msix; /* max. MSI-X vectors */
1669 u32 vector_cap; /* MSI-X vector capab.*/
1670 int msi_enabled; /* MSI/MSI-X enabled */
1684 (dev)->a_ops.adapter_interrupt(dev)
1687 (dev)->a_ops.adapter_notify(dev, event)
1690 (dev)->a_ops.adapter_disable_int(dev)
1693 (dev)->a_ops.adapter_enable_int(dev)
1696 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1699 ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1702 ((dev)->a_ops.adapter_start(dev))
1705 (dev)->a_ops.adapter_ioremap(dev, size)
1708 ((fib)->dev)->a_ops.adapter_deliver(fib)
1711 dev->a_ops.adapter_bounds(dev,cmd,lba)
1714 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1717 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1720 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1723 (dev)->a_ops.adapter_comm(dev, comm)
1739 #define GetAttributes 1
1786 #define ST_PERM 1
1826 #define CACHE_CSTABLE 1
1834 #define CMFILE_SYNCH_NVRAM 1
1945 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1963 #define CT_PM_UNIT_IMMEDIATE 1
1982 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
2048 * SRB Functions - set in aac_srb->function
2069 * SRB SCSI Status - set in aac_srb->scsi_status
2104 * Object-Server / Volume-Manager Dispatch Classes
2108 #define VM_NameServe 1
2132 #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
2136 * that a content manager might report. The
2138 * of a content manager. Raw mode might be
2177 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
2181 #define CFACT_PAUSE 1
2200 * Accept the configuration as-is
2245 manager (eg, filesystem) */
2253 #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
2266 struct aac_mntent mnt[1];
2278 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
2351 * Ugly - non Linux like ioctl coding for back compat.
2397 * If this value is set to 1 then interrupt moderation will occur
2461 u8 new_comm_interface:1;
2462 u8 new_commands_supported:1;
2463 u8 disable_passthrough:1;
2464 u8 expose_non_dasd:1;
2465 u8 queue_allowed:1;
2466 u8 bled_check_enabled:1;
2467 u8 reserved1:1;
2468 u8 reserted2:1;
2545 #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
2546 #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
2547 #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
2548 #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
2549 #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
2550 #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
2551 #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
2552 #define DoorBellAifPending (1<<6) /* Adapter -> Host */
2555 #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
2562 #define AifCmdEventNotify 1 /* Notify of event */
2586 #define AifJobStsSuccess 1 /* Job completes */
2636 return pci_channel_offline(dev->pdev) || dev->handle_pci_error; in aac_pci_offline()
2642 return -1; in aac_adapter_check_health()
2644 return (dev)->a_ops.adapter_check_health(dev); in aac_adapter_check_health()
2652 schedule_delayed_work(&dev->safw_rescan_work, AAC_RESCAN_DELAY); in aac_schedule_safw_scan_worker()
2657 schedule_delayed_work(&dev->src_reinit_aif_worker, AAC_RESCAN_DELAY); in aac_schedule_src_reinit_aif_worker()
2665 wait_event(dev->scsi_host_ptr->host_wait, in aac_safw_rescan_worker()
2666 !scsi_host_in_recovery(dev->scsi_host_ptr)); in aac_safw_rescan_worker()
2673 cancel_delayed_work_sync(&dev->safw_rescan_work); in aac_cancel_rescan_worker()
2674 cancel_delayed_work_sync(&dev->src_reinit_aif_worker); in aac_cancel_rescan_worker()
2717 #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2726 #define shost_to_class(shost) &shost->shost_dev
2759 u16 device = dev->pdev->device; in aac_is_src()
2764 return 1; in aac_is_src()
2770 return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64); in aac_supports_2T()