Lines Matching +full:svs +full:- +full:calibration +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/nvmem-consumer.h>
35 /* svs bank 1-line software id */
41 /* svs bank 2-line type */
45 /* svs bank mode support */
51 /* svs bank volt flags */
58 /* svs bank register fields and common configuration */
131 /* svs bank related setting */
148 inode->i_private); \
163 inode->i_private); \
178 * enum svsb_phase - svs bank phase enumeration
179 * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition
180 * @SVSB_PHASE_INIT01: svs bank basic init for data calibration
181 * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table
182 * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect
183 * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
185 * Each svs bank has its own independent phase and we enable each svs bank by
186 * running their phase orderly. However, when svs bank encounters unexpected
187 * condition, it will fire an irq (PHASE_ERROR) to inform svs software.
189 * svs bank general phase-enabled order:
190 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
316 * struct svs_platform - svs platform control
317 * @base: svs platform register base
318 * @dev: svs platform device
319 * @main_clk: main clock for svs bank
320 * @pbank: svs bank pointer needing to be protected by spin_lock section
321 * @banks: svs banks that svs platform supports
322 * @rst: svs platform reset control
323 * @efuse_max: total number of svs efuse
325 * @regs: svs platform registers map
326 * @bank_max: total number of svs banks
327 * @efuse: svs efuse data received from NVMEM framework
328 * @tefuse: thermal efuse data received from NVMEM framework
355 * struct svs_bank - svs bank representation
369 * @reg_data: bank register data in different phase for debug purpose
373 * @turn_freq_base: refenrece frequency for 2-line turn point
395 * @cpu_id: cpu core id for SVS CPU bank use only
396 * @ctl0: TS-x selection
402 * @bts: svs efuse data
403 * @mts: svs efuse data
404 * @bdes: svs efuse data
405 * @mdes: svs efuse data
406 * @mtdes: svs efuse data
407 * @dcbdet: svs efuse data
408 * @dcmdet: svs efuse data
409 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
410 * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank
412 * Svs bank will generate suitalbe voltages by below general math equation
477 /* If not divide 1000, "numerator * 100" will have data overflow. */ in percent()
486 return readl_relaxed(svsp->base + svsp->regs[rg_i]); in svs_readl_relaxed()
492 writel_relaxed(val, svsp->base + svsp->regs[rg_i]); in svs_writel_relaxed()
497 struct svs_bank *svsb = svsp->pbank; in svs_switch_bank()
499 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); in svs_switch_bank()
511 return (opp_u_volt - svsb_volt_base) / svsb_volt_step; in svs_opp_volt_to_bank_volt()
519 for (i = 0; i < svsb->opp_count; i++) { in svs_sync_bank_volts_from_opp()
520 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, in svs_sync_bank_volts_from_opp()
521 svsb->opp_dfreq[i], in svs_sync_bank_volts_from_opp()
524 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n", in svs_sync_bank_volts_from_opp()
525 svsb->opp_dfreq[i], PTR_ERR(opp)); in svs_sync_bank_volts_from_opp()
530 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, in svs_sync_bank_volts_from_opp()
531 svsb->volt_step, in svs_sync_bank_volts_from_opp()
532 svsb->volt_base); in svs_sync_bank_volts_from_opp()
541 int ret = -EPERM, tzone_temp = 0; in svs_adjust_pm_opp_volts()
544 mutex_lock(&svsb->lock); in svs_adjust_pm_opp_volts()
547 * 2-line bank updates its corresponding opp volts. in svs_adjust_pm_opp_volts()
548 * 1-line bank updates all opp volts. in svs_adjust_pm_opp_volts()
550 if (svsb->type == SVSB_HIGH) { in svs_adjust_pm_opp_volts()
552 opp_stop = svsb->turn_pt; in svs_adjust_pm_opp_volts()
553 } else if (svsb->type == SVSB_LOW) { in svs_adjust_pm_opp_volts()
554 opp_start = svsb->turn_pt; in svs_adjust_pm_opp_volts()
555 opp_stop = svsb->opp_count; in svs_adjust_pm_opp_volts()
558 opp_stop = svsb->opp_count; in svs_adjust_pm_opp_volts()
562 if (!IS_ERR_OR_NULL(svsb->tzd)) { in svs_adjust_pm_opp_volts()
563 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); in svs_adjust_pm_opp_volts()
564 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && in svs_adjust_pm_opp_volts()
565 svsb->temp < SVSB_TEMP_LOWER_BOUND)) { in svs_adjust_pm_opp_volts()
566 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", in svs_adjust_pm_opp_volts()
567 svsb->tzone_name, ret, svsb->temp); in svs_adjust_pm_opp_volts()
568 svsb->phase = SVSB_PHASE_ERROR; in svs_adjust_pm_opp_volts()
571 if (tzone_temp >= svsb->tzone_htemp) in svs_adjust_pm_opp_volts()
572 temp_voffset += svsb->tzone_htemp_voffset; in svs_adjust_pm_opp_volts()
573 else if (tzone_temp <= svsb->tzone_ltemp) in svs_adjust_pm_opp_volts()
574 temp_voffset += svsb->tzone_ltemp_voffset; in svs_adjust_pm_opp_volts()
576 /* 2-line bank update all opp volts when running mon mode */ in svs_adjust_pm_opp_volts()
577 if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH || in svs_adjust_pm_opp_volts()
578 svsb->type == SVSB_LOW)) { in svs_adjust_pm_opp_volts()
580 opp_stop = svsb->opp_count; in svs_adjust_pm_opp_volts()
586 switch (svsb->phase) { in svs_adjust_pm_opp_volts()
588 opp_volt = svsb->opp_dvolt[i]; in svs_adjust_pm_opp_volts()
595 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); in svs_adjust_pm_opp_volts()
597 svsb->volt_step, in svs_adjust_pm_opp_volts()
598 svsb->volt_base); in svs_adjust_pm_opp_volts()
601 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); in svs_adjust_pm_opp_volts()
602 ret = -EINVAL; in svs_adjust_pm_opp_volts()
606 opp_volt = min(opp_volt, svsb->opp_dvolt[i]); in svs_adjust_pm_opp_volts()
607 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, in svs_adjust_pm_opp_volts()
608 svsb->opp_dfreq[i], in svs_adjust_pm_opp_volts()
610 svsb->opp_dvolt[i]); in svs_adjust_pm_opp_volts()
612 dev_err(svsb->dev, "set %uuV fail: %d\n", in svs_adjust_pm_opp_volts()
619 mutex_unlock(&svsb->lock); in svs_adjust_pm_opp_volts()
629 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) in svs_bank_disable_and_restore_default_volts()
633 svsp->pbank = svsb; in svs_bank_disable_and_restore_default_volts()
639 svsb->phase = SVSB_PHASE_ERROR; in svs_bank_disable_and_restore_default_volts()
646 struct svs_platform *svsp = (struct svs_platform *)m->private; in svs_dump_debug_show()
651 for (i = 0; i < svsp->efuse_max; i++) in svs_dump_debug_show()
652 if (svsp->efuse && svsp->efuse[i]) in svs_dump_debug_show()
654 i, svsp->efuse[i]); in svs_dump_debug_show()
656 for (i = 0; i < svsp->tefuse_max; i++) in svs_dump_debug_show()
657 if (svsp->tefuse) in svs_dump_debug_show()
659 i, svsp->tefuse[i]); in svs_dump_debug_show()
661 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) { in svs_dump_debug_show()
662 svsb = &svsp->banks[idx]; in svs_dump_debug_show()
675 svs_reg_addr = (unsigned long)(svsp->base + in svs_dump_debug_show()
676 svsp->regs[j]); in svs_dump_debug_show()
678 svs_reg_addr, svsb->reg_data[i][j]); in svs_dump_debug_show()
690 struct svs_bank *svsb = (struct svs_bank *)m->private; in svs_enable_debug_show()
692 switch (svsb->phase) { in svs_enable_debug_show()
717 struct svs_bank *svsb = file_inode(filp)->i_private; in svs_enable_debug_write()
718 struct svs_platform *svsp = dev_get_drvdata(svsb->dev); in svs_enable_debug_write()
723 return -EINVAL; in svs_enable_debug_write()
735 svsb->mode_support = SVSB_MODE_ALL_DISABLE; in svs_enable_debug_write()
747 struct svs_bank *svsb = (struct svs_bank *)m->private; in svs_status_debug_show()
752 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); in svs_status_debug_show()
755 svsb->name, svsb->turn_pt); in svs_status_debug_show()
758 svsb->name, tzone_temp, svsb->turn_pt); in svs_status_debug_show()
760 for (i = 0; i < svsb->opp_count; i++) { in svs_status_debug_show()
761 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, in svs_status_debug_show()
762 svsb->opp_dfreq[i], true); in svs_status_debug_show()
765 svsb->name, svsb->opp_dfreq[i], in svs_status_debug_show()
771 i, svsb->opp_dfreq[i], i, in svs_status_debug_show()
774 i, svsb->volt[i], i, svsb->freq_pct[i]); in svs_status_debug_show()
787 const char *d = "/sys/kernel/debug/svs"; in svs_create_debug_cmds()
804 svs_dir = debugfs_create_dir("svs", NULL); in svs_create_debug_cmds()
806 dev_err(svsp->dev, "cannot create %s: %ld\n", in svs_create_debug_cmds()
816 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", in svs_create_debug_cmds()
822 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_create_debug_cmds()
823 svsb = &svsp->banks[idx]; in svs_create_debug_cmds()
825 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) in svs_create_debug_cmds()
828 svsb_dir = debugfs_create_dir(svsb->name, svs_dir); in svs_create_debug_cmds()
830 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", in svs_create_debug_cmds()
831 d, svsb->name, PTR_ERR(svsb_dir)); in svs_create_debug_cmds()
840 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n", in svs_create_debug_cmds()
841 d, svsb->name, svsb_entries[i].name, in svs_create_debug_cmds()
860 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx)); in interpolate()
867 struct svs_bank *svsb = svsp->pbank; in svs_get_bank_volts_v3()
868 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; in svs_get_bank_volts_v3()
870 u32 middle_index = (svsb->opp_count / 2); in svs_get_bank_volts_v3()
872 if (svsb->phase == SVSB_PHASE_MON && in svs_get_bank_volts_v3()
873 svsb->volt_flags & SVSB_MON_VOLT_IGNORE) in svs_get_bank_volts_v3()
879 /* Target is to set svsb->volt[] by algorithm */ in svs_get_bank_volts_v3()
881 if (svsb->type == SVSB_HIGH) { in svs_get_bank_volts_v3()
882 /* volt[0] ~ volt[turn_pt - 1] */ in svs_get_bank_volts_v3()
887 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
890 } else if (svsb->type == SVSB_LOW) { in svs_get_bank_volts_v3()
891 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ in svs_get_bank_volts_v3()
892 j = svsb->opp_count - 7; in svs_get_bank_volts_v3()
893 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); in svs_get_bank_volts_v3()
895 for (i = j; i < svsb->opp_count; i++) { in svs_get_bank_volts_v3()
899 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
903 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */ in svs_get_bank_volts_v3()
905 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt], in svs_get_bank_volts_v3()
906 svsb->freq_pct[j], in svs_get_bank_volts_v3()
907 svsb->volt[turn_pt], in svs_get_bank_volts_v3()
908 svsb->volt[j], in svs_get_bank_volts_v3()
909 svsb->freq_pct[i]); in svs_get_bank_volts_v3()
912 if (svsb->type == SVSB_HIGH) { in svs_get_bank_volts_v3()
913 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ in svs_get_bank_volts_v3()
914 j = turn_pt - 7; in svs_get_bank_volts_v3()
915 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); in svs_get_bank_volts_v3()
921 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
925 /* volt[1] ~ volt[j - 1] by interpolate */ in svs_get_bank_volts_v3()
927 svsb->volt[i] = interpolate(svsb->freq_pct[0], in svs_get_bank_volts_v3()
928 svsb->freq_pct[j], in svs_get_bank_volts_v3()
929 svsb->volt[0], in svs_get_bank_volts_v3()
930 svsb->volt[j], in svs_get_bank_volts_v3()
931 svsb->freq_pct[i]); in svs_get_bank_volts_v3()
932 } else if (svsb->type == SVSB_LOW) { in svs_get_bank_volts_v3()
933 /* volt[turn_pt] ~ volt[opp_count - 1] */ in svs_get_bank_volts_v3()
934 for (i = turn_pt; i < svsb->opp_count; i++) { in svs_get_bank_volts_v3()
938 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
944 if (svsb->type == SVSB_HIGH) { in svs_get_bank_volts_v3()
946 opp_stop = svsb->turn_pt; in svs_get_bank_volts_v3()
947 } else if (svsb->type == SVSB_LOW) { in svs_get_bank_volts_v3()
948 opp_start = svsb->turn_pt; in svs_get_bank_volts_v3()
949 opp_stop = svsb->opp_count; in svs_get_bank_volts_v3()
953 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) in svs_get_bank_volts_v3()
954 svsb->volt[i] -= svsb->dvt_fixed; in svs_get_bank_volts_v3()
959 struct svs_bank *svsb = svsp->pbank; in svs_set_bank_freq_pct_v3()
962 u32 middle_index = (svsb->opp_count / 2); in svs_set_bank_freq_pct_v3()
964 for (i = 0; i < svsb->opp_count; i++) { in svs_set_bank_freq_pct_v3()
965 if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { in svs_set_bank_freq_pct_v3()
966 svsb->turn_pt = i; in svs_set_bank_freq_pct_v3()
971 turn_pt = svsb->turn_pt; in svs_set_bank_freq_pct_v3()
975 if (svsb->type == SVSB_HIGH) { in svs_set_bank_freq_pct_v3()
982 freq_pct30 = svsb->freq_pct[0]; in svs_set_bank_freq_pct_v3()
984 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */ in svs_set_bank_freq_pct_v3()
989 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
992 } else if (svsb->type == SVSB_LOW) { in svs_set_bank_freq_pct_v3()
995 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] in svs_set_bank_freq_pct_v3()
997 freq_pct30 = svsb->freq_pct[turn_pt]; in svs_set_bank_freq_pct_v3()
999 j = svsb->opp_count - 7; in svs_set_bank_freq_pct_v3()
1000 for (i = j; i < svsb->opp_count; i++) { in svs_set_bank_freq_pct_v3()
1004 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1009 if (svsb->type == SVSB_HIGH) { in svs_set_bank_freq_pct_v3()
1012 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] in svs_set_bank_freq_pct_v3()
1014 freq_pct30 = svsb->freq_pct[0]; in svs_set_bank_freq_pct_v3()
1016 j = turn_pt - 7; in svs_set_bank_freq_pct_v3()
1021 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1024 } else if (svsb->type == SVSB_LOW) { in svs_set_bank_freq_pct_v3()
1025 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ in svs_set_bank_freq_pct_v3()
1026 for (i = turn_pt; i < svsb->opp_count; i++) { in svs_set_bank_freq_pct_v3()
1030 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1042 struct svs_bank *svsb = svsp->pbank; in svs_get_bank_volts_v2()
1046 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); in svs_get_bank_volts_v2()
1047 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); in svs_get_bank_volts_v2()
1048 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); in svs_get_bank_volts_v2()
1049 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); in svs_get_bank_volts_v2()
1052 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); in svs_get_bank_volts_v2()
1053 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); in svs_get_bank_volts_v2()
1054 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); in svs_get_bank_volts_v2()
1055 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); in svs_get_bank_volts_v2()
1058 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i], in svs_get_bank_volts_v2()
1059 svsb->freq_pct[i + 2], in svs_get_bank_volts_v2()
1060 svsb->volt[i], in svs_get_bank_volts_v2()
1061 svsb->volt[i + 2], in svs_get_bank_volts_v2()
1062 svsb->freq_pct[i + 1]); in svs_get_bank_volts_v2()
1064 svsb->volt[15] = interpolate(svsb->freq_pct[12], in svs_get_bank_volts_v2()
1065 svsb->freq_pct[14], in svs_get_bank_volts_v2()
1066 svsb->volt[12], in svs_get_bank_volts_v2()
1067 svsb->volt[14], in svs_get_bank_volts_v2()
1068 svsb->freq_pct[15]); in svs_get_bank_volts_v2()
1070 for (i = 0; i < svsb->opp_count; i++) in svs_get_bank_volts_v2()
1071 svsb->volt[i] += svsb->volt_od; in svs_get_bank_volts_v2()
1076 struct svs_bank *svsb = svsp->pbank; in svs_set_bank_freq_pct_v2()
1079 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | in svs_set_bank_freq_pct_v2()
1080 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) | in svs_set_bank_freq_pct_v2()
1081 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) | in svs_set_bank_freq_pct_v2()
1082 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]); in svs_set_bank_freq_pct_v2()
1084 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) | in svs_set_bank_freq_pct_v2()
1085 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) | in svs_set_bank_freq_pct_v2()
1086 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) | in svs_set_bank_freq_pct_v2()
1087 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]); in svs_set_bank_freq_pct_v2()
1096 struct svs_bank *svsb = svsp->pbank; in svs_set_bank_phase()
1101 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | in svs_set_bank_phase()
1102 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); in svs_set_bank_phase()
1105 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) | in svs_set_bank_phase()
1106 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | in svs_set_bank_phase()
1107 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); in svs_set_bank_phase()
1110 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) | in svs_set_bank_phase()
1111 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); in svs_set_bank_phase()
1114 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); in svs_set_bank_phase()
1115 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); in svs_set_bank_phase()
1118 svsb->set_freq_pct(svsp); in svs_set_bank_phase()
1122 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) | in svs_set_bank_phase()
1123 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax); in svs_set_bank_phase()
1128 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); in svs_set_bank_phase()
1129 svs_writel_relaxed(svsp, svsb->ctl0, CTL0); in svs_set_bank_phase()
1134 svs_writel_relaxed(svsp, svsb->vboot, VBOOT); in svs_set_bank_phase()
1139 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) | in svs_set_bank_phase()
1140 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in); in svs_set_bank_phase()
1146 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) | in svs_set_bank_phase()
1147 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts); in svs_set_bank_phase()
1153 dev_err(svsb->dev, "requested unknown target phase: %u\n", in svs_set_bank_phase()
1162 struct svs_bank *svsb = svsp->pbank; in svs_save_bank_register_data()
1166 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); in svs_save_bank_register_data()
1171 struct svs_bank *svsb = svsp->pbank; in svs_error_isr_handler()
1173 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", in svs_error_isr_handler()
1175 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n", in svs_error_isr_handler()
1178 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n", in svs_error_isr_handler()
1181 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); in svs_error_isr_handler()
1185 svsb->phase = SVSB_PHASE_ERROR; in svs_error_isr_handler()
1192 struct svs_bank *svsb = svsp->pbank; in svs_init01_isr_handler()
1194 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", in svs_init01_isr_handler()
1201 svsb->phase = SVSB_PHASE_INIT01; in svs_init01_isr_handler()
1202 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & in svs_init01_isr_handler()
1204 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || in svs_init01_isr_handler()
1205 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && in svs_init01_isr_handler()
1206 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) in svs_init01_isr_handler()
1207 svsb->dc_voffset_in = 0; in svs_init01_isr_handler()
1209 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) & in svs_init01_isr_handler()
1214 svsb->core_sel &= ~SVSB_DET_CLK_EN; in svs_init01_isr_handler()
1219 struct svs_bank *svsb = svsp->pbank; in svs_init02_isr_handler()
1221 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", in svs_init02_isr_handler()
1228 svsb->phase = SVSB_PHASE_INIT02; in svs_init02_isr_handler()
1229 svsb->get_volts(svsp); in svs_init02_isr_handler()
1237 struct svs_bank *svsb = svsp->pbank; in svs_mon_mode_isr_handler()
1241 svsb->phase = SVSB_PHASE_MON; in svs_mon_mode_isr_handler()
1242 svsb->get_volts(svsp); in svs_mon_mode_isr_handler()
1244 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); in svs_mon_mode_isr_handler()
1248 static irqreturn_t svs_isr(int irq, void *data) in svs_isr() argument
1250 struct svs_platform *svsp = data; in svs_isr()
1255 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_isr()
1256 svsb = &svsp->banks[idx]; in svs_isr()
1257 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); in svs_isr()
1260 svsp->pbank = svsb; in svs_isr()
1262 /* Find out which svs bank fires interrupt */ in svs_isr()
1263 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { in svs_isr()
1289 if (svsb->phase == SVSB_PHASE_INIT01 || in svs_isr()
1290 svsb->phase == SVSB_PHASE_INIT02) in svs_isr()
1291 complete(&svsb->init_completion); in svs_isr()
1307 /* Svs bank init01 preparation - power enable */ in svs_init01()
1308 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1309 svsb = &svsp->banks[idx]; in svs_init01()
1311 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1314 ret = regulator_enable(svsb->buck); in svs_init01()
1316 dev_err(svsb->dev, "%s enable fail: %d\n", in svs_init01()
1317 svsb->buck_name, ret); in svs_init01()
1322 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST); in svs_init01()
1324 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret); in svs_init01()
1326 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { in svs_init01()
1327 if (!pm_runtime_enabled(svsb->opp_dev)) { in svs_init01()
1328 pm_runtime_enable(svsb->opp_dev); in svs_init01()
1329 svsb->pm_runtime_enabled_count++; in svs_init01()
1332 ret = pm_runtime_resume_and_get(svsb->opp_dev); in svs_init01()
1334 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret); in svs_init01()
1341 * Svs bank init01 preparation - vboot voltage adjustment in svs_init01()
1342 * Sometimes two svs banks use the same buck. Therefore, in svs_init01()
1343 * we have to set each svs bank to target voltage(vboot) first. in svs_init01()
1345 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1346 svsb = &svsp->banks[idx]; in svs_init01()
1348 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1356 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, in svs_init01()
1357 svsb->volt_step, in svs_init01()
1358 svsb->volt_base); in svs_init01()
1360 for (i = 0; i < svsb->opp_count; i++) { in svs_init01()
1361 opp_freq = svsb->opp_dfreq[i]; in svs_init01()
1362 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { in svs_init01()
1363 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, in svs_init01()
1369 dev_err(svsb->dev, in svs_init01()
1377 ret = dev_pm_opp_disable(svsb->opp_dev, in svs_init01()
1378 svsb->opp_dfreq[i]); in svs_init01()
1380 dev_err(svsb->dev, in svs_init01()
1382 svsb->opp_dfreq[i], ret); in svs_init01()
1389 /* Svs bank init01 begins */ in svs_init01()
1390 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1391 svsb = &svsp->banks[idx]; in svs_init01()
1393 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1396 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, in svs_init01()
1397 svsb->volt_step, in svs_init01()
1398 svsb->volt_base); in svs_init01()
1400 buck_volt = regulator_get_voltage(svsb->buck); in svs_init01()
1402 dev_err(svsb->dev, in svs_init01()
1405 ret = -EPERM; in svs_init01()
1410 svsp->pbank = svsb; in svs_init01()
1414 time_left = wait_for_completion_timeout(&svsb->init_completion, in svs_init01()
1417 dev_err(svsb->dev, "init01 completion timeout\n"); in svs_init01()
1418 ret = -EBUSY; in svs_init01()
1424 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1425 svsb = &svsp->banks[idx]; in svs_init01()
1427 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1430 for (i = 0; i < svsb->opp_count; i++) { in svs_init01()
1431 r = dev_pm_opp_enable(svsb->opp_dev, in svs_init01()
1432 svsb->opp_dfreq[i]); in svs_init01()
1434 dev_err(svsb->dev, "opp %uHz enable fail: %d\n", in svs_init01()
1435 svsb->opp_dfreq[i], r); in svs_init01()
1438 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { in svs_init01()
1439 r = pm_runtime_put_sync(svsb->opp_dev); in svs_init01()
1441 dev_err(svsb->dev, "mtcmos off fail: %d\n", r); in svs_init01()
1443 if (svsb->pm_runtime_enabled_count > 0) { in svs_init01()
1444 pm_runtime_disable(svsb->opp_dev); in svs_init01()
1445 svsb->pm_runtime_enabled_count--; in svs_init01()
1449 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL); in svs_init01()
1451 dev_notice(svsb->dev, "set normal mode fail: %d\n", r); in svs_init01()
1453 r = regulator_disable(svsb->buck); in svs_init01()
1455 dev_err(svsb->dev, "%s disable fail: %d\n", in svs_init01()
1456 svsb->buck_name, r); in svs_init01()
1472 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init02()
1473 svsb = &svsp->banks[idx]; in svs_init02()
1475 if (!(svsb->mode_support & SVSB_MODE_INIT02)) in svs_init02()
1478 reinit_completion(&svsb->init_completion); in svs_init02()
1480 svsp->pbank = svsb; in svs_init02()
1484 time_left = wait_for_completion_timeout(&svsb->init_completion, in svs_init02()
1487 dev_err(svsb->dev, "init02 completion timeout\n"); in svs_init02()
1488 ret = -EBUSY; in svs_init02()
1494 * 2-line high/low bank update its corresponding opp voltages only. in svs_init02()
1498 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init02()
1499 svsb = &svsp->banks[idx]; in svs_init02()
1501 if (!(svsb->mode_support & SVSB_MODE_INIT02)) in svs_init02()
1504 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { in svs_init02()
1506 dev_err(svsb->dev, "sync volt fail\n"); in svs_init02()
1507 ret = -EPERM; in svs_init02()
1516 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init02()
1517 svsb = &svsp->banks[idx]; in svs_init02()
1530 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mon_mode()
1531 svsb = &svsp->banks[idx]; in svs_mon_mode()
1533 if (!(svsb->mode_support & SVSB_MODE_MON)) in svs_mon_mode()
1537 svsp->pbank = svsb; in svs_mon_mode()
1567 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_suspend()
1568 svsb = &svsp->banks[idx]; in svs_suspend()
1572 ret = reset_control_assert(svsp->rst); in svs_suspend()
1574 dev_err(svsp->dev, "cannot assert reset %d\n", ret); in svs_suspend()
1578 clk_disable_unprepare(svsp->main_clk); in svs_suspend()
1588 ret = clk_prepare_enable(svsp->main_clk); in svs_resume()
1590 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n"); in svs_resume()
1594 ret = reset_control_deassert(svsp->rst); in svs_resume()
1596 dev_err(svsp->dev, "cannot deassert reset %d\n", ret); in svs_resume()
1609 dev_err(svsp->dev, "assert reset: %d\n", in svs_resume()
1610 reset_control_assert(svsp->rst)); in svs_resume()
1613 clk_disable_unprepare(svsp->main_clk); in svs_resume()
1625 dev_set_drvdata(svsp->dev, svsp); in svs_bank_resource_setup()
1627 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_bank_resource_setup()
1628 svsb = &svsp->banks[idx]; in svs_bank_resource_setup()
1630 switch (svsb->sw_id) { in svs_bank_resource_setup()
1632 svsb->name = "SVSB_CPU_LITTLE"; in svs_bank_resource_setup()
1635 svsb->name = "SVSB_CPU_BIG"; in svs_bank_resource_setup()
1638 svsb->name = "SVSB_CCI"; in svs_bank_resource_setup()
1641 if (svsb->type == SVSB_HIGH) in svs_bank_resource_setup()
1642 svsb->name = "SVSB_GPU_HIGH"; in svs_bank_resource_setup()
1643 else if (svsb->type == SVSB_LOW) in svs_bank_resource_setup()
1644 svsb->name = "SVSB_GPU_LOW"; in svs_bank_resource_setup()
1646 svsb->name = "SVSB_GPU"; in svs_bank_resource_setup()
1649 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); in svs_bank_resource_setup()
1650 return -EINVAL; in svs_bank_resource_setup()
1653 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), in svs_bank_resource_setup()
1655 if (!svsb->dev) in svs_bank_resource_setup()
1656 return -ENOMEM; in svs_bank_resource_setup()
1658 ret = dev_set_name(svsb->dev, "%s", svsb->name); in svs_bank_resource_setup()
1662 dev_set_drvdata(svsb->dev, svsp); in svs_bank_resource_setup()
1664 ret = devm_pm_opp_of_add_table(svsb->opp_dev); in svs_bank_resource_setup()
1666 dev_err(svsb->dev, "add opp table fail: %d\n", ret); in svs_bank_resource_setup()
1670 mutex_init(&svsb->lock); in svs_bank_resource_setup()
1671 init_completion(&svsb->init_completion); in svs_bank_resource_setup()
1673 if (svsb->mode_support & SVSB_MODE_INIT01) { in svs_bank_resource_setup()
1674 svsb->buck = devm_regulator_get_optional(svsb->opp_dev, in svs_bank_resource_setup()
1675 svsb->buck_name); in svs_bank_resource_setup()
1676 if (IS_ERR(svsb->buck)) { in svs_bank_resource_setup()
1677 dev_err(svsb->dev, "cannot get \"%s-supply\"\n", in svs_bank_resource_setup()
1678 svsb->buck_name); in svs_bank_resource_setup()
1679 return PTR_ERR(svsb->buck); in svs_bank_resource_setup()
1683 if (!IS_ERR_OR_NULL(svsb->tzone_name)) { in svs_bank_resource_setup()
1684 svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); in svs_bank_resource_setup()
1685 if (IS_ERR(svsb->tzd)) { in svs_bank_resource_setup()
1686 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", in svs_bank_resource_setup()
1687 svsb->tzone_name); in svs_bank_resource_setup()
1688 return PTR_ERR(svsb->tzd); in svs_bank_resource_setup()
1692 count = dev_pm_opp_get_opp_count(svsb->opp_dev); in svs_bank_resource_setup()
1693 if (svsb->opp_count != count) { in svs_bank_resource_setup()
1694 dev_err(svsb->dev, in svs_bank_resource_setup()
1696 svsb->opp_count, count); in svs_bank_resource_setup()
1700 for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { in svs_bank_resource_setup()
1701 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); in svs_bank_resource_setup()
1703 dev_err(svsb->dev, "cannot find freq = %ld\n", in svs_bank_resource_setup()
1708 svsb->opp_dfreq[i] = freq; in svs_bank_resource_setup()
1709 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp); in svs_bank_resource_setup()
1710 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i], in svs_bank_resource_setup()
1711 svsb->freq_base); in svs_bank_resource_setup()
1725 cell = nvmem_cell_get(svsp->dev, nvmem_cell_name); in svs_get_efuse_data()
1727 dev_err(svsp->dev, "no \"%s\"? %ld\n", in svs_get_efuse_data()
1734 dev_err(svsp->dev, "cannot read \"%s\" efuse: %ld\n", in svs_get_efuse_data()
1752 for (i = 0; i < svsp->efuse_max; i++) in svs_mt8192_efuse_parsing()
1753 if (svsp->efuse[i]) in svs_mt8192_efuse_parsing()
1754 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", in svs_mt8192_efuse_parsing()
1755 i, svsp->efuse[i]); in svs_mt8192_efuse_parsing()
1757 if (!svsp->efuse[9]) { in svs_mt8192_efuse_parsing()
1758 dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); in svs_mt8192_efuse_parsing()
1762 /* Svs efuse parsing */ in svs_mt8192_efuse_parsing()
1763 vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); in svs_mt8192_efuse_parsing()
1765 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8192_efuse_parsing()
1766 svsb = &svsp->banks[idx]; in svs_mt8192_efuse_parsing()
1769 svsb->vmin = 0x1e; in svs_mt8192_efuse_parsing()
1771 if (svsb->type == SVSB_LOW) { in svs_mt8192_efuse_parsing()
1772 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1773 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1774 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1775 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1776 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1777 } else if (svsb->type == SVSB_HIGH) { in svs_mt8192_efuse_parsing()
1778 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1779 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1780 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1781 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1782 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1785 svsb->vmax += svsb->dvt_fixed; in svs_mt8192_efuse_parsing()
1788 ret = svs_get_efuse_data(svsp, "t-calibration-data", in svs_mt8192_efuse_parsing()
1789 &svsp->tefuse, &svsp->tefuse_max); in svs_mt8192_efuse_parsing()
1793 for (i = 0; i < svsp->tefuse_max; i++) in svs_mt8192_efuse_parsing()
1794 if (svsp->tefuse[i] != 0) in svs_mt8192_efuse_parsing()
1797 if (i == svsp->tefuse_max) in svs_mt8192_efuse_parsing()
1798 golden_temp = 50; /* All thermal efuse data are 0 */ in svs_mt8192_efuse_parsing()
1800 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1802 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8192_efuse_parsing()
1803 svsb = &svsp->banks[idx]; in svs_mt8192_efuse_parsing()
1804 svsb->mts = 500; in svs_mt8192_efuse_parsing()
1805 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; in svs_mt8192_efuse_parsing()
1820 for (i = 0; i < svsp->efuse_max; i++) in svs_mt8183_efuse_parsing()
1821 if (svsp->efuse[i]) in svs_mt8183_efuse_parsing()
1822 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", in svs_mt8183_efuse_parsing()
1823 i, svsp->efuse[i]); in svs_mt8183_efuse_parsing()
1825 if (!svsp->efuse[2]) { in svs_mt8183_efuse_parsing()
1826 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n"); in svs_mt8183_efuse_parsing()
1830 /* Svs efuse parsing */ in svs_mt8183_efuse_parsing()
1831 ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); in svs_mt8183_efuse_parsing()
1833 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
1834 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
1837 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; in svs_mt8183_efuse_parsing()
1839 switch (svsb->sw_id) { in svs_mt8183_efuse_parsing()
1841 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1842 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1843 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1844 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1845 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1848 svsb->volt_od += 10; in svs_mt8183_efuse_parsing()
1850 svsb->volt_od += 2; in svs_mt8183_efuse_parsing()
1853 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1854 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1855 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1856 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1857 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1860 svsb->volt_od += 15; in svs_mt8183_efuse_parsing()
1862 svsb->volt_od += 12; in svs_mt8183_efuse_parsing()
1865 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1866 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1867 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1868 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1869 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1872 svsb->volt_od += 10; in svs_mt8183_efuse_parsing()
1874 svsb->volt_od += 2; in svs_mt8183_efuse_parsing()
1877 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1878 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1879 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1880 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1881 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1884 svsb->freq_base = 800000000; /* 800MHz */ in svs_mt8183_efuse_parsing()
1885 svsb->dvt_fixed = 2; in svs_mt8183_efuse_parsing()
1889 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); in svs_mt8183_efuse_parsing()
1894 ret = svs_get_efuse_data(svsp, "t-calibration-data", in svs_mt8183_efuse_parsing()
1895 &svsp->tefuse, &svsp->tefuse_max); in svs_mt8183_efuse_parsing()
1900 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); in svs_mt8183_efuse_parsing()
1901 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); in svs_mt8183_efuse_parsing()
1903 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1904 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1905 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1906 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1907 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1908 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1910 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0); in svs_mt8183_efuse_parsing()
1911 adc_cali_en_t = svsp->tefuse[0] & BIT(0); in svs_mt8183_efuse_parsing()
1912 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0); in svs_mt8183_efuse_parsing()
1914 ts_id = (svsp->tefuse[1] >> 9) & BIT(0); in svs_mt8183_efuse_parsing()
1918 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); in svs_mt8183_efuse_parsing()
1922 o_slope = 1534 - o_slope * 10; in svs_mt8183_efuse_parsing()
1928 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || in svs_mt8183_efuse_parsing()
1929 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || in svs_mt8183_efuse_parsing()
1930 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || in svs_mt8183_efuse_parsing()
1931 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || in svs_mt8183_efuse_parsing()
1932 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || in svs_mt8183_efuse_parsing()
1933 o_vtsabb < -8 || o_vtsabb > 484 || in svs_mt8183_efuse_parsing()
1935 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); in svs_mt8183_efuse_parsing()
1939 ge = ((adc_ge_t - 512) * 10000) / 4096; in svs_mt8183_efuse_parsing()
1940 oe = (adc_oe_t - 512); in svs_mt8183_efuse_parsing()
1943 format[0] = (o_vtsmcu[0] + 3350 - oe); in svs_mt8183_efuse_parsing()
1944 format[1] = (o_vtsmcu[1] + 3350 - oe); in svs_mt8183_efuse_parsing()
1945 format[2] = (o_vtsmcu[2] + 3350 - oe); in svs_mt8183_efuse_parsing()
1946 format[3] = (o_vtsmcu[3] + 3350 - oe); in svs_mt8183_efuse_parsing()
1947 format[4] = (o_vtsmcu[4] + 3350 - oe); in svs_mt8183_efuse_parsing()
1948 format[5] = (o_vtsabb + 3350 - oe); in svs_mt8183_efuse_parsing()
1956 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
1957 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
1958 svsb->mts = mts; in svs_mt8183_efuse_parsing()
1960 switch (svsb->sw_id) { in svs_mt8183_efuse_parsing()
1974 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); in svs_mt8183_efuse_parsing()
1983 svsb->bts = (temp0 + temp2 - 250) * 4 / 10; in svs_mt8183_efuse_parsing()
1989 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
1990 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
1991 svsb->mode_support &= ~SVSB_MODE_MON; in svs_mt8183_efuse_parsing()
2005 dev_err(svsp->dev, "cannot find %s node\n", node_name); in svs_get_subsys_device()
2006 return ERR_PTR(-ENODEV); in svs_get_subsys_device()
2012 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name); in svs_get_subsys_device()
2013 return ERR_PTR(-ENXIO); in svs_get_subsys_device()
2018 return &pdev->dev; in svs_get_subsys_device()
2031 sup_link = device_link_add(svsp->dev, dev, in svs_add_device_link()
2034 dev_err(svsp->dev, "sup_link is NULL\n"); in svs_add_device_link()
2035 return ERR_PTR(-EINVAL); in svs_add_device_link()
2038 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) in svs_add_device_link()
2039 return ERR_PTR(-EPROBE_DEFER); in svs_add_device_link()
2050 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); in svs_mt8192_platform_probe()
2051 if (IS_ERR(svsp->rst)) in svs_mt8192_platform_probe()
2052 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), in svs_mt8192_platform_probe()
2053 "cannot get svs reset control\n"); in svs_mt8192_platform_probe()
2057 return dev_err_probe(svsp->dev, PTR_ERR(dev), in svs_mt8192_platform_probe()
2060 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8192_platform_probe()
2061 svsb = &svsp->banks[idx]; in svs_mt8192_platform_probe()
2063 if (svsb->type == SVSB_HIGH) in svs_mt8192_platform_probe()
2064 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); in svs_mt8192_platform_probe()
2065 else if (svsb->type == SVSB_LOW) in svs_mt8192_platform_probe()
2066 svsb->opp_dev = svs_get_subsys_device(svsp, "gpu"); in svs_mt8192_platform_probe()
2068 if (IS_ERR(svsb->opp_dev)) in svs_mt8192_platform_probe()
2069 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), in svs_mt8192_platform_probe()
2085 return dev_err_probe(svsp->dev, PTR_ERR(dev), in svs_mt8183_platform_probe()
2088 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_platform_probe()
2089 svsb = &svsp->banks[idx]; in svs_mt8183_platform_probe()
2091 switch (svsb->sw_id) { in svs_mt8183_platform_probe()
2094 svsb->opp_dev = get_cpu_device(svsb->cpu_id); in svs_mt8183_platform_probe()
2097 svsb->opp_dev = svs_add_device_link(svsp, "cci"); in svs_mt8183_platform_probe()
2100 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); in svs_mt8183_platform_probe()
2103 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); in svs_mt8183_platform_probe()
2104 return -EINVAL; in svs_mt8183_platform_probe()
2107 if (IS_ERR(svsb->opp_dev)) in svs_mt8183_platform_probe()
2108 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), in svs_mt8183_platform_probe()
2281 .name = "mt8192-svs",
2290 .name = "mt8183-svs",
2300 .compatible = "mediatek,mt8192-svs",
2301 .data = &svs_mt8192_platform_data,
2303 .compatible = "mediatek,mt8183-svs",
2304 .data = &svs_mt8183_platform_data,
2317 svsp_data = of_device_get_match_data(&pdev->dev); in svs_probe()
2319 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); in svs_probe()
2321 return -ENOMEM; in svs_probe()
2323 svsp->dev = &pdev->dev; in svs_probe()
2324 svsp->banks = svsp_data->banks; in svs_probe()
2325 svsp->regs = svsp_data->regs; in svs_probe()
2326 svsp->bank_max = svsp_data->bank_max; in svs_probe()
2328 ret = svsp_data->probe(svsp); in svs_probe()
2332 ret = svs_get_efuse_data(svsp, "svs-calibration-data", in svs_probe()
2333 &svsp->efuse, &svsp->efuse_max); in svs_probe()
2335 ret = -EPERM; in svs_probe()
2339 if (!svsp_data->efuse_parsing(svsp)) { in svs_probe()
2340 dev_err(svsp->dev, "efuse data parsing failed\n"); in svs_probe()
2341 ret = -EPERM; in svs_probe()
2347 dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); in svs_probe()
2357 svsp->main_clk = devm_clk_get(svsp->dev, "main"); in svs_probe()
2358 if (IS_ERR(svsp->main_clk)) { in svs_probe()
2359 dev_err(svsp->dev, "failed to get clock: %ld\n", in svs_probe()
2360 PTR_ERR(svsp->main_clk)); in svs_probe()
2361 ret = PTR_ERR(svsp->main_clk); in svs_probe()
2365 ret = clk_prepare_enable(svsp->main_clk); in svs_probe()
2367 dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); in svs_probe()
2371 svsp->base = of_iomap(svsp->dev->of_node, 0); in svs_probe()
2372 if (IS_ERR_OR_NULL(svsp->base)) { in svs_probe()
2373 dev_err(svsp->dev, "cannot find svs register base\n"); in svs_probe()
2374 ret = -EINVAL; in svs_probe()
2378 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, in svs_probe()
2379 IRQF_ONESHOT, svsp_data->name, svsp); in svs_probe()
2381 dev_err(svsp->dev, "register irq(%d) failed: %d\n", in svs_probe()
2388 dev_err(svsp->dev, "svs start fail: %d\n", ret); in svs_probe()
2395 dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); in svs_probe()
2403 iounmap(svsp->base); in svs_probe()
2406 clk_disable_unprepare(svsp->main_clk); in svs_probe()
2409 if (!IS_ERR_OR_NULL(svsp->tefuse)) in svs_probe()
2410 kfree(svsp->tefuse); in svs_probe()
2413 if (!IS_ERR_OR_NULL(svsp->efuse)) in svs_probe()
2414 kfree(svsp->efuse); in svs_probe()
2424 .name = "mtk-svs",
2433 MODULE_DESCRIPTION("MediaTek SVS driver");