Lines Matching +full:drv +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
19 #define SPM_CTL_INDEX 0x7f
21 #define SPM_CTL_EN BIT(0)
40 [SPM_REG_AVS_CTL] = 0x904,
41 [SPM_REG_AVS_LIMIT] = 0x908,
46 .avs_ctl = 0x1010031,
47 .avs_limit = 0x4580458,
52 .avs_ctl = 0x101c031,
53 .avs_limit = 0x4580458,
58 .avs_ctl = 0x1010031,
59 .avs_limit = 0x4700470,
64 .avs_ctl = 0x1010031,
65 .avs_limit = 0x4200420,
69 [SPM_REG_CFG] = 0x08,
70 [SPM_REG_SPM_CTL] = 0x30,
71 [SPM_REG_DLY] = 0x34,
72 [SPM_REG_SEQ_ENTRY] = 0x400,
78 .spm_cfg = 0x1,
79 .spm_dly = 0x3C102800,
80 .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
81 0x5B, 0x60, 0x03, 0x60, 0x76, 0x76, 0x0B, 0x94, 0x5B, 0x80,
82 0x10, 0x26, 0x30, 0x0F },
83 .start_index[PM_SLEEP_MODE_STBY] = 0,
90 .spm_cfg = 0x1,
91 .spm_dly = 0x3C102800,
92 .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
93 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
94 0x80, 0x10, 0x26, 0x30, 0x0F },
95 .start_index[PM_SLEEP_MODE_STBY] = 0,
101 .spm_cfg = 0x1,
102 .spm_dly = 0x3C102800,
103 .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x50, 0x1B, 0x10, 0x80,
104 0x30, 0x90, 0x5B, 0x60, 0x50, 0x03, 0x60, 0x76, 0x76, 0x0B,
105 0x50, 0x1B, 0x94, 0x5B, 0x80, 0x10, 0x26, 0x30, 0x50, 0x0F },
106 .start_index[PM_SLEEP_MODE_STBY] = 0,
111 [SPM_REG_CFG] = 0x08,
112 [SPM_REG_SPM_CTL] = 0x30,
113 [SPM_REG_DLY] = 0x34,
114 [SPM_REG_PMIC_DATA_0] = 0x40,
115 [SPM_REG_PMIC_DATA_1] = 0x44,
121 .spm_cfg = 0x14,
122 .spm_dly = 0x3c11840a,
123 .pmic_data[0] = 0x03030080,
124 .pmic_data[1] = 0x00030000,
125 .start_index[PM_SLEEP_MODE_STBY] = 0,
131 .spm_cfg = 0x14,
132 .spm_dly = 0x3c102800,
133 .pmic_data[0] = 0x03030080,
134 .pmic_data[1] = 0x00030000,
135 .start_index[PM_SLEEP_MODE_STBY] = 0,
140 [SPM_REG_CFG] = 0x08,
141 [SPM_REG_SPM_CTL] = 0x30,
142 [SPM_REG_DLY] = 0x34,
143 [SPM_REG_SEQ_ENTRY] = 0x80,
149 .spm_cfg = 0x1,
150 .spm_dly = 0x3C102800,
151 .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
152 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
153 0x0F },
154 .start_index[PM_SLEEP_MODE_STBY] = 0,
161 .spm_cfg = 0x0,
162 .spm_dly = 0x3C102800,
163 .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
164 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
165 0x80, 0x10, 0x26, 0x30, 0x0F },
166 .start_index[PM_SLEEP_MODE_STBY] = 0,
171 [SPM_REG_CFG] = 0x08,
172 [SPM_REG_SPM_CTL] = 0x20,
173 [SPM_REG_PMIC_DLY] = 0x24,
174 [SPM_REG_PMIC_DATA_0] = 0x28,
175 [SPM_REG_PMIC_DATA_1] = 0x2C,
176 [SPM_REG_SEQ_ENTRY] = 0x80,
182 .spm_cfg = 0x1F,
183 .pmic_dly = 0x02020004,
184 .pmic_data[0] = 0x0084009C,
185 .pmic_data[1] = 0x00A4001C,
186 .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
187 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
188 .start_index[PM_SLEEP_MODE_STBY] = 0,
192 static inline void spm_register_write(struct spm_driver_data *drv, in spm_register_write() argument
195 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
196 writel_relaxed(val, drv->reg_base + in spm_register_write()
197 drv->reg_data->reg_offset[reg]); in spm_register_write()
201 static inline void spm_register_write_sync(struct spm_driver_data *drv, in spm_register_write_sync() argument
206 if (!drv->reg_data->reg_offset[reg]) in spm_register_write_sync()
210 writel_relaxed(val, drv->reg_base + in spm_register_write_sync()
211 drv->reg_data->reg_offset[reg]); in spm_register_write_sync()
212 ret = readl_relaxed(drv->reg_base + in spm_register_write_sync()
213 drv->reg_data->reg_offset[reg]); in spm_register_write_sync()
220 static inline u32 spm_register_read(struct spm_driver_data *drv, in spm_register_read() argument
223 return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); in spm_register_read()
226 void spm_set_low_power_mode(struct spm_driver_data *drv, in spm_set_low_power_mode() argument
232 start_index = drv->reg_data->start_index[mode]; in spm_set_low_power_mode()
234 ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL); in spm_set_low_power_mode()
238 spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); in spm_set_low_power_mode()
242 { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
244 { .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
246 { .compatible = "qcom,msm8226-saw2-v2.1-cpu",
248 { .compatible = "qcom,msm8909-saw2-v3.0-cpu",
250 { .compatible = "qcom,msm8916-saw2-v3.0-cpu",
252 { .compatible = "qcom,msm8939-saw2-v3.0-cpu",
254 { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
256 { .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
258 { .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
260 { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
262 { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
264 { .compatible = "qcom,apq8084-saw2-v2.1-cpu",
266 { .compatible = "qcom,apq8064-saw2-v1.1-cpu",
275 struct spm_driver_data *drv; in spm_dev_probe() local
278 drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); in spm_dev_probe()
279 if (!drv) in spm_dev_probe()
280 return -ENOMEM; in spm_dev_probe()
282 drv->reg_base = devm_platform_ioremap_resource(pdev, 0); in spm_dev_probe()
283 if (IS_ERR(drv->reg_base)) in spm_dev_probe()
284 return PTR_ERR(drv->reg_base); in spm_dev_probe()
286 match_id = of_match_node(spm_match_table, pdev->dev.of_node); in spm_dev_probe()
288 return -ENODEV; in spm_dev_probe()
290 drv->reg_data = match_id->data; in spm_dev_probe()
291 platform_set_drvdata(pdev, drv); in spm_dev_probe()
294 addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; in spm_dev_probe()
295 __iowrite32_copy(addr, drv->reg_data->seq, in spm_dev_probe()
296 ARRAY_SIZE(drv->reg_data->seq) / 4); in spm_dev_probe()
304 spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl); in spm_dev_probe()
305 spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit); in spm_dev_probe()
306 spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg); in spm_dev_probe()
307 spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly); in spm_dev_probe()
308 spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly); in spm_dev_probe()
309 spm_register_write(drv, SPM_REG_PMIC_DATA_0, in spm_dev_probe()
310 drv->reg_data->pmic_data[0]); in spm_dev_probe()
311 spm_register_write(drv, SPM_REG_PMIC_DATA_1, in spm_dev_probe()
312 drv->reg_data->pmic_data[1]); in spm_dev_probe()
315 if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) in spm_dev_probe()
316 spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); in spm_dev_probe()
318 return 0; in spm_dev_probe()