Lines Matching +full:rx +full:- +full:clk +full:- +full:tap +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk.h>
7 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
182 struct clk *clk; member
235 return readl(tqspi->base + offset); in tegra_qspi_readl()
240 writel(value, tqspi->base + offset); in tegra_qspi_writel()
244 readl(tqspi->base + QSPI_COMMAND1); in tegra_qspi_writel()
271 unsigned int remain_len = t->len - tqspi->cur_pos; in tegra_qspi_calculate_curr_xfer_param()
272 unsigned int bits_per_word = t->bits_per_word; in tegra_qspi_calculate_curr_xfer_param()
274 tqspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_qspi_calculate_curr_xfer_param()
284 bits_per_word == 32) && t->len > 3) { in tegra_qspi_calculate_curr_xfer_param()
285 tqspi->is_packed = true; in tegra_qspi_calculate_curr_xfer_param()
286 tqspi->words_per_32bit = 32 / bits_per_word; in tegra_qspi_calculate_curr_xfer_param()
288 tqspi->is_packed = false; in tegra_qspi_calculate_curr_xfer_param()
289 tqspi->words_per_32bit = 1; in tegra_qspi_calculate_curr_xfer_param()
292 if (tqspi->is_packed) { in tegra_qspi_calculate_curr_xfer_param()
293 max_len = min(remain_len, tqspi->max_buf_size); in tegra_qspi_calculate_curr_xfer_param()
294 tqspi->curr_dma_words = max_len / tqspi->bytes_per_word; in tegra_qspi_calculate_curr_xfer_param()
297 max_word = (remain_len - 1) / tqspi->bytes_per_word + 1; in tegra_qspi_calculate_curr_xfer_param()
298 max_word = min(max_word, tqspi->max_buf_size / 4); in tegra_qspi_calculate_curr_xfer_param()
299 tqspi->curr_dma_words = max_word; in tegra_qspi_calculate_curr_xfer_param()
311 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
317 if (tqspi->is_packed) { in tegra_qspi_fill_tx_fifo_from_client_txbuf()
318 fifo_words_left = tx_empty_count * tqspi->words_per_32bit; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
319 written_words = min(fifo_words_left, tqspi->curr_dma_words); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
320 len = written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
325 for (i = 0; (i < 4) && len; i++, len--) in tegra_qspi_fill_tx_fifo_from_client_txbuf()
330 tqspi->cur_tx_pos += written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
333 u8 bytes_per_word = tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
335 max_n_32bit = min(tqspi->curr_dma_words, tx_empty_count); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
337 len = written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
338 if (len > t->len - tqspi->cur_pos) in tegra_qspi_fill_tx_fifo_from_client_txbuf()
339 len = t->len - tqspi->cur_pos; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
344 for (i = 0; len && (i < min(4, bytes_per_word)); i++, len--) in tegra_qspi_fill_tx_fifo_from_client_txbuf()
349 tqspi->cur_tx_pos += write_bytes; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
358 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
365 if (tqspi->is_packed) { in tegra_qspi_read_rx_fifo_to_client_rxbuf()
366 len = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
370 for (i = 0; len && (i < 4); i++, len--) in tegra_qspi_read_rx_fifo_to_client_rxbuf()
374 read_words += tqspi->curr_dma_words; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
375 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
377 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
378 u8 bytes_per_word = tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
382 if (len > t->len - tqspi->cur_pos) in tegra_qspi_read_rx_fifo_to_client_rxbuf()
383 len = t->len - tqspi->cur_pos; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
388 for (i = 0; len && (i < bytes_per_word); i++, len--) in tegra_qspi_read_rx_fifo_to_client_rxbuf()
393 tqspi->cur_rx_pos += read_bytes; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
402 dma_sync_single_for_cpu(tqspi->dev, tqspi->tx_dma_phys, in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
403 tqspi->dma_buf_size, DMA_TO_DEVICE); in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
413 if (tqspi->is_packed) { in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
414 tqspi->cur_tx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
416 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
423 consume = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
424 if (consume > t->len - tqspi->cur_pos) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
425 consume = t->len - tqspi->cur_pos; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
427 for (count = 0; count < tqspi->curr_dma_words; count++) { in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
430 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
432 tqspi->tx_dma_buf[count] = x; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
435 tqspi->cur_tx_pos += write_bytes; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
438 dma_sync_single_for_device(tqspi->dev, tqspi->tx_dma_phys, in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
439 tqspi->dma_buf_size, DMA_TO_DEVICE); in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
445 dma_sync_single_for_cpu(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
446 tqspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
448 if (tqspi->is_packed) { in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
449 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
451 unsigned char *rx_buf = t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
452 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
460 consume = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
461 if (consume > t->len - tqspi->cur_pos) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
462 consume = t->len - tqspi->cur_pos; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
464 for (count = 0; count < tqspi->curr_dma_words; count++) { in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
465 u32 x = tqspi->rx_dma_buf[count] & rx_mask; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
467 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
471 tqspi->cur_rx_pos += read_bytes; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
474 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
475 tqspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
489 reinit_completion(&tqspi->tx_dma_complete); in tegra_qspi_start_tx_dma()
491 if (tqspi->is_packed) in tegra_qspi_start_tx_dma()
492 tx_dma_phys = t->tx_dma; in tegra_qspi_start_tx_dma()
494 tx_dma_phys = tqspi->tx_dma_phys; in tegra_qspi_start_tx_dma()
496 tqspi->tx_dma_desc = dmaengine_prep_slave_single(tqspi->tx_dma_chan, tx_dma_phys, in tegra_qspi_start_tx_dma()
500 if (!tqspi->tx_dma_desc) { in tegra_qspi_start_tx_dma()
501 dev_err(tqspi->dev, "Unable to get TX descriptor\n"); in tegra_qspi_start_tx_dma()
502 return -EIO; in tegra_qspi_start_tx_dma()
505 tqspi->tx_dma_desc->callback = tegra_qspi_dma_complete; in tegra_qspi_start_tx_dma()
506 tqspi->tx_dma_desc->callback_param = &tqspi->tx_dma_complete; in tegra_qspi_start_tx_dma()
507 dmaengine_submit(tqspi->tx_dma_desc); in tegra_qspi_start_tx_dma()
508 dma_async_issue_pending(tqspi->tx_dma_chan); in tegra_qspi_start_tx_dma()
517 reinit_completion(&tqspi->rx_dma_complete); in tegra_qspi_start_rx_dma()
519 if (tqspi->is_packed) in tegra_qspi_start_rx_dma()
520 rx_dma_phys = t->rx_dma; in tegra_qspi_start_rx_dma()
522 rx_dma_phys = tqspi->rx_dma_phys; in tegra_qspi_start_rx_dma()
524 tqspi->rx_dma_desc = dmaengine_prep_slave_single(tqspi->rx_dma_chan, rx_dma_phys, in tegra_qspi_start_rx_dma()
528 if (!tqspi->rx_dma_desc) { in tegra_qspi_start_rx_dma()
529 dev_err(tqspi->dev, "Unable to get RX descriptor\n"); in tegra_qspi_start_rx_dma()
530 return -EIO; in tegra_qspi_start_rx_dma()
533 tqspi->rx_dma_desc->callback = tegra_qspi_dma_complete; in tegra_qspi_start_rx_dma()
534 tqspi->rx_dma_desc->callback_param = &tqspi->rx_dma_complete; in tegra_qspi_start_rx_dma()
535 dmaengine_submit(tqspi->rx_dma_desc); in tegra_qspi_start_rx_dma()
536 dma_async_issue_pending(tqspi->rx_dma_chan); in tegra_qspi_start_rx_dma()
543 void __iomem *addr = tqspi->base + QSPI_FIFO_STATUS; in tegra_qspi_flush_fifos()
574 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_dma_map_xfer()
575 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_dma_map_xfer()
578 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_dma_map_xfer()
580 if (t->tx_buf) { in tegra_qspi_dma_map_xfer()
581 t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEVICE); in tegra_qspi_dma_map_xfer()
582 if (dma_mapping_error(tqspi->dev, t->tx_dma)) in tegra_qspi_dma_map_xfer()
583 return -ENOMEM; in tegra_qspi_dma_map_xfer()
586 if (t->rx_buf) { in tegra_qspi_dma_map_xfer()
587 t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_DEVICE); in tegra_qspi_dma_map_xfer()
588 if (dma_mapping_error(tqspi->dev, t->rx_dma)) { in tegra_qspi_dma_map_xfer()
589 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); in tegra_qspi_dma_map_xfer()
590 return -ENOMEM; in tegra_qspi_dma_map_xfer()
601 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_dma_unmap_xfer()
603 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); in tegra_qspi_dma_unmap_xfer()
604 dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); in tegra_qspi_dma_unmap_xfer()
615 if (tqspi->is_packed) { in tegra_qspi_start_dma_based_transfer()
621 val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1); in tegra_qspi_start_dma_based_transfer()
626 if (tqspi->is_packed) in tegra_qspi_start_dma_based_transfer()
627 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_start_dma_based_transfer()
629 len = tqspi->curr_dma_words * 4; in tegra_qspi_start_dma_based_transfer()
645 tqspi->dma_control_reg = val; in tegra_qspi_start_dma_based_transfer()
648 if (tqspi->cur_direction & DATA_DIR_TX) { in tegra_qspi_start_dma_based_transfer()
649 dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; in tegra_qspi_start_dma_based_transfer()
652 ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); in tegra_qspi_start_dma_based_transfer()
654 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
661 dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
666 if (tqspi->cur_direction & DATA_DIR_RX) { in tegra_qspi_start_dma_based_transfer()
667 dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; in tegra_qspi_start_dma_based_transfer()
670 ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); in tegra_qspi_start_dma_based_transfer()
672 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
676 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_start_dma_based_transfer()
677 tqspi->dma_buf_size, in tegra_qspi_start_dma_based_transfer()
682 dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
683 if (tqspi->cur_direction & DATA_DIR_TX) in tegra_qspi_start_dma_based_transfer()
684 dmaengine_terminate_all(tqspi->tx_dma_chan); in tegra_qspi_start_dma_based_transfer()
689 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_start_dma_based_transfer()
691 tqspi->is_curr_dma_xfer = true; in tegra_qspi_start_dma_based_transfer()
692 tqspi->dma_control_reg = val; in tegra_qspi_start_dma_based_transfer()
704 if (qspi->cur_direction & DATA_DIR_TX) in tegra_qspi_start_cpu_based_transfer()
707 cur_words = qspi->curr_dma_words; in tegra_qspi_start_cpu_based_transfer()
709 val = QSPI_DMA_BLK_SET(cur_words - 1); in tegra_qspi_start_cpu_based_transfer()
714 qspi->is_curr_dma_xfer = false; in tegra_qspi_start_cpu_based_transfer()
715 val = qspi->command1_reg; in tegra_qspi_start_cpu_based_transfer()
724 if (!tqspi->soc_data->has_dma) in tegra_qspi_deinit_dma()
727 if (tqspi->tx_dma_buf) { in tegra_qspi_deinit_dma()
728 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, in tegra_qspi_deinit_dma()
729 tqspi->tx_dma_buf, tqspi->tx_dma_phys); in tegra_qspi_deinit_dma()
730 tqspi->tx_dma_buf = NULL; in tegra_qspi_deinit_dma()
733 if (tqspi->tx_dma_chan) { in tegra_qspi_deinit_dma()
734 dma_release_channel(tqspi->tx_dma_chan); in tegra_qspi_deinit_dma()
735 tqspi->tx_dma_chan = NULL; in tegra_qspi_deinit_dma()
738 if (tqspi->rx_dma_buf) { in tegra_qspi_deinit_dma()
739 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, in tegra_qspi_deinit_dma()
740 tqspi->rx_dma_buf, tqspi->rx_dma_phys); in tegra_qspi_deinit_dma()
741 tqspi->rx_dma_buf = NULL; in tegra_qspi_deinit_dma()
744 if (tqspi->rx_dma_chan) { in tegra_qspi_deinit_dma()
745 dma_release_channel(tqspi->rx_dma_chan); in tegra_qspi_deinit_dma()
746 tqspi->rx_dma_chan = NULL; in tegra_qspi_deinit_dma()
757 if (!tqspi->soc_data->has_dma) in tegra_qspi_init_dma()
760 dma_chan = dma_request_chan(tqspi->dev, "rx"); in tegra_qspi_init_dma()
766 tqspi->rx_dma_chan = dma_chan; in tegra_qspi_init_dma()
768 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); in tegra_qspi_init_dma()
770 err = -ENOMEM; in tegra_qspi_init_dma()
774 tqspi->rx_dma_buf = dma_buf; in tegra_qspi_init_dma()
775 tqspi->rx_dma_phys = dma_phys; in tegra_qspi_init_dma()
777 dma_chan = dma_request_chan(tqspi->dev, "tx"); in tegra_qspi_init_dma()
783 tqspi->tx_dma_chan = dma_chan; in tegra_qspi_init_dma()
785 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); in tegra_qspi_init_dma()
787 err = -ENOMEM; in tegra_qspi_init_dma()
791 tqspi->tx_dma_buf = dma_buf; in tegra_qspi_init_dma()
792 tqspi->tx_dma_phys = dma_phys; in tegra_qspi_init_dma()
793 tqspi->use_dma = true; in tegra_qspi_init_dma()
800 if (err != -EPROBE_DEFER) { in tegra_qspi_init_dma()
801 dev_err(tqspi->dev, "cannot use DMA: %d\n", err); in tegra_qspi_init_dma()
802 dev_err(tqspi->dev, "falling back to PIO\n"); in tegra_qspi_init_dma()
812 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_setup_transfer_one()
813 struct tegra_qspi_client_data *cdata = spi->controller_data; in tegra_qspi_setup_transfer_one()
814 u32 command1, command2, speed = t->speed_hz; in tegra_qspi_setup_transfer_one()
815 u8 bits_per_word = t->bits_per_word; in tegra_qspi_setup_transfer_one()
819 if (!has_acpi_companion(tqspi->dev) && speed != tqspi->cur_speed) { in tegra_qspi_setup_transfer_one()
820 clk_set_rate(tqspi->clk, speed); in tegra_qspi_setup_transfer_one()
821 tqspi->cur_speed = speed; in tegra_qspi_setup_transfer_one()
824 tqspi->cur_pos = 0; in tegra_qspi_setup_transfer_one()
825 tqspi->cur_rx_pos = 0; in tegra_qspi_setup_transfer_one()
826 tqspi->cur_tx_pos = 0; in tegra_qspi_setup_transfer_one()
827 tqspi->curr_xfer = t; in tegra_qspi_setup_transfer_one()
832 command1 = tqspi->def_command1_reg; in tegra_qspi_setup_transfer_one()
834 command1 |= QSPI_BIT_LENGTH(bits_per_word - 1); in tegra_qspi_setup_transfer_one()
837 req_mode = spi->mode & 0x3; in tegra_qspi_setup_transfer_one()
843 if (spi->mode & SPI_CS_HIGH) in tegra_qspi_setup_transfer_one()
849 if (cdata && cdata->tx_clk_tap_delay) in tegra_qspi_setup_transfer_one()
850 tx_tap = cdata->tx_clk_tap_delay; in tegra_qspi_setup_transfer_one()
852 if (cdata && cdata->rx_clk_tap_delay) in tegra_qspi_setup_transfer_one()
853 rx_tap = cdata->rx_clk_tap_delay; in tegra_qspi_setup_transfer_one()
856 if (command2 != tqspi->def_command2_reg) in tegra_qspi_setup_transfer_one()
860 command1 = tqspi->command1_reg; in tegra_qspi_setup_transfer_one()
862 command1 |= QSPI_BIT_LENGTH(bits_per_word - 1); in tegra_qspi_setup_transfer_one()
873 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_start_transfer_one()
881 if (tqspi->is_packed) in tegra_qspi_start_transfer_one()
885 tqspi->cur_direction = 0; in tegra_qspi_start_transfer_one()
888 if (t->rx_buf) { in tegra_qspi_start_transfer_one()
890 tqspi->cur_direction |= DATA_DIR_RX; in tegra_qspi_start_transfer_one()
891 bus_width = t->rx_nbits; in tegra_qspi_start_transfer_one()
894 if (t->tx_buf) { in tegra_qspi_start_transfer_one()
896 tqspi->cur_direction |= DATA_DIR_TX; in tegra_qspi_start_transfer_one()
897 bus_width = t->tx_nbits; in tegra_qspi_start_transfer_one()
909 tqspi->command1_reg = command1; in tegra_qspi_start_transfer_one()
911 tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG); in tegra_qspi_start_transfer_one()
917 if (tqspi->use_dma && total_fifo_words > QSPI_FIFO_DEPTH) in tegra_qspi_start_transfer_one()
928 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_parse_cdata_dt()
930 cdata = devm_kzalloc(tqspi->dev, sizeof(*cdata), GFP_KERNEL); in tegra_qspi_parse_cdata_dt()
934 device_property_read_u32(&spi->dev, "nvidia,tx-clk-tap-delay", in tegra_qspi_parse_cdata_dt()
935 &cdata->tx_clk_tap_delay); in tegra_qspi_parse_cdata_dt()
936 device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay", in tegra_qspi_parse_cdata_dt()
937 &cdata->rx_clk_tap_delay); in tegra_qspi_parse_cdata_dt()
944 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_setup()
945 struct tegra_qspi_client_data *cdata = spi->controller_data; in tegra_qspi_setup()
950 ret = pm_runtime_resume_and_get(tqspi->dev); in tegra_qspi_setup()
952 dev_err(tqspi->dev, "failed to get runtime PM: %d\n", ret); in tegra_qspi_setup()
958 spi->controller_data = cdata; in tegra_qspi_setup()
960 spin_lock_irqsave(&tqspi->lock, flags); in tegra_qspi_setup()
963 val = tqspi->def_command1_reg; in tegra_qspi_setup()
965 if (spi->mode & SPI_CS_HIGH) in tegra_qspi_setup()
970 tqspi->def_command1_reg = val; in tegra_qspi_setup()
971 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_setup()
973 spin_unlock_irqrestore(&tqspi->lock, flags); in tegra_qspi_setup()
975 pm_runtime_put(tqspi->dev); in tegra_qspi_setup()
982 dev_dbg(tqspi->dev, "============ QSPI REGISTER DUMP ============\n"); in tegra_qspi_dump_regs()
983 dev_dbg(tqspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", in tegra_qspi_dump_regs()
986 dev_dbg(tqspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", in tegra_qspi_dump_regs()
989 dev_dbg(tqspi->dev, "INTR_MASK: 0x%08x | MISC: 0x%08x\n", in tegra_qspi_dump_regs()
992 dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", in tegra_qspi_dump_regs()
999 dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->status_reg); in tegra_qspi_handle_error()
1002 if (device_reset(tqspi->dev) < 0) in tegra_qspi_handle_error()
1003 dev_warn_once(tqspi->dev, "device reset failed\n"); in tegra_qspi_handle_error()
1008 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_transfer_end()
1009 int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1; in tegra_qspi_transfer_end()
1012 tqspi->command1_reg |= QSPI_CS_SW_VAL; in tegra_qspi_transfer_end()
1014 tqspi->command1_reg &= ~QSPI_CS_SW_VAL; in tegra_qspi_transfer_end()
1015 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_transfer_end()
1016 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_transfer_end()
1030 cmd_config |= QSPI_COMMAND_SIZE_SET((len * 8) - 1); in tegra_qspi_cmd_config()
1045 addr_config |= QSPI_ADDRESS_SIZE_SET((len * 8) - 1); in tegra_qspi_addr_config()
1055 struct spi_device *spi = msg->spi; in tegra_qspi_combined_seq_xfer()
1065 if (spi->mode & SPI_TPM_HW_FLOW) { in tegra_qspi_combined_seq_xfer()
1066 if (tqspi->soc_data->supports_tpm) in tegra_qspi_combined_seq_xfer()
1069 return -EIO; in tegra_qspi_combined_seq_xfer()
1074 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in tegra_qspi_combined_seq_xfer()
1078 cmd_config = tegra_qspi_cmd_config(false, xfer->tx_nbits, in tegra_qspi_combined_seq_xfer()
1079 xfer->len); in tegra_qspi_combined_seq_xfer()
1080 cmd_value = *((const u8 *)(xfer->tx_buf)); in tegra_qspi_combined_seq_xfer()
1084 addr_config = tegra_qspi_addr_config(false, xfer->tx_nbits, in tegra_qspi_combined_seq_xfer()
1085 xfer->len); in tegra_qspi_combined_seq_xfer()
1086 address_value = *((const u32 *)(xfer->tx_buf)); in tegra_qspi_combined_seq_xfer()
1099 reinit_completion(&tqspi->xfer_completion); in tegra_qspi_combined_seq_xfer()
1106 dev_err(tqspi->dev, "Failed to start transfer-one: %d\n", in tegra_qspi_combined_seq_xfer()
1113 (&tqspi->xfer_completion, in tegra_qspi_combined_seq_xfer()
1117 dev_err_ratelimited(tqspi->dev, in tegra_qspi_combined_seq_xfer()
1119 if (tqspi->is_curr_dma_xfer && in tegra_qspi_combined_seq_xfer()
1120 (tqspi->cur_direction & DATA_DIR_TX)) in tegra_qspi_combined_seq_xfer()
1122 (tqspi->tx_dma_chan); in tegra_qspi_combined_seq_xfer()
1124 if (tqspi->is_curr_dma_xfer && in tegra_qspi_combined_seq_xfer()
1125 (tqspi->cur_direction & DATA_DIR_RX)) in tegra_qspi_combined_seq_xfer()
1127 (tqspi->rx_dma_chan); in tegra_qspi_combined_seq_xfer()
1130 if (!tqspi->is_curr_dma_xfer) { in tegra_qspi_combined_seq_xfer()
1148 if (device_reset(tqspi->dev) < 0) in tegra_qspi_combined_seq_xfer()
1149 dev_warn_once(tqspi->dev, in tegra_qspi_combined_seq_xfer()
1151 ret = -EIO; in tegra_qspi_combined_seq_xfer()
1155 if (tqspi->tx_status || tqspi->rx_status) { in tegra_qspi_combined_seq_xfer()
1156 dev_err(tqspi->dev, "QSPI Transfer failed\n"); in tegra_qspi_combined_seq_xfer()
1157 tqspi->tx_status = 0; in tegra_qspi_combined_seq_xfer()
1158 tqspi->rx_status = 0; in tegra_qspi_combined_seq_xfer()
1159 ret = -EIO; in tegra_qspi_combined_seq_xfer()
1164 ret = -EINVAL; in tegra_qspi_combined_seq_xfer()
1167 msg->actual_length += xfer->len; in tegra_qspi_combined_seq_xfer()
1168 if (!xfer->cs_change && transfer_phase == DATA_TRANSFER) { in tegra_qspi_combined_seq_xfer()
1177 msg->status = ret; in tegra_qspi_combined_seq_xfer()
1185 struct spi_device *spi = msg->spi; in tegra_qspi_non_combined_seq_xfer()
1190 msg->status = 0; in tegra_qspi_non_combined_seq_xfer()
1191 msg->actual_length = 0; in tegra_qspi_non_combined_seq_xfer()
1192 tqspi->tx_status = 0; in tegra_qspi_non_combined_seq_xfer()
1193 tqspi->rx_status = 0; in tegra_qspi_non_combined_seq_xfer()
1198 if (tqspi->soc_data->supports_tpm) in tegra_qspi_non_combined_seq_xfer()
1201 list_for_each_entry(transfer, &msg->transfers, transfer_list) { in tegra_qspi_non_combined_seq_xfer()
1206 tqspi->dummy_cycles = 0; in tegra_qspi_non_combined_seq_xfer()
1213 if (!list_is_last(&xfer->transfer_list, &msg->transfers)) { in tegra_qspi_non_combined_seq_xfer()
1217 if (next_xfer->dummy_data) { in tegra_qspi_non_combined_seq_xfer()
1218 u32 dummy_cycles = next_xfer->len * 8 / next_xfer->tx_nbits; in tegra_qspi_non_combined_seq_xfer()
1221 tqspi->dummy_cycles = dummy_cycles; in tegra_qspi_non_combined_seq_xfer()
1222 dummy_bytes = next_xfer->len; in tegra_qspi_non_combined_seq_xfer()
1228 reinit_completion(&tqspi->xfer_completion); in tegra_qspi_non_combined_seq_xfer()
1234 dev_err(tqspi->dev, "failed to start transfer: %d\n", ret); in tegra_qspi_non_combined_seq_xfer()
1238 ret = wait_for_completion_timeout(&tqspi->xfer_completion, in tegra_qspi_non_combined_seq_xfer()
1241 dev_err(tqspi->dev, "transfer timeout\n"); in tegra_qspi_non_combined_seq_xfer()
1242 if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX)) in tegra_qspi_non_combined_seq_xfer()
1243 dmaengine_terminate_all(tqspi->tx_dma_chan); in tegra_qspi_non_combined_seq_xfer()
1244 if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX)) in tegra_qspi_non_combined_seq_xfer()
1245 dmaengine_terminate_all(tqspi->rx_dma_chan); in tegra_qspi_non_combined_seq_xfer()
1247 ret = -EIO; in tegra_qspi_non_combined_seq_xfer()
1251 if (tqspi->tx_status || tqspi->rx_status) { in tegra_qspi_non_combined_seq_xfer()
1253 ret = -EIO; in tegra_qspi_non_combined_seq_xfer()
1257 msg->actual_length += xfer->len + dummy_bytes; in tegra_qspi_non_combined_seq_xfer()
1266 if (list_is_last(&xfer->transfer_list, &msg->transfers)) { in tegra_qspi_non_combined_seq_xfer()
1267 /* de-activate CS after last transfer only when cs_change is not set */ in tegra_qspi_non_combined_seq_xfer()
1268 if (!xfer->cs_change) { in tegra_qspi_non_combined_seq_xfer()
1272 } else if (xfer->cs_change) { in tegra_qspi_non_combined_seq_xfer()
1273 /* de-activated CS between the transfers only when cs_change is set */ in tegra_qspi_non_combined_seq_xfer()
1281 msg->status = ret; in tegra_qspi_non_combined_seq_xfer()
1292 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in tegra_qspi_validate_cmb_seq()
1295 if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3) in tegra_qspi_validate_cmb_seq()
1297 xfer = list_first_entry(&msg->transfers, typeof(*xfer), in tegra_qspi_validate_cmb_seq()
1299 if (xfer->len > 2) in tegra_qspi_validate_cmb_seq()
1302 if (xfer->len > 4 || xfer->len < 3) in tegra_qspi_validate_cmb_seq()
1305 if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) in tegra_qspi_validate_cmb_seq()
1329 struct spi_transfer *t = tqspi->curr_xfer; in handle_cpu_based_xfer()
1332 spin_lock_irqsave(&tqspi->lock, flags); in handle_cpu_based_xfer()
1334 if (tqspi->tx_status || tqspi->rx_status) { in handle_cpu_based_xfer()
1336 complete(&tqspi->xfer_completion); in handle_cpu_based_xfer()
1340 if (tqspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
1343 if (tqspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
1344 tqspi->cur_pos = tqspi->cur_tx_pos; in handle_cpu_based_xfer()
1346 tqspi->cur_pos = tqspi->cur_rx_pos; in handle_cpu_based_xfer()
1348 if (tqspi->cur_pos == t->len) { in handle_cpu_based_xfer()
1349 complete(&tqspi->xfer_completion); in handle_cpu_based_xfer()
1356 spin_unlock_irqrestore(&tqspi->lock, flags); in handle_cpu_based_xfer()
1362 struct spi_transfer *t = tqspi->curr_xfer; in handle_dma_based_xfer()
1368 if (tqspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
1369 if (tqspi->tx_status) { in handle_dma_based_xfer()
1370 dmaengine_terminate_all(tqspi->tx_dma_chan); in handle_dma_based_xfer()
1374 &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1376 dmaengine_terminate_all(tqspi->tx_dma_chan); in handle_dma_based_xfer()
1377 dev_err(tqspi->dev, "failed TX DMA transfer\n"); in handle_dma_based_xfer()
1383 if (tqspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
1384 if (tqspi->rx_status) { in handle_dma_based_xfer()
1385 dmaengine_terminate_all(tqspi->rx_dma_chan); in handle_dma_based_xfer()
1389 &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1391 dmaengine_terminate_all(tqspi->rx_dma_chan); in handle_dma_based_xfer()
1392 dev_err(tqspi->dev, "failed RX DMA transfer\n"); in handle_dma_based_xfer()
1398 spin_lock_irqsave(&tqspi->lock, flags); in handle_dma_based_xfer()
1403 complete(&tqspi->xfer_completion); in handle_dma_based_xfer()
1407 if (tqspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
1410 if (tqspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
1411 tqspi->cur_pos = tqspi->cur_tx_pos; in handle_dma_based_xfer()
1413 tqspi->cur_pos = tqspi->cur_rx_pos; in handle_dma_based_xfer()
1415 if (tqspi->cur_pos == t->len) { in handle_dma_based_xfer()
1417 complete(&tqspi->xfer_completion); in handle_dma_based_xfer()
1431 spin_unlock_irqrestore(&tqspi->lock, flags); in handle_dma_based_xfer()
1439 tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_isr_thread()
1441 if (tqspi->cur_direction & DATA_DIR_TX) in tegra_qspi_isr_thread()
1442 tqspi->tx_status = tqspi->status_reg & (QSPI_TX_FIFO_UNF | QSPI_TX_FIFO_OVF); in tegra_qspi_isr_thread()
1444 if (tqspi->cur_direction & DATA_DIR_RX) in tegra_qspi_isr_thread()
1445 tqspi->rx_status = tqspi->status_reg & (QSPI_RX_FIFO_OVF | QSPI_RX_FIFO_UNF); in tegra_qspi_isr_thread()
1449 if (!tqspi->is_curr_dma_xfer) in tegra_qspi_isr_thread()
1485 .compatible = "nvidia,tegra210-qspi",
1488 .compatible = "nvidia,tegra186-qspi",
1491 .compatible = "nvidia,tegra194-qspi",
1494 .compatible = "nvidia,tegra234-qspi",
1497 .compatible = "nvidia,tegra241-qspi",
1534 master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi)); in tegra_qspi_probe()
1536 return -ENOMEM; in tegra_qspi_probe()
1541 master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH | in tegra_qspi_probe()
1543 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8); in tegra_qspi_probe()
1544 master->flags = SPI_CONTROLLER_HALF_DUPLEX; in tegra_qspi_probe()
1545 master->setup = tegra_qspi_setup; in tegra_qspi_probe()
1546 master->transfer_one_message = tegra_qspi_transfer_one_message; in tegra_qspi_probe()
1547 master->num_chipselect = 1; in tegra_qspi_probe()
1548 master->auto_runtime_pm = true; in tegra_qspi_probe()
1550 bus_num = of_alias_get_id(pdev->dev.of_node, "spi"); in tegra_qspi_probe()
1552 master->bus_num = bus_num; in tegra_qspi_probe()
1554 tqspi->master = master; in tegra_qspi_probe()
1555 tqspi->dev = &pdev->dev; in tegra_qspi_probe()
1556 spin_lock_init(&tqspi->lock); in tegra_qspi_probe()
1558 tqspi->soc_data = device_get_match_data(&pdev->dev); in tegra_qspi_probe()
1559 master->num_chipselect = tqspi->soc_data->cs_count; in tegra_qspi_probe()
1560 tqspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); in tegra_qspi_probe()
1561 if (IS_ERR(tqspi->base)) in tegra_qspi_probe()
1562 return PTR_ERR(tqspi->base); in tegra_qspi_probe()
1564 tqspi->phys = r->start; in tegra_qspi_probe()
1568 tqspi->irq = qspi_irq; in tegra_qspi_probe()
1570 if (!has_acpi_companion(tqspi->dev)) { in tegra_qspi_probe()
1571 tqspi->clk = devm_clk_get(&pdev->dev, "qspi"); in tegra_qspi_probe()
1572 if (IS_ERR(tqspi->clk)) { in tegra_qspi_probe()
1573 ret = PTR_ERR(tqspi->clk); in tegra_qspi_probe()
1574 dev_err(&pdev->dev, "failed to get clock: %d\n", ret); in tegra_qspi_probe()
1580 tqspi->max_buf_size = QSPI_FIFO_DEPTH << 2; in tegra_qspi_probe()
1581 tqspi->dma_buf_size = DEFAULT_QSPI_DMA_BUF_LEN; in tegra_qspi_probe()
1587 if (tqspi->use_dma) in tegra_qspi_probe()
1588 tqspi->max_buf_size = tqspi->dma_buf_size; in tegra_qspi_probe()
1590 init_completion(&tqspi->tx_dma_complete); in tegra_qspi_probe()
1591 init_completion(&tqspi->rx_dma_complete); in tegra_qspi_probe()
1592 init_completion(&tqspi->xfer_completion); in tegra_qspi_probe()
1594 pm_runtime_enable(&pdev->dev); in tegra_qspi_probe()
1595 ret = pm_runtime_resume_and_get(&pdev->dev); in tegra_qspi_probe()
1597 dev_err(&pdev->dev, "failed to get runtime PM: %d\n", ret); in tegra_qspi_probe()
1601 if (device_reset(tqspi->dev) < 0) in tegra_qspi_probe()
1602 dev_warn_once(tqspi->dev, "device reset failed\n"); in tegra_qspi_probe()
1604 tqspi->def_command1_reg = QSPI_M_S | QSPI_CS_SW_HW | QSPI_CS_SW_VAL; in tegra_qspi_probe()
1605 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_probe()
1606 tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1); in tegra_qspi_probe()
1607 tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2); in tegra_qspi_probe()
1608 tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2); in tegra_qspi_probe()
1610 pm_runtime_put(&pdev->dev); in tegra_qspi_probe()
1612 ret = request_threaded_irq(tqspi->irq, NULL, in tegra_qspi_probe()
1614 dev_name(&pdev->dev), tqspi); in tegra_qspi_probe()
1616 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", tqspi->irq, ret); in tegra_qspi_probe()
1620 master->dev.of_node = pdev->dev.of_node; in tegra_qspi_probe()
1623 dev_err(&pdev->dev, "failed to register master: %d\n", ret); in tegra_qspi_probe()
1632 pm_runtime_force_suspend(&pdev->dev); in tegra_qspi_probe()
1643 free_irq(tqspi->irq, tqspi); in tegra_qspi_remove()
1644 pm_runtime_force_suspend(&pdev->dev); in tegra_qspi_remove()
1667 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_resume()
1668 tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2); in tegra_qspi_resume()
1680 if (has_acpi_companion(tqspi->dev)) in tegra_qspi_runtime_suspend()
1685 clk_disable_unprepare(tqspi->clk); in tegra_qspi_runtime_suspend()
1697 if (has_acpi_companion(tqspi->dev)) in tegra_qspi_runtime_resume()
1699 ret = clk_prepare_enable(tqspi->clk); in tegra_qspi_runtime_resume()
1701 dev_err(tqspi->dev, "failed to enable clock: %d\n", ret); in tegra_qspi_runtime_resume()
1713 .name = "tegra-qspi",
1723 MODULE_ALIAS("platform:qspi-tegra");