Lines Matching +full:rx +full:- +full:float +full:- +full:inactive
1 // SPDX-License-Identifier: GPL-2.0+
30 #include <linux/dma-mapping.h>
33 #include <linux/dma/imx-dma.h>
125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
154 #define UTS_LOOP (1<<12) /* Loop tx and rx */
161 /* We've been assigned a range on the "Low-density serial ports" major */
174 #define DRIVER_NAME "IMX-uart"
266 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
267 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
268 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
269 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
276 writel(val, sport->port.membase + offset); in imx_uart_writel()
281 return readl(sport->port.membase + offset); in imx_uart_readl()
286 return sport->devdata->uts_reg; in imx_uart_uts_reg()
291 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
302 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
303 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
304 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
311 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
312 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
313 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
322 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
331 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
350 * and UTS[6-3]". in imx_uart_soft_reset()
363 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_soft_reset()
371 sport->idle_counter = 0; in imx_uart_soft_reset()
395 if (sport->dma_is_enabled) { in imx_uart_start_rx()
414 if (sport->tx_state == OFF) in imx_uart_stop_tx()
421 if (sport->dma_is_txing) in imx_uart_stop_tx()
438 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
439 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
440 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
442 if (port->rs485.delay_rts_after_send > 0) { in imx_uart_stop_tx()
443 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
444 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
451 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
452 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
455 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
458 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
464 if (!port->rs485_rx_during_tx_gpio) in imx_uart_stop_tx()
467 sport->tx_state = OFF; in imx_uart_stop_tx()
470 sport->tx_state = OFF; in imx_uart_stop_tx()
483 if (sport->dma_is_enabled) { in imx_uart_stop_rx_with_loopback_ctrl()
494 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_stop_rx_with_loopback_ctrl()
495 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_stop_rx_with_loopback_ctrl()
496 sport->have_rtscts && !sport->have_rtsgpio && loopback) { in imx_uart_stop_rx_with_loopback_ctrl()
512 * Stop RX and enable loopback in order to make sure RS485 bus in imx_uart_stop_rx()
523 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
525 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
533 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
535 if (sport->port.x_char) { in imx_uart_transmit_buffer()
537 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
538 sport->port.icount.tx++; in imx_uart_transmit_buffer()
539 sport->port.x_char = 0; in imx_uart_transmit_buffer()
543 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
544 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
548 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
551 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
556 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
569 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
571 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
572 uart_xmit_advance(&sport->port, 1); in imx_uart_transmit_buffer()
576 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
579 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
585 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
586 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
590 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
592 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
598 uart_xmit_advance(&sport->port, sport->tx_bytes); in imx_uart_dma_tx_callback()
600 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
602 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
605 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
607 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
609 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
615 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
621 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
622 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
624 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
625 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
629 if (sport->dma_is_txing) in imx_uart_dma_tx()
636 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
638 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
639 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
640 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
642 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
644 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
645 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
646 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
649 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
657 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
662 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
663 desc->callback_param = sport; in imx_uart_dma_tx()
673 sport->dma_is_txing = 1; in imx_uart_dma_tx()
685 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
689 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
694 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
695 if (sport->tx_state == OFF) { in imx_uart_start_tx()
697 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
704 * Since we are about to transmit we can not stop RX in imx_uart_start_tx()
706 * transmitted data being just looped to RX. in imx_uart_start_tx()
708 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && in imx_uart_start_tx()
709 !port->rs485_rx_during_tx_gpio) in imx_uart_start_tx()
712 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
714 if (port->rs485.delay_rts_before_send > 0) { in imx_uart_start_tx()
715 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
716 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
723 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
724 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
726 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
731 * tx-callback. in imx_uart_start_tx()
733 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
739 sport->tx_state = SEND; in imx_uart_start_tx()
742 sport->tx_state = SEND; in imx_uart_start_tx()
745 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
750 if (sport->dma_is_enabled) { in imx_uart_start_tx()
751 if (sport->port.x_char) { in imx_uart_start_tx()
752 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
753 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
761 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
776 * Update sport->old_status here, so any follow-up calls to in __imx_uart_rtsint()
787 sport->old_status |= TIOCM_CTS; in __imx_uart_rtsint()
789 sport->old_status &= ~TIOCM_CTS; in __imx_uart_rtsint()
790 uart_handle_cts_change(&sport->port, usr1); in __imx_uart_rtsint()
791 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
801 spin_lock(&sport->port.lock); in imx_uart_rtsint()
805 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
814 spin_lock(&sport->port.lock); in imx_uart_txint()
816 spin_unlock(&sport->port.lock); in imx_uart_txint()
820 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
821 * This is to be called from Rx ISRs only when some bytes were actually
828 * issuing soft reset to the UART (just stop/start of RX does not help). Note
834 /* To detect hardware 0xff flood we monitor RxD line between RX in imx_uart_check_flood()
840 * progress, so we might get RX interrupt later with USR2_WAKE bit in imx_uart_check_flood()
847 * We use 'idle_counter' to ensure that we got at least so many RX in imx_uart_check_flood()
854 * We count interrupts, not chars in 'idle-counter' for simplicity. in imx_uart_check_flood()
859 sport->idle_counter = 0; in imx_uart_check_flood()
860 } else if (++sport->idle_counter > 3) { in imx_uart_check_flood()
861 dev_warn(sport->port.dev, "RX flood detected: soft reset."); in imx_uart_check_flood()
862 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ in imx_uart_check_flood()
869 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
870 u32 usr2, rx; in __imx_uart_rxint() local
877 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) { in __imx_uart_rxint()
879 sport->port.icount.rx++; in __imx_uart_rxint()
881 if (unlikely(rx & URXD_ERR)) { in __imx_uart_rxint()
882 if (rx & URXD_BRK) { in __imx_uart_rxint()
883 sport->port.icount.brk++; in __imx_uart_rxint()
884 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
887 else if (rx & URXD_PRERR) in __imx_uart_rxint()
888 sport->port.icount.parity++; in __imx_uart_rxint()
889 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
890 sport->port.icount.frame++; in __imx_uart_rxint()
891 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
892 sport->port.icount.overrun++; in __imx_uart_rxint()
894 if (rx & sport->port.ignore_status_mask) in __imx_uart_rxint()
897 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
899 if (rx & URXD_BRK) in __imx_uart_rxint()
901 else if (rx & URXD_PRERR) in __imx_uart_rxint()
903 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
905 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
908 sport->port.sysrq = 0; in __imx_uart_rxint()
909 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { in __imx_uart_rxint()
913 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
916 if (tty_insert_flip_char(port, rx, flg) == 0) in __imx_uart_rxint()
917 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
930 spin_lock(&sport->port.lock); in imx_uart_rxint()
934 spin_unlock(&sport->port.lock); in imx_uart_rxint()
957 if (sport->dte_mode) in imx_uart_get_hwmctrl()
972 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
977 sport->old_status = status; in imx_uart_mctrl_check()
980 sport->port.icount.rng++; in imx_uart_mctrl_check()
982 sport->port.icount.dsr++; in imx_uart_mctrl_check()
984 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
986 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
988 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
997 spin_lock(&sport->port.lock); in imx_uart_int()
1009 * actions, for example if a character that sits in the RX FIFO and that in imx_uart_int()
1062 sport->port.icount.overrun++; in imx_uart_int()
1067 spin_unlock(&sport->port.lock); in imx_uart_int()
1083 if (sport->dma_is_txing) in imx_uart_tx_empty()
1095 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1106 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1138 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1150 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1159 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1163 * This is our per-port timeout handler, for checking the
1171 if (sport->port.state) { in imx_uart_timeout()
1172 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1174 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1176 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1181 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1182 * [1] the RX DMA buffer is full.
1191 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1192 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1193 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1195 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1201 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1204 spin_lock(&sport->port.lock); in imx_uart_dma_rx_callback()
1206 spin_unlock(&sport->port.lock); in imx_uart_dma_rx_callback()
1211 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1214 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1216 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1222 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1225 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1226 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1228 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1229 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1232 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1235 spin_lock(&sport->port.lock); in imx_uart_dma_rx_callback()
1237 spin_unlock(&sport->port.lock); in imx_uart_dma_rx_callback()
1239 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1241 /* CPU claims ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1242 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1246 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1248 /* UART retrieves ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1249 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1253 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1255 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1258 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1259 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1264 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1270 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1271 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1272 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1276 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1277 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1279 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size); in imx_uart_start_rx_dma()
1282 dev_err(dev, "DMA mapping error for RX.\n"); in imx_uart_start_rx_dma()
1283 return -EINVAL; in imx_uart_start_rx_dma()
1287 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1292 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); in imx_uart_start_rx_dma()
1293 return -EINVAL; in imx_uart_start_rx_dma()
1295 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1296 desc->callback_param = sport; in imx_uart_start_rx_dma()
1298 dev_dbg(dev, "RX: prepare for the DMA.\n"); in imx_uart_start_rx_dma()
1299 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1300 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1307 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1314 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1316 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1318 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1322 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1325 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1331 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1335 sport->idle_counter = 0; in imx_uart_clear_rx_errors()
1358 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1359 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1360 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1361 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1362 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1363 kfree(sport->rx_buf); in imx_uart_dma_exit()
1364 sport->rx_buf = NULL; in imx_uart_dma_exit()
1367 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1368 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1369 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1370 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1377 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1380 /* Prepare for RX : */ in imx_uart_dma_init()
1381 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1382 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1384 ret = -EINVAL; in imx_uart_dma_init()
1389 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1392 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1393 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1395 dev_err(dev, "error in RX dma configuration.\n"); in imx_uart_dma_init()
1399 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods; in imx_uart_dma_init()
1400 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL); in imx_uart_dma_init()
1401 if (!sport->rx_buf) { in imx_uart_dma_init()
1402 ret = -ENOMEM; in imx_uart_dma_init()
1405 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1408 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1409 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1411 ret = -EINVAL; in imx_uart_dma_init()
1416 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1419 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1442 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1454 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_disable_dma()
1456 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1459 /* half the RX buffer size */
1470 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1473 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1475 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1479 if (uart_console(&sport->port)) in imx_uart_startup()
1480 sport->rxtl = RXTL_CONSOLE_DEFAULT; in imx_uart_startup()
1482 sport->rxtl = RXTL_DEFAULT; in imx_uart_startup()
1484 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_startup()
1501 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1514 if (sport->have_rtscts) in imx_uart_startup()
1522 if (sport->inverted_rx) in imx_uart_startup()
1530 if (sport->inverted_tx) in imx_uart_startup()
1536 if (sport->dte_mode) in imx_uart_startup()
1544 if (!sport->have_rtscts) in imx_uart_startup()
1547 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1557 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1574 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1585 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1586 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1587 if (sport->dma_is_txing) { in imx_uart_shutdown()
1588 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1589 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1590 sport->dma_is_txing = 0; in imx_uart_shutdown()
1592 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1593 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1594 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1596 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1599 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1603 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1607 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1609 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1613 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1618 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1624 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1630 if (port->rs485.flags & SER_RS485_ENABLED && in imx_uart_shutdown()
1631 port->rs485.flags & SER_RS485_RTS_ON_SEND && in imx_uart_shutdown()
1632 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_shutdown()
1646 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1648 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1649 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1656 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1658 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1661 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1662 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1663 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1666 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1671 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1686 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1694 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1695 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1696 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1697 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1701 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1706 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1709 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1719 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1722 if (!sport->have_rtscts) in imx_uart_set_termios()
1723 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1725 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1731 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1736 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1739 * to have RTS inactive (which then should take precedence). in imx_uart_set_termios()
1745 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1747 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1749 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1751 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1755 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1756 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1757 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1758 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1759 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1764 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1765 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1766 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1767 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1768 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1773 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1774 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1777 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1778 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1781 * Update the per-port timeout. in imx_uart_set_termios()
1783 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1785 /* custom-baudrate handling */ in imx_uart_set_termios()
1786 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1788 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1790 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1796 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1799 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1805 num -= 1; in imx_uart_set_termios()
1806 denom -= 1; in imx_uart_set_termios()
1829 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1834 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1835 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1837 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1842 return port->type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1851 port->type = PORT_IMX; in imx_uart_config_port()
1864 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1865 ret = -EINVAL; in imx_uart_verify_port()
1866 if (port->irq != ser->irq) in imx_uart_verify_port()
1867 ret = -EINVAL; in imx_uart_verify_port()
1868 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1869 ret = -EINVAL; in imx_uart_verify_port()
1870 if (port->uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1871 ret = -EINVAL; in imx_uart_verify_port()
1872 if (port->mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1873 ret = -EINVAL; in imx_uart_verify_port()
1874 if (port->iobase != ser->port) in imx_uart_verify_port()
1875 ret = -EINVAL; in imx_uart_verify_port()
1876 if (ser->hub6 != 0) in imx_uart_verify_port()
1877 ret = -EINVAL; in imx_uart_verify_port()
1890 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1893 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1895 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1897 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_poll_init()
1899 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1904 * This prevents that a character that already sits in the RX fifo is in imx_uart_poll_init()
1927 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1968 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1969 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1970 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1971 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1972 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1976 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1983 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1984 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1985 rs485conf->flags & SER_RS485_RX_DURING_TX) { in imx_uart_rs485_config()
1989 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_rs485_config()
2038 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
2044 if (sport->port.sysrq) in imx_uart_console_write()
2047 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2049 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2066 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2077 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2117 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2119 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2125 * without need of float support or long long division, in imx_uart_console_get_options()
2138 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2158 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2159 co->index = 0; in imx_uart_console_setup()
2160 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2162 return -ENODEV; in imx_uart_console_setup()
2165 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2174 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, sport->rxtl); in imx_uart_console_setup()
2176 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2179 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2183 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2185 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2194 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_exit()
2196 clk_disable_unprepare(sport->clk_per); in imx_uart_console_exit()
2197 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_exit()
2210 .index = -1,
2235 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2236 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2237 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2238 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2248 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2249 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2250 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2251 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2263 /* Default RX DMA buffer configuration */
2269 struct device_node *np = pdev->dev.of_node; in imx_uart_probe()
2278 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2280 return -ENOMEM; in imx_uart_probe()
2282 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe()
2286 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe()
2289 sport->port.line = ret; in imx_uart_probe()
2291 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") || in imx_uart_probe()
2292 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */ in imx_uart_probe()
2294 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode"); in imx_uart_probe()
2296 sport->have_rtsgpio = of_property_present(np, "rts-gpios"); in imx_uart_probe()
2298 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx"); in imx_uart_probe()
2300 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx"); in imx_uart_probe()
2302 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) { in imx_uart_probe()
2303 sport->rx_period_length = dma_buf_conf[0]; in imx_uart_probe()
2304 sport->rx_periods = dma_buf_conf[1]; in imx_uart_probe()
2306 sport->rx_period_length = RX_DMA_PERIOD_LEN; in imx_uart_probe()
2307 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_probe()
2310 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2311 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2312 sport->port.line); in imx_uart_probe()
2313 return -EINVAL; in imx_uart_probe()
2326 sport->port.dev = &pdev->dev; in imx_uart_probe()
2327 sport->port.mapbase = res->start; in imx_uart_probe()
2328 sport->port.membase = base; in imx_uart_probe()
2329 sport->port.type = PORT_IMX; in imx_uart_probe()
2330 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2331 sport->port.irq = rxirq; in imx_uart_probe()
2332 sport->port.fifosize = 32; in imx_uart_probe()
2333 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2334 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2335 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2337 if (sport->have_rtscts || sport->have_rtsgpio) in imx_uart_probe()
2338 sport->port.rs485_supported = imx_rs485_supported; in imx_uart_probe()
2339 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2340 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2342 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2343 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2344 return PTR_ERR(sport->gpios); in imx_uart_probe()
2346 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2347 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2348 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2349 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2353 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2354 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2355 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2356 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2360 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2363 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2365 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret); in imx_uart_probe()
2369 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2378 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2379 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2380 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2381 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2382 dev_err(&pdev->dev, in imx_uart_probe()
2383 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2400 * data from being fed into the RX FIFO, enable loopback mode in in imx_uart_probe()
2401 * UTS register, which disconnects the RX path from external RXD in imx_uart_probe()
2403 * no data can be fed to the RX FIFO that way. in imx_uart_probe()
2405 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2406 sport->have_rtscts && !sport->have_rtsgpio) { in imx_uart_probe()
2420 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2451 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2452 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2453 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2454 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2461 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2462 dev_name(&pdev->dev), sport); in imx_uart_probe()
2464 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2469 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2470 dev_name(&pdev->dev), sport); in imx_uart_probe()
2472 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2477 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2478 dev_name(&pdev->dev), sport); in imx_uart_probe()
2480 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2485 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2486 dev_name(&pdev->dev), sport); in imx_uart_probe()
2488 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2493 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2497 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2500 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2509 uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2518 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2519 if (!sport->context_saved) { in imx_uart_restore_context()
2520 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2524 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2525 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2526 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2527 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2528 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2529 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2530 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2531 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2532 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2533 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2534 sport->context_saved = false; in imx_uart_restore_context()
2535 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2543 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2544 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2545 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2546 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2547 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2548 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2549 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2550 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2551 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2552 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2553 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2554 sport->context_saved = true; in imx_uart_save_context()
2555 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2571 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2589 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2603 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2617 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2618 disable_irq(sport->port.irq); in imx_uart_suspend()
2620 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2637 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2638 enable_irq(sport->port.irq); in imx_uart_resume()
2640 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2649 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2651 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2658 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2660 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2683 .name = "imx-uart",
2715 MODULE_ALIAS("platform:imx-uart");