Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
21 #include <ufs/ufshcd.h>
22 #include "ufshcd-pltfrm.h"
23 #include <ufs/unipro.h>
24 #include "ufs-qcom.h"
25 #include <ufs/ufshci.h>
26 #include <ufs/ufs_quirks.h>
114 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
115 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
120 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init()
121 struct device *dev = hba->dev; in ufs_qcom_ice_init()
125 if (ice == ERR_PTR(-EOPNOTSUPP)) { in ufs_qcom_ice_init()
133 host->ice = ice; in ufs_qcom_ice_init()
134 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_qcom_ice_init()
141 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_resume()
142 return qcom_ice_resume(host->ice); in ufs_qcom_ice_resume()
149 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_suspend()
150 return qcom_ice_suspend(host->ice); in ufs_qcom_ice_suspend()
162 if (!(cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE)) in ufs_qcom_ice_program_key()
163 return qcom_ice_evict_key(host->ice, slot); in ufs_qcom_ice_program_key()
165 /* Only AES-256-XTS has been tested so far. */ in ufs_qcom_ice_program_key()
166 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; in ufs_qcom_ice_program_key()
169 return -EOPNOTSUPP; in ufs_qcom_ice_program_key()
171 return qcom_ice_program_key(host->ice, in ufs_qcom_ice_program_key()
174 cfg->crypto_key, in ufs_qcom_ice_program_key()
175 cfg->data_unit_size, slot); in ufs_qcom_ice_program_key()
216 if (optional && err == -ENOENT) { in ufs_qcom_host_clk_get()
221 if (err != -EPROBE_DEFER) in ufs_qcom_host_clk_get()
241 if (!host->is_lane_clks_enabled) in ufs_qcom_disable_lane_clks()
244 clk_disable_unprepare(host->tx_l1_sync_clk); in ufs_qcom_disable_lane_clks()
245 clk_disable_unprepare(host->tx_l0_sync_clk); in ufs_qcom_disable_lane_clks()
246 clk_disable_unprepare(host->rx_l1_sync_clk); in ufs_qcom_disable_lane_clks()
247 clk_disable_unprepare(host->rx_l0_sync_clk); in ufs_qcom_disable_lane_clks()
249 host->is_lane_clks_enabled = false; in ufs_qcom_disable_lane_clks()
255 struct device *dev = host->hba->dev; in ufs_qcom_enable_lane_clks()
257 if (host->is_lane_clks_enabled) in ufs_qcom_enable_lane_clks()
261 host->rx_l0_sync_clk); in ufs_qcom_enable_lane_clks()
266 host->tx_l0_sync_clk); in ufs_qcom_enable_lane_clks()
271 host->rx_l1_sync_clk); in ufs_qcom_enable_lane_clks()
276 host->tx_l1_sync_clk); in ufs_qcom_enable_lane_clks()
280 host->is_lane_clks_enabled = true; in ufs_qcom_enable_lane_clks()
285 clk_disable_unprepare(host->rx_l1_sync_clk); in ufs_qcom_enable_lane_clks()
287 clk_disable_unprepare(host->tx_l0_sync_clk); in ufs_qcom_enable_lane_clks()
289 clk_disable_unprepare(host->rx_l0_sync_clk); in ufs_qcom_enable_lane_clks()
297 struct device *dev = host->hba->dev; in ufs_qcom_init_lane_clks()
303 &host->rx_l0_sync_clk, false); in ufs_qcom_init_lane_clks()
308 &host->tx_l0_sync_clk, false); in ufs_qcom_init_lane_clks()
313 if (host->hba->lanes_per_direction > 1) { in ufs_qcom_init_lane_clks()
315 &host->rx_l1_sync_clk, false); in ufs_qcom_init_lane_clks()
320 &host->tx_l1_sync_clk, true); in ufs_qcom_init_lane_clks()
355 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_qcom_check_hibern8()
359 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", in ufs_qcom_check_hibern8()
368 ufshcd_rmwl(host->hba, QUNIPRO_SEL, in ufs_qcom_select_unipro_mode()
372 if (host->hw_ver.major >= 0x05) in ufs_qcom_select_unipro_mode()
373 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
377 * ufs_qcom_host_reset - reset host controller and PHY
385 if (!host->core_reset) { in ufs_qcom_host_reset()
386 dev_warn(hba->dev, "%s: reset control not set\n", __func__); in ufs_qcom_host_reset()
390 reenable_intr = hba->is_irq_enabled; in ufs_qcom_host_reset()
391 disable_irq(hba->irq); in ufs_qcom_host_reset()
392 hba->is_irq_enabled = false; in ufs_qcom_host_reset()
394 ret = reset_control_assert(host->core_reset); in ufs_qcom_host_reset()
396 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", in ufs_qcom_host_reset()
403 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in ufs_qcom_host_reset()
408 ret = reset_control_deassert(host->core_reset); in ufs_qcom_host_reset()
410 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", in ufs_qcom_host_reset()
416 enable_irq(hba->irq); in ufs_qcom_host_reset()
417 hba->is_irq_enabled = true; in ufs_qcom_host_reset()
427 if (host->hw_ver.major == 0x1) { in ufs_qcom_get_hs_gear()
429 * HS-G3 operations may not reliably work on legacy QCOM in ufs_qcom_get_hs_gear()
430 * UFS host controller hardware even though capability in ufs_qcom_get_hs_gear()
433 * Hence downgrade the maximum supported gear to HS-G2. in ufs_qcom_get_hs_gear()
436 } else if (host->hw_ver.major >= 0x4) { in ufs_qcom_get_hs_gear()
440 /* Default is HS-G3 */ in ufs_qcom_get_hs_gear()
447 struct phy *phy = host->generic_phy; in ufs_qcom_power_up_sequence()
450 /* Reset UFS Host Controller and PHY */ in ufs_qcom_power_up_sequence()
453 dev_warn(hba->dev, "%s: host reset returned %d\n", in ufs_qcom_power_up_sequence()
456 if (phy->power_count) in ufs_qcom_power_up_sequence()
460 /* phy initialization - calibrate the phy */ in ufs_qcom_power_up_sequence()
463 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in ufs_qcom_power_up_sequence()
468 phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); in ufs_qcom_power_up_sequence()
470 /* power on phy - start serdes and phy's power and clocks */ in ufs_qcom_power_up_sequence()
473 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", in ufs_qcom_power_up_sequence()
490 * Internal hardware sub-modules within the UTP controller control the CGCs.
491 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
493 * this function enables them (after every UFS link startup) to save some power
523 /* check if UFS PHY moved from DISABLED to HIBERN8 */ in ufs_qcom_hce_enable_notify()
529 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); in ufs_qcom_hce_enable_notify()
530 err = -EINVAL; in ufs_qcom_hce_enable_notify()
537 * Return: zero for success and non-zero in case of a failure.
579 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); in ufs_qcom_cfg_timers()
580 return -EINVAL; in ufs_qcom_cfg_timers()
583 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_cfg_timers()
584 if (!strcmp(clki->name, "core_clk")) in ufs_qcom_cfg_timers()
585 core_clk_rate = clk_get_rate(clki->clk); in ufs_qcom_cfg_timers()
614 dev_err(hba->dev, in ufs_qcom_cfg_timers()
618 return -EINVAL; in ufs_qcom_cfg_timers()
620 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; in ufs_qcom_cfg_timers()
623 dev_err(hba->dev, in ufs_qcom_cfg_timers()
627 return -EINVAL; in ufs_qcom_cfg_timers()
629 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; in ufs_qcom_cfg_timers()
631 dev_err(hba->dev, "%s: invalid rate = %d\n", in ufs_qcom_cfg_timers()
633 return -EINVAL; in ufs_qcom_cfg_timers()
639 dev_err(hba->dev, in ufs_qcom_cfg_timers()
643 return -EINVAL; in ufs_qcom_cfg_timers()
645 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; in ufs_qcom_cfg_timers()
649 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); in ufs_qcom_cfg_timers()
650 return -EINVAL; in ufs_qcom_cfg_timers()
665 if (update_link_startup_timer && host->hw_ver.major != 0x5) { in ufs_qcom_cfg_timers()
688 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_link_startup_notify()
690 return -EINVAL; in ufs_qcom_link_startup_notify()
702 * Some UFS devices (and may be host) have issues if LCC is in ufs_qcom_link_startup_notify()
724 if (!host->device_reset) in ufs_qcom_device_reset_ctrl()
727 gpiod_set_value_cansleep(host->device_reset, asserted); in ufs_qcom_device_reset_ctrl()
734 struct phy *phy = host->generic_phy; in ufs_qcom_suspend()
748 /* reset the connected UFS device during power down */ in ufs_qcom_suspend()
761 struct phy *phy = host->generic_phy; in ufs_qcom_resume()
767 dev_err(hba->dev, "%s: failed PHY power on: %d\n", in ufs_qcom_resume()
787 if (host->dev_ref_clk_ctrl_mmio && in ufs_qcom_dev_ref_clk_ctrl()
788 (enable ^ host->is_dev_ref_clk_enabled)) { in ufs_qcom_dev_ref_clk_ctrl()
789 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
792 temp |= host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
794 temp &= ~host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
805 gating_wait = host->hba->dev_info.clk_gating_wait_us; in ufs_qcom_dev_ref_clk_ctrl()
813 * HS-MODE to LS-MODE or HIBERN8 state. Give it in ufs_qcom_dev_ref_clk_ctrl()
821 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
827 readl(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
837 host->is_dev_ref_clk_enabled = enable; in ufs_qcom_dev_ref_clk_ctrl()
843 struct device *dev = host->hba->dev; in ufs_qcom_icc_set_bw()
846 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); in ufs_qcom_icc_set_bw()
852 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); in ufs_qcom_icc_set_bw()
863 struct ufs_pa_layer_attr *p = &host->dev_req_params; in ufs_qcom_get_bw_table()
864 int gear = max_t(u32, p->gear_rx, p->gear_tx); in ufs_qcom_get_bw_table()
865 int lane = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_bw_table()
868 if (p->hs_rate == PA_HS_MODE_B) in ufs_qcom_get_bw_table()
897 return -EINVAL; in ufs_qcom_pwr_change_notify()
912 dev_err(hba->dev, "%s: failed to determine capabilities\n", in ufs_qcom_pwr_change_notify()
922 if (dev_req_params->gear_tx > host->hs_gear) in ufs_qcom_pwr_change_notify()
923 host->hs_gear = dev_req_params->gear_tx; in ufs_qcom_pwr_change_notify()
926 if (!ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
930 if (host->hw_ver.major >= 0x4) { in ufs_qcom_pwr_change_notify()
932 dev_req_params->gear_tx, in ufs_qcom_pwr_change_notify()
937 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, in ufs_qcom_pwr_change_notify()
938 dev_req_params->pwr_rx, in ufs_qcom_pwr_change_notify()
939 dev_req_params->hs_rate, false)) { in ufs_qcom_pwr_change_notify()
940 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_pwr_change_notify()
947 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
951 memcpy(&host->dev_req_params, in ufs_qcom_pwr_change_notify()
957 if (ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
962 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
988 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) in ufs_qcom_apply_dev_quirks()
991 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) in ufs_qcom_apply_dev_quirks()
992 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; in ufs_qcom_apply_dev_quirks()
1001 if (host->hw_ver.major == 0x1) in ufs_qcom_get_ufs_hci_version()
1008 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1011 * QCOM UFS host controller might have some non standard behaviours (quirks)
1013 * quirks to standard UFS host controller driver so standard takes them into
1020 if (host->hw_ver.major == 0x01) { in ufs_qcom_advertise_quirks()
1021 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS in ufs_qcom_advertise_quirks()
1025 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) in ufs_qcom_advertise_quirks()
1026 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; in ufs_qcom_advertise_quirks()
1028 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; in ufs_qcom_advertise_quirks()
1031 if (host->hw_ver.major == 0x2) { in ufs_qcom_advertise_quirks()
1032 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; in ufs_qcom_advertise_quirks()
1036 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS in ufs_qcom_advertise_quirks()
1041 if (host->hw_ver.major > 0x3) in ufs_qcom_advertise_quirks()
1042 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_advertise_quirks()
1049 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_qcom_set_caps()
1050 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; in ufs_qcom_set_caps()
1051 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; in ufs_qcom_set_caps()
1052 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_qcom_set_caps()
1053 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; in ufs_qcom_set_caps()
1054 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_qcom_set_caps()
1056 if (host->hw_ver.major >= 0x2) { in ufs_qcom_set_caps()
1057 host->caps = UFS_QCOM_CAP_QUNIPRO | in ufs_qcom_set_caps()
1063 * ufs_qcom_setup_clocks - enables/disable clocks
1068 * Return: 0 on success, non-zero on failure.
1097 if (ufshcd_is_hs_mode(&hba->pwr_info)) in ufs_qcom_setup_clocks()
1114 ufs_qcom_assert_reset(host->hba); in ufs_qcom_reset_assert()
1125 ufs_qcom_deassert_reset(host->hba); in ufs_qcom_reset_deassert()
1142 struct device *dev = host->hba->dev; in ufs_qcom_icc_init()
1145 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); in ufs_qcom_icc_init()
1146 if (IS_ERR(host->icc_ddr)) in ufs_qcom_icc_init()
1147 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), in ufs_qcom_icc_init()
1150 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); in ufs_qcom_icc_init()
1151 if (IS_ERR(host->icc_cpu)) in ufs_qcom_icc_init()
1152 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), in ufs_qcom_icc_init()
1156 * Set Maximum bandwidth vote before initializing the UFS controller and in ufs_qcom_icc_init()
1169 * ufs_qcom_init - bind phy with controller
1175 * Return: -EPROBE_DEFER if binding fails, returns negative error
1181 struct device *dev = hba->dev; in ufs_qcom_init()
1189 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); in ufs_qcom_init()
1190 return -ENOMEM; in ufs_qcom_init()
1194 host->hba = hba; in ufs_qcom_init()
1198 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); in ufs_qcom_init()
1199 if (IS_ERR(host->core_reset)) { in ufs_qcom_init()
1200 err = dev_err_probe(dev, PTR_ERR(host->core_reset), in ufs_qcom_init()
1205 /* Fire up the reset controller. Failure here is non-fatal. */ in ufs_qcom_init()
1206 host->rcdev.of_node = dev->of_node; in ufs_qcom_init()
1207 host->rcdev.ops = &ufs_qcom_reset_ops; in ufs_qcom_init()
1208 host->rcdev.owner = dev->driver->owner; in ufs_qcom_init()
1209 host->rcdev.nr_resets = 1; in ufs_qcom_init()
1210 err = devm_reset_controller_register(dev, &host->rcdev); in ufs_qcom_init()
1215 host->generic_phy = devm_phy_get(dev, "ufsphy"); in ufs_qcom_init()
1216 if (IS_ERR(host->generic_phy)) { in ufs_qcom_init()
1217 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); in ufs_qcom_init()
1226 host->device_reset = devm_gpiod_get_optional(dev, "reset", in ufs_qcom_init()
1228 if (IS_ERR(host->device_reset)) { in ufs_qcom_init()
1229 err = PTR_ERR(host->device_reset); in ufs_qcom_init()
1230 if (err != -EPROBE_DEFER) in ufs_qcom_init()
1235 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, in ufs_qcom_init()
1236 &host->hw_ver.minor, &host->hw_ver.step); in ufs_qcom_init()
1240 * moved inside UFS controller register address space itself. in ufs_qcom_init()
1242 if (host->hw_ver.major >= 0x02) { in ufs_qcom_init()
1243 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; in ufs_qcom_init()
1244 host->dev_ref_clk_en_mask = BIT(26); in ufs_qcom_init()
1250 host->dev_ref_clk_ctrl_mmio = in ufs_qcom_init()
1252 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) in ufs_qcom_init()
1253 host->dev_ref_clk_ctrl_mmio = NULL; in ufs_qcom_init()
1254 host->dev_ref_clk_en_mask = BIT(5); in ufs_qcom_init()
1258 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_init()
1259 if (!strcmp(clki->name, "core_clk_unipro")) in ufs_qcom_init()
1260 clki->keep_link_active = true; in ufs_qcom_init()
1276 if (hba->dev->id < MAX_UFS_QCOM_HOSTS) in ufs_qcom_init()
1277 ufs_qcom_hosts[hba->dev->id] = host; in ufs_qcom_init()
1282 /* Failure is non-fatal */ in ufs_qcom_init()
1290 host->hs_gear = UFS_HS_G2; in ufs_qcom_init()
1305 phy_power_off(host->generic_phy); in ufs_qcom_exit()
1306 phy_exit(host->generic_phy); in ufs_qcom_exit()
1316 return -EINVAL; in ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div()
1392 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; in ufs_qcom_clk_scale_notify()
1425 dev_req_params->gear_rx, in ufs_qcom_clk_scale_notify()
1426 dev_req_params->pwr_rx, in ufs_qcom_clk_scale_notify()
1427 dev_req_params->hs_rate, in ufs_qcom_clk_scale_notify()
1438 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1440 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1446 host->testbus.select_major = TSTBUS_UNIPRO; in ufs_qcom_get_default_testbus_cfg()
1447 host->testbus.select_minor = 37; in ufs_qcom_get_default_testbus_cfg()
1452 if (host->testbus.select_major >= TSTBUS_MAX) { in ufs_qcom_testbus_cfg_is_ok()
1453 dev_err(host->hba->dev, in ufs_qcom_testbus_cfg_is_ok()
1455 __func__, host->testbus.select_major); in ufs_qcom_testbus_cfg_is_ok()
1469 return -EINVAL; in ufs_qcom_testbus_config()
1472 return -EPERM; in ufs_qcom_testbus_config()
1474 switch (host->testbus.select_major) { in ufs_qcom_testbus_config()
1531 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1532 (u32)host->testbus.select_major << 19, in ufs_qcom_testbus_config()
1534 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1535 (u32)host->testbus.select_minor << offset, in ufs_qcom_testbus_config()
1573 /* clear bit 17 - UTP_DBG_RAMS_EN */ in ufs_qcom_dump_dbg_regs()
1599 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1600 * @hba: per-adapter instance
1609 if (!host->device_reset) in ufs_qcom_device_reset()
1610 return -EOPNOTSUPP; in ufs_qcom_device_reset()
1613 * The UFS device shall detect reset pulses of 1us, sleep for 10us to in ufs_qcom_device_reset()
1630 p->polling_ms = 60; in ufs_qcom_config_scaling_param()
1631 p->timer = DEVFREQ_TIMER_DELAYED; in ufs_qcom_config_scaling_param()
1632 d->upthreshold = 70; in ufs_qcom_config_scaling_param()
1633 d->downdifferential = 5; in ufs_qcom_config_scaling_param()
1661 struct platform_device *pdev = to_platform_device(hba->dev); in ufs_qcom_mcq_config_resource()
1666 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); in ufs_qcom_mcq_config_resource()
1669 res = &hba->res[i]; in ufs_qcom_mcq_config_resource()
1670 res->resource = platform_get_resource_byname(pdev, in ufs_qcom_mcq_config_resource()
1672 res->name); in ufs_qcom_mcq_config_resource()
1673 if (!res->resource) { in ufs_qcom_mcq_config_resource()
1674 dev_info(hba->dev, "Resource %s not provided\n", res->name); in ufs_qcom_mcq_config_resource()
1676 return -ENODEV; in ufs_qcom_mcq_config_resource()
1679 res_mem = res->resource; in ufs_qcom_mcq_config_resource()
1680 res->base = hba->mmio_base; in ufs_qcom_mcq_config_resource()
1684 res->base = devm_ioremap_resource(hba->dev, res->resource); in ufs_qcom_mcq_config_resource()
1685 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1686 dev_err(hba->dev, "Failed to map res %s, err=%d\n", in ufs_qcom_mcq_config_resource()
1687 res->name, (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1688 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1689 res->base = NULL; in ufs_qcom_mcq_config_resource()
1695 res = &hba->res[RES_MCQ]; in ufs_qcom_mcq_config_resource()
1697 if (res->base) in ufs_qcom_mcq_config_resource()
1701 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); in ufs_qcom_mcq_config_resource()
1703 return -ENOMEM; in ufs_qcom_mcq_config_resource()
1705 res_mcq->start = res_mem->start + in ufs_qcom_mcq_config_resource()
1706 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); in ufs_qcom_mcq_config_resource()
1707 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; in ufs_qcom_mcq_config_resource()
1708 res_mcq->flags = res_mem->flags; in ufs_qcom_mcq_config_resource()
1709 res_mcq->name = "mcq"; in ufs_qcom_mcq_config_resource()
1713 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", in ufs_qcom_mcq_config_resource()
1718 res->base = devm_ioremap_resource(hba->dev, res_mcq); in ufs_qcom_mcq_config_resource()
1719 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1720 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", in ufs_qcom_mcq_config_resource()
1721 (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1722 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1727 hba->mcq_base = res->base; in ufs_qcom_mcq_config_resource()
1730 res->base = NULL; in ufs_qcom_mcq_config_resource()
1741 mem_res = &hba->res[RES_UFS]; in ufs_qcom_op_runtime_config()
1742 sqdao_res = &hba->res[RES_MCQ_SQD]; in ufs_qcom_op_runtime_config()
1744 if (!mem_res->base || !sqdao_res->base) in ufs_qcom_op_runtime_config()
1745 return -EINVAL; in ufs_qcom_op_runtime_config()
1748 opr = &hba->mcq_opr[i]; in ufs_qcom_op_runtime_config()
1749 opr->offset = sqdao_res->resource->start - in ufs_qcom_op_runtime_config()
1750 mem_res->resource->start + 0x40 * i; in ufs_qcom_op_runtime_config()
1751 opr->stride = 0x100; in ufs_qcom_op_runtime_config()
1752 opr->base = sqdao_res->base + 0x40 * i; in ufs_qcom_op_runtime_config()
1767 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; in ufs_qcom_get_outstanding_cqs()
1769 if (!mcq_vs_res->base) in ufs_qcom_get_outstanding_cqs()
1770 return -EINVAL; in ufs_qcom_get_outstanding_cqs()
1772 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); in ufs_qcom_get_outstanding_cqs()
1790 u32 id = desc->msi_index; in ufs_qcom_mcq_esi_handler()
1791 struct ufs_hw_queue *hwq = &hba->uhq[id]; in ufs_qcom_mcq_esi_handler()
1806 if (host->esi_enabled) in ufs_qcom_config_esi()
1813 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; in ufs_qcom_config_esi()
1814 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, in ufs_qcom_config_esi()
1817 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); in ufs_qcom_config_esi()
1821 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1822 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1823 ret = devm_request_irq(hba->dev, desc->irq, in ufs_qcom_config_esi()
1825 IRQF_SHARED, "qcom-mcq-esi", desc); in ufs_qcom_config_esi()
1827 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", in ufs_qcom_config_esi()
1828 __func__, desc->irq, ret); in ufs_qcom_config_esi()
1833 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1837 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1838 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1841 devm_free_irq(hba->dev, desc->irq, hba); in ufs_qcom_config_esi()
1843 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1844 platform_msi_domain_free_irqs(hba->dev); in ufs_qcom_config_esi()
1846 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && in ufs_qcom_config_esi()
1847 host->hw_ver.step == 0) { in ufs_qcom_config_esi()
1857 host->esi_enabled = true; in ufs_qcom_config_esi()
1863 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1893 * ufs_qcom_probe - probe routine of the driver
1896 * Return: zero for success and non-zero for failure.
1901 struct device *dev = &pdev->dev; in ufs_qcom_probe()
1912 * ufs_qcom_remove - set driver_data of the device to NULL
1922 pm_runtime_get_sync(&(pdev)->dev); in ufs_qcom_remove()
1924 if (host->esi_enabled) in ufs_qcom_remove()
1925 platform_msi_domain_free_irqs(hba->dev); in ufs_qcom_remove()
1960 .name = "ufshcd-qcom",