Lines Matching +full:0 +full:x00000031
58 * max : 74 : 0 dB
60 * min : 0 : -74 dB
62 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7400, 100, 0);
63 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7400, 100, 0);
64 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 1200, 0);
72 0, 0, TLV_DB_SCALE_ITEM(120, 0, 0),
73 1, 63, TLV_DB_SCALE_ITEM(30, 30, 0)
96 { CX2072X_AFG_POWER_STATE, 0x00000003 },
97 { CX2072X_UM_RESPONSE, 0x00000000 },
98 { CX2072X_GPIO_DATA, 0x00000000 },
99 { CX2072X_GPIO_ENABLE, 0x00000000 },
100 { CX2072X_GPIO_DIRECTION, 0x00000000 },
101 { CX2072X_GPIO_WAKE, 0x00000000 },
102 { CX2072X_GPIO_UM_ENABLE, 0x00000000 },
103 { CX2072X_GPIO_STICKY_MASK, 0x00000000 },
104 { CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
105 { CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
106 { CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
107 { CX2072X_DAC1_POWER_STATE, 0x00000433 },
108 { CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
109 { CX2072X_DAC1_EAPD_ENABLE, 0x00000000 },
110 { CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
111 { CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
112 { CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
113 { CX2072X_DAC2_POWER_STATE, 0x00000433 },
114 { CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
115 { CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
116 { CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
117 { CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
118 { CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
119 { CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
120 { CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
121 { CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
122 { CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
123 { CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
124 { CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
125 { CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
126 { CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
127 { CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
128 { CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
129 { CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
130 { CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
131 { CX2072X_ADC1_POWER_STATE, 0x00000433 },
132 { CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
133 { CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
134 { CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
135 { CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
136 { CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
137 { CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
138 { CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
139 { CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
140 { CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
141 { CX2072X_ADC2_POWER_STATE, 0x00000433 },
142 { CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
143 { CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0x00000000 },
144 { CX2072X_PORTA_POWER_STATE, 0x00000433 },
145 { CX2072X_PORTA_PIN_CTRL, 0x000000c0 },
146 { CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x00000000 },
147 { CX2072X_PORTA_PIN_SENSE, 0x00000000 },
148 { CX2072X_PORTA_EAPD_BTL, 0x00000002 },
149 { CX2072X_PORTB_POWER_STATE, 0x00000433 },
150 { CX2072X_PORTB_PIN_CTRL, 0x00000000 },
151 { CX2072X_PORTB_UNSOLICITED_RESPONSE, 0x00000000 },
152 { CX2072X_PORTB_PIN_SENSE, 0x00000000 },
153 { CX2072X_PORTB_EAPD_BTL, 0x00000002 },
154 { CX2072X_PORTB_GAIN_RIGHT, 0x00000000 },
155 { CX2072X_PORTB_GAIN_LEFT, 0x00000000 },
156 { CX2072X_PORTC_POWER_STATE, 0x00000433 },
157 { CX2072X_PORTC_PIN_CTRL, 0x00000000 },
158 { CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
159 { CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
160 { CX2072X_PORTD_POWER_STATE, 0x00000433 },
161 { CX2072X_PORTD_PIN_CTRL, 0x00000020 },
162 { CX2072X_PORTD_UNSOLICITED_RESPONSE, 0x00000000 },
163 { CX2072X_PORTD_PIN_SENSE, 0x00000000 },
164 { CX2072X_PORTD_GAIN_RIGHT, 0x00000000 },
165 { CX2072X_PORTD_GAIN_LEFT, 0x00000000 },
166 { CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
167 { CX2072X_PORTE_POWER_STATE, 0x00000433 },
168 { CX2072X_PORTE_PIN_CTRL, 0x00000040 },
169 { CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
170 { CX2072X_PORTE_PIN_SENSE, 0x00000000 },
171 { CX2072X_PORTE_EAPD_BTL, 0x00000002 },
172 { CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
173 { CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
174 { CX2072X_PORTF_POWER_STATE, 0x00000433 },
175 { CX2072X_PORTF_PIN_CTRL, 0x00000000 },
176 { CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
177 { CX2072X_PORTF_PIN_SENSE, 0x00000000 },
178 { CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
179 { CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
180 { CX2072X_PORTG_POWER_STATE, 0x00000433 },
181 { CX2072X_PORTG_PIN_CTRL, 0x00000040 },
182 { CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
183 { CX2072X_PORTG_EAPD_BTL, 0x00000002 },
184 { CX2072X_PORTM_POWER_STATE, 0x00000433 },
185 { CX2072X_PORTM_PIN_CTRL, 0x00000000 },
186 { CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
187 { CX2072X_PORTM_EAPD_BTL, 0x00000002 },
188 { CX2072X_MIXER_POWER_STATE, 0x00000433 },
189 { CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
190 { CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
191 { CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
192 { CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
193 { CX2072X_SPKR_DRC_ENABLE_STEP, 0x040065a4 },
194 { CX2072X_SPKR_DRC_CONTROL, 0x007b0024 },
195 { CX2072X_SPKR_DRC_TEST, 0x00000000 },
196 { CX2072X_DIGITAL_BIOS_TEST0, 0x001f008a },
197 { CX2072X_DIGITAL_BIOS_TEST2, 0x00990026 },
198 { CX2072X_I2SPCM_CONTROL1, 0x00010001 },
199 { CX2072X_I2SPCM_CONTROL2, 0x00000000 },
200 { CX2072X_I2SPCM_CONTROL3, 0x00000000 },
201 { CX2072X_I2SPCM_CONTROL4, 0x00000000 },
202 { CX2072X_I2SPCM_CONTROL5, 0x00000000 },
203 { CX2072X_I2SPCM_CONTROL6, 0x00000000 },
204 { CX2072X_UM_INTERRUPT_CRTL_E, 0x00000000 },
205 { CX2072X_CODEC_TEST2, 0x00000000 },
206 { CX2072X_CODEC_TEST9, 0x00000004 },
207 { CX2072X_CODEC_TEST20, 0x00000600 },
208 { CX2072X_CODEC_TEST26, 0x00000208 },
209 { CX2072X_ANALOG_TEST4, 0x00000000 },
210 { CX2072X_ANALOG_TEST5, 0x00000000 },
211 { CX2072X_ANALOG_TEST6, 0x0000059a },
212 { CX2072X_ANALOG_TEST7, 0x000000a7 },
213 { CX2072X_ANALOG_TEST8, 0x00000017 },
214 { CX2072X_ANALOG_TEST9, 0x00000000 },
215 { CX2072X_ANALOG_TEST10, 0x00000285 },
216 { CX2072X_ANALOG_TEST11, 0x00000000 },
217 { CX2072X_ANALOG_TEST12, 0x00000000 },
218 { CX2072X_ANALOG_TEST13, 0x00000000 },
219 { CX2072X_DIGITAL_TEST1, 0x00000242 },
220 { CX2072X_DIGITAL_TEST11, 0x00000000 },
221 { CX2072X_DIGITAL_TEST12, 0x00000084 },
222 { CX2072X_DIGITAL_TEST15, 0x00000077 },
223 { CX2072X_DIGITAL_TEST16, 0x00000021 },
224 { CX2072X_DIGITAL_TEST17, 0x00000018 },
225 { CX2072X_DIGITAL_TEST18, 0x00000024 },
226 { CX2072X_DIGITAL_TEST19, 0x00000001 },
227 { CX2072X_DIGITAL_TEST20, 0x00000002 },
234 { CX2072X_ANALOG_TEST9, 0x080 }, /* DC offset Calibration */
235 { CX2072X_CODEC_TEST26, 0x65f }, /* Disable the PA */
236 { CX2072X_ANALOG_TEST10, 0x289 }, /* Set the speaker output gain */
237 { CX2072X_CODEC_TEST20, 0xf05 },
238 { CX2072X_CODEC_TESTXX, 0x380 },
239 { CX2072X_CODEC_TEST26, 0xb90 },
240 { CX2072X_CODEC_TEST9, 0x001 }, /* Enable 30 Hz High pass filter */
241 { CX2072X_ANALOG_TEST3, 0x300 }, /* Disable PCBEEP pad */
242 { CX2072X_CODEC_TEST24, 0x100 }, /* Disable SnM mode */
243 { CX2072X_PORTD_PIN_CTRL, 0x020 }, /* Enable PortD input */
244 { CX2072X_GPIO_ENABLE, 0x040 }, /* Enable GPIO7 pin for button */
245 { CX2072X_GPIO_UM_ENABLE, 0x040 }, /* Enable UM for GPIO7 */
246 { CX2072X_UM_RESPONSE, 0x080 }, /* Enable button response */
247 { CX2072X_DIGITAL_TEST12, 0x0c4 }, /* Enable headset button */
248 { CX2072X_DIGITAL_TEST0, 0x415 }, /* Power down class-D during idle */
249 { CX2072X_I2SPCM_CONTROL2, 0x00f }, /* Enable I2S TX */
250 { CX2072X_I2SPCM_CONTROL3, 0x00f }, /* Enable I2S RX */
500 buf[0] = reg >> 8; in cx2072x_reg_raw_write()
501 buf[1] = reg & 0xff; in cx2072x_reg_raw_write()
508 return ret < 0 ? ret : -EIO; in cx2072x_reg_raw_write()
510 return 0; in cx2072x_reg_raw_write()
537 __le32 recv_buf = 0; in cx2072x_reg_read()
545 send_buf[0] = reg >> 8; in cx2072x_reg_read()
546 send_buf[1] = reg & 0xff; in cx2072x_reg_read()
548 msgs[0].addr = client->addr; in cx2072x_reg_read()
549 msgs[0].len = sizeof(send_buf); in cx2072x_reg_read()
550 msgs[0].buf = send_buf; in cx2072x_reg_read()
551 msgs[0].flags = 0; in cx2072x_reg_read()
561 return ret < 0 ? ret : -EIO; in cx2072x_reg_read()
565 return 0; in cx2072x_reg_read()
574 for (i = 0; i < ARRAY_SIZE(mclk_pre_div); i++) { in get_div_from_mclk()
611 pt_sample_per_sync = 0; in cx2072x_config_pll()
637 0x40 | (pre_div_val << 8)); in cx2072x_config_pll()
638 if (frac_div == 0) { in cx2072x_config_pll()
640 regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7, 0x100); in cx2072x_config_pll()
644 frac & 0xfff); in cx2072x_config_pll()
653 if (frac_div == 0) { in cx2072x_config_pll()
655 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16, 0x00); in cx2072x_config_pll()
659 (pt_sample_per_sync << 4) & 0xf0); in cx2072x_config_pll()
664 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST19, 0x01); in cx2072x_config_pll()
665 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST20, 0x02); in cx2072x_config_pll()
667 0x01, 0x01); in cx2072x_config_pll()
670 return 0; in cx2072x_config_pll()
676 unsigned int bclk_rate = 0; in cx2072x_config_i2spcm()
677 int is_i2s = 0; in cx2072x_config_i2spcm()
678 int has_one_bit_delay = 0; in cx2072x_config_i2spcm()
679 int is_frame_inv = 0; in cx2072x_config_i2spcm()
680 int is_bclk_inv = 0; in cx2072x_config_i2spcm()
685 int i2s_right_pause_interval = 0; in cx2072x_config_i2spcm()
699 if (frame_len <= 0) { in cx2072x_config_i2spcm()
704 if (sample_size <= 0) { in cx2072x_config_i2spcm()
711 regdbt2.ulval = 0xac; in cx2072x_config_i2spcm()
720 reg2.r.tx_master = 0; in cx2072x_config_i2spcm()
721 reg3.r.rx_master = 0; in cx2072x_config_i2spcm()
802 reg2.r.tx_dstart_dly = 0; in cx2072x_config_i2spcm()
807 reg4.ulval = 0; in cx2072x_config_i2spcm()
810 reg2.r.tx_slot_1 = 0; in cx2072x_config_i2spcm()
812 reg3.r.rx_slot_1 = 0; in cx2072x_config_i2spcm()
814 reg3.r.rx_slot_2 = 0; in cx2072x_config_i2spcm()
829 reg5.r.i2s_pcm_clk_div_chan_en = 0; in cx2072x_config_i2spcm()
832 regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, 0); in cx2072x_config_i2spcm()
848 regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL2, 0xffffffc0, in cx2072x_config_i2spcm()
850 regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL3, 0xffffffc0, in cx2072x_config_i2spcm()
859 return 0; in cx2072x_config_i2spcm()
871 0x00, 0x10); in afg_power_ev()
876 0x10, 0x10); in afg_power_ev()
880 return 0; in afg_power_ev()
885 CX2072X_PORTD_GAIN_RIGHT, 0, 3, 0, boost_tlv),
887 CX2072X_PORTC_GAIN_RIGHT, 0, 3, 0, boost_tlv),
889 CX2072X_PORTB_GAIN_RIGHT, 0, 3, 0, boost_tlv),
891 CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0, 0x4a, 0, adc_tlv),
893 CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0, 0x4a, 0, adc_tlv),
895 CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0, 0x4a, 0, adc_tlv),
897 CX2072X_DAC1_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
899 CX2072X_DAC1_AMP_GAIN_RIGHT, 7, 1, 0),
901 CX2072X_DAC2_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
902 SOC_SINGLE_TLV("HPF Freq", CX2072X_CODEC_TEST9, 0, 0x3f, 0, hpf_tlv),
904 SOC_SINGLE("PortA HP Amp Switch", CX2072X_PORTA_PIN_CTRL, 7, 1, 0),
920 if (sample_size < 0) in cx2072x_hw_params()
924 if (frame_size < 0) in cx2072x_hw_params()
927 if (cx2072x->mclk_rate == 0) { in cx2072x_hw_params()
973 return 0; in cx2072x_hw_params()
983 return 0; in cx2072x_set_dai_bclk_ratio()
998 return 0; in cx2072x_set_dai_sysclk()
1045 return 0; in cx2072x_set_dai_fmt()
1049 SOC_DAPM_SINGLE("Switch", CX2072X_PORTA_PIN_CTRL, 6, 1, 0);
1052 SOC_DAPM_SINGLE("Switch", CX2072X_PORTE_PIN_CTRL, 6, 1, 0);
1055 SOC_DAPM_SINGLE("Switch", CX2072X_PORTG_PIN_CTRL, 6, 1, 0);
1058 SOC_DAPM_SINGLE("Switch", CX2072X_PORTM_PIN_CTRL, 6, 1, 0);
1061 SOC_DAPM_SINGLE("Switch", CX2072X_PORTB_PIN_CTRL, 5, 1, 0);
1064 SOC_DAPM_SINGLE("Switch", CX2072X_PORTC_PIN_CTRL, 5, 1, 0);
1067 SOC_DAPM_SINGLE("Switch", CX2072X_PORTD_PIN_CTRL, 5, 1, 0);
1070 SOC_DAPM_SINGLE("Switch", CX2072X_PORTE_PIN_CTRL, 5, 1, 0);
1073 SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 0, 1, 0);
1076 SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 1, 1, 0);
1079 SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 2, 1, 0);
1082 SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL2, 3, 1, 0);
1085 SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 0, 1, 0);
1088 SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 1, 1, 0);
1091 SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 2, 1, 0);
1094 SOC_DAPM_SINGLE("Switch", CX2072X_I2SPCM_CONTROL3, 3, 1, 0);
1101 SOC_ENUM_SINGLE(CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1107 SOC_ENUM_SINGLE(CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1113 SOC_ENUM_SINGLE(CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1119 SOC_ENUM_SINGLE(CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1130 SOC_ENUM_SINGLE(CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0, 7, adc1in_sel_text);
1140 SOC_ENUM_SINGLE(CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0, 3, adc2in_sel_text);
1155 .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1162 .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1169 .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1175 {.id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \
1182 SND_SOC_DAPM_AIF_IN("In AIF", "Playback", 0, SND_SOC_NOPM, 0, 0),
1184 SND_SOC_DAPM_SWITCH("I2S DAC1L", SND_SOC_NOPM, 0, 0, &i2sdac1l_ctl),
1185 SND_SOC_DAPM_SWITCH("I2S DAC1R", SND_SOC_NOPM, 0, 0, &i2sdac1r_ctl),
1186 SND_SOC_DAPM_SWITCH("I2S DAC2L", SND_SOC_NOPM, 0, 0, &i2sdac2l_ctl),
1187 SND_SOC_DAPM_SWITCH("I2S DAC2R", SND_SOC_NOPM, 0, 0, &i2sdac2r_ctl),
1190 0, 0xfff, 0x00, 0x03),
1193 0, 0xfff, 0x00, 0x03),
1195 SND_SOC_DAPM_MUX("PortA Mux", SND_SOC_NOPM, 0, 0, &porta_mux),
1196 SND_SOC_DAPM_MUX("PortG Mux", SND_SOC_NOPM, 0, 0, &portg_mux),
1197 SND_SOC_DAPM_MUX("PortE Mux", SND_SOC_NOPM, 0, 0, &porte_mux),
1198 SND_SOC_DAPM_MUX("PortM Mux", SND_SOC_NOPM, 0, 0, &portm_mux),
1201 CX2072X_PORTA_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1204 CX2072X_PORTM_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1207 CX2072X_PORTG_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1209 CX2072X_DAPM_SUPPLY_S("AFG Power", 0, CX2072X_AFG_POWER_STATE,
1210 0, 0xfff, 0x00, 0x03, afg_power_ev,
1213 SND_SOC_DAPM_SWITCH("PortA Out En", SND_SOC_NOPM, 0, 0,
1215 SND_SOC_DAPM_SWITCH("PortE Out En", SND_SOC_NOPM, 0, 0,
1217 SND_SOC_DAPM_SWITCH("PortG Out En", SND_SOC_NOPM, 0, 0,
1219 SND_SOC_DAPM_SWITCH("PortM Out En", SND_SOC_NOPM, 0, 0,
1229 SND_SOC_DAPM_AIF_OUT("Out AIF", "Capture", 0, SND_SOC_NOPM, 0, 0),
1231 SND_SOC_DAPM_SWITCH("I2S ADC1L", SND_SOC_NOPM, 0, 0, &i2sadc1l_ctl),
1232 SND_SOC_DAPM_SWITCH("I2S ADC1R", SND_SOC_NOPM, 0, 0, &i2sadc1r_ctl),
1233 SND_SOC_DAPM_SWITCH("I2S ADC2L", SND_SOC_NOPM, 0, 0, &i2sadc2l_ctl),
1234 SND_SOC_DAPM_SWITCH("I2S ADC2R", SND_SOC_NOPM, 0, 0, &i2sadc2r_ctl),
1237 0, 0xff, 0x00, 0x03),
1239 0, 0xff, 0x00, 0x03),
1241 SND_SOC_DAPM_MUX("ADC1 Mux", SND_SOC_NOPM, 0, 0, &adc1_mux),
1242 SND_SOC_DAPM_MUX("ADC2 Mux", SND_SOC_NOPM, 0, 0, &adc2_mux),
1245 CX2072X_PORTB_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1247 CX2072X_PORTC_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1249 CX2072X_PORTD_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1251 CX2072X_PORTE_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1253 CX2072X_MIXER_POWER_STATE, 0, 0xfff, 0x00, 0x03),
1255 SND_SOC_DAPM_MIXER("Widget15 Mixer", SND_SOC_NOPM, 0, 0,
1257 SND_SOC_DAPM_SWITCH("PortB In En", SND_SOC_NOPM, 0, 0, &portbinen_ctl),
1258 SND_SOC_DAPM_SWITCH("PortC In En", SND_SOC_NOPM, 0, 0, &portcinen_ctl),
1259 SND_SOC_DAPM_SWITCH("PortD In En", SND_SOC_NOPM, 0, 0, &portdinen_ctl),
1260 SND_SOC_DAPM_SWITCH("PortE In En", SND_SOC_NOPM, 0, 0, &porteinen_ctl),
1262 SND_SOC_DAPM_MICBIAS("Headset Bias", CX2072X_ANALOG_TEST11, 1, 0),
1263 SND_SOC_DAPM_MICBIAS("PortB Mic Bias", CX2072X_PORTB_PIN_CTRL, 2, 0),
1264 SND_SOC_DAPM_MICBIAS("PortD Mic Bias", CX2072X_PORTD_PIN_CTRL, 2, 0),
1265 SND_SOC_DAPM_MICBIAS("PortE Mic Bias", CX2072X_PORTE_PIN_CTRL, 2, 0),
1353 regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0); in cx2072x_set_bias_level()
1357 return 0; in cx2072x_set_bias_level()
1374 regmap_write(cx2072x->regmap, CX2072X_GPIO_STICKY_MASK, 0x1f); in cx2072x_enable_jack_detect()
1377 regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24); in cx2072x_enable_jack_detect()
1380 regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x80); in cx2072x_enable_jack_detect()
1383 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST15, 0x73); in cx2072x_enable_jack_detect()
1386 regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST12, 0x300); in cx2072x_enable_jack_detect()
1389 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST1, 0); in cx2072x_enable_jack_detect()
1404 regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0); in cx2072x_disable_jack_detect()
1405 regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0); in cx2072x_disable_jack_detect()
1413 unsigned int type = 0; in cx2072x_jack_status_check()
1414 int state = 0; in cx2072x_jack_status_check()
1422 if (jack == 0x80) { in cx2072x_jack_status_check()
1425 if (type & 0x8) { in cx2072x_jack_status_check()
1428 if (type & 0x2) in cx2072x_jack_status_check()
1432 * Nokia headset (type & 0x4) and in cx2072x_jack_status_check()
1440 regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24); in cx2072x_jack_status_check()
1444 dev_dbg(codec->dev, "CX2072X_HSDETECT type=0x%X,Jack state = %x\n", in cx2072x_jack_status_check()
1465 return 0; in cx2072x_set_jack()
1480 return 0; in cx2072x_set_jack()
1499 regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0); in cx2072x_probe()
1506 0x20, 0x20); in cx2072x_probe()
1509 0x84, 0xff); in cx2072x_probe()
1514 return 0; in cx2072x_probe()
1546 return 0; in cx2072x_dsp_dai_probe()
1624 return 0; in cx2072x_runtime_suspend()
1657 cx2072x->bclk_ratio = 0; in cx2072x_i2c_probe()
1674 if (ret < 0) in cx2072x_i2c_probe()
1680 return 0; in cx2072x_i2c_probe()
1689 { "cx20721", 0 },
1690 { "cx20723", 0 },
1697 { "14F10720", 0 },