Lines Matching +full:15 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5651.h -- RT5651 ALSA SoC audio driver
12 #include <dt-bindings/sound/rt5651.h>
19 /* I/O - Output */
23 /* I/O - Input */
28 /* I/O - ADC/DAC/DMIC */
35 /* Mixer - D-D */
48 /* Mixer - ADC */
53 /* Mixer - DAC */
72 /* Format - ADC/DAC */
82 /* Function - Analog */
99 /* Function - Digital */
176 #define RT5651_L_MUTE (0x1 << 15)
177 #define RT5651_L_MUTE_SFT 15
190 #define RT5651_EN_DFO (0x1 << 15)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
206 #define RT5651_INL_SEL_SFT 15
207 #define RT5651_INL_SEL_IN4P (0x0 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
251 #define RT5651_M_MONO_ADC_L (0x1 << 15)
252 #define RT5651_M_MONO_ADC_L_SFT 15
313 #define RT5651_M_ADCMIX_L (0x1 << 15)
314 #define RT5651_M_ADCMIX_L_SFT 15
331 #define RT5651_M_DAC_R1_MIXL (0x1 << 9)
332 #define RT5651_M_DAC_R1_MIXL_SFT 9
359 #define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
360 #define RT5651_STO_DD_R2_L_VOL_SFT 9
375 #define RT5651_M_STO_L_DAC_L (0x1 << 15)
376 #define RT5651_M_STO_L_DAC_L_SFT 15
387 #define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
388 #define RT5651_M_DAC_R2_DAC_R_SFT 9
393 #define RT5651_RXDP_SRC_MASK (0x1 << 15)
394 #define RT5651_RXDP_SRC_SFT 15
395 #define RT5651_RXDP_SRC_NOR (0x0 << 15)
396 #define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
466 #define RT5651_PDM_L_SEL_MASK (0x1 << 15)
467 #define RT5651_PDM_L_SEL_SFT 15
468 #define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
469 #define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
498 #define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
616 #define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
617 #define RT5651_M_DAC_R1_SPM_L_SFT 15
640 #define RT5651_M_DAC_R2_MM (0x1 << 15)
641 #define RT5651_M_DAC_R2_MM_SFT 15
670 #define RT5651_M_IN2_L_OM_L (0x1 << 9)
671 #define RT5651_M_IN2_L_OM_L_SFT 9
700 #define RT5651_M_IN2_R_OM_R (0x1 << 9)
701 #define RT5651_M_IN2_R_OM_R_SFT 9
714 #define RT5651_M_DAC_L1_LM (0x1 << 15)
715 #define RT5651_M_DAC_L1_LM_SFT 15
726 #define RT5651_PWR_I2S1 (0x1 << 15)
727 #define RT5651_PWR_I2S1_BIT 15
740 #define RT5651_PWR_ADC_STO1_F (0x1 << 15)
741 #define RT5651_PWR_ADC_STO1_F_BIT 15
748 #define RT5651_PWR_PDM (0x1 << 9)
749 #define RT5651_PWR_PDM_BIT 9
752 #define RT5651_PWR_VREF1 (0x1 << 15)
753 #define RT5651_PWR_VREF1_BIT 15
781 #define RT5651_PWR_BST1 (0x1 << 15)
782 #define RT5651_PWR_BST1_BIT 15
789 #define RT5651_PWR_PLL (0x1 << 9)
790 #define RT5651_PWR_PLL_BIT 9
805 #define RT5651_PWR_OM_L (0x1 << 15)
806 #define RT5651_PWR_OM_L_BIT 15
823 #define RT5651_PWR_IN1_L (0x1 << 9)
824 #define RT5651_PWR_IN1_L_BIT 9
833 #define RT5651_I2S_MS_MASK (0x1 << 15)
834 #define RT5651_I2S_MS_SFT 15
835 #define RT5651_I2S_MS_M (0x0 << 15)
836 #define RT5651_I2S_MS_S (0x1 << 15)
909 #define RT5651_DMIC_1_EN_MASK (0x1 << 15)
910 #define RT5651_DMIC_1_EN_SFT 15
911 #define RT5651_DMIC_1_DIS (0x0 << 15)
912 #define RT5651_DMIC_1_EN (0x1 << 15)
930 #define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
931 #define RT5651_TDM_INTEL_SEL_SFT 15
932 #define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
933 #define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
950 #define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
951 #define RT5651_TDM_ADC_SEL_SFT 9
952 #define RT5651_TDM_ADC_SEL_NOR (0x0 << 9)
953 #define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
984 #define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
985 #define RT5651_TDM_LRCK_POL_SEL_SFT 15
986 #define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
987 #define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
1004 #define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1005 #define RT5651_TDM_END_EDGE_EN_SFT 9
1095 #define RT5651_STO1_T_MASK (0x1 << 15)
1096 #define RT5651_STO1_T_SFT 15
1097 #define RT5651_STO1_T_SCLK (0x0 << 15)
1098 #define RT5651_STO1_T_LRCK1 (0x1 << 15)
1107 #define RT5651_DMIC_1_M_MASK (0x1 << 9)
1108 #define RT5651_DMIC_1_M_SFT 9
1109 #define RT5651_DMIC_1_M_NOR (0x0 << 9)
1110 #define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1113 #define RT5651_STO1_ASRC_EN (0x1 << 15)
1114 #define RT5651_STO1_ASRC_EN_SFT 15
1186 #define RT5651_SMT_TRIG_MASK (0x1 << 15)
1187 #define RT5651_SMT_TRIG_SFT 15
1188 #define RT5651_SMT_TRIG_DIS (0x0 << 15)
1189 #define RT5651_SMT_TRIG_EN (0x1 << 15)
1190 #define RT5651_HP_L_SMT_MASK (0x1 << 9)
1191 #define RT5651_HP_L_SMT_SFT 9
1192 #define RT5651_HP_L_SMT_DIS (0x0 << 9)
1193 #define RT5651_HP_L_SMT_EN (0x1 << 9)
1305 #define RT5651_MIC1_BS_MASK (0x1 << 15)
1306 #define RT5651_MIC1_BS_SFT 15
1307 #define RT5651_MIC1_BS_9AV (0x0 << 15)
1308 #define RT5651_MIC1_BS_75AV (0x1 << 15)
1317 #define RT5651_MIC1_OVTH_MASK (0x3 << 9)
1318 #define RT5651_MIC1_OVTH_SFT 9
1319 #define RT5651_MIC1_OVTH_600UA (0x0 << 9)
1320 #define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1321 #define RT5651_MIC1_OVTH_2000UA (0x2 << 9)
1360 #define RT5651_EQ_SRC_MASK (0x1 << 15)
1361 #define RT5651_EQ_SRC_SFT 15
1362 #define RT5651_EQ_SRC_DAC (0x0 << 15)
1363 #define RT5651_EQ_SRC_ADC (0x1 << 15)
1433 #define RT5651_MT_MASK (0x1 << 15)
1434 #define RT5651_MT_SFT 15
1435 #define RT5651_MT_DIS (0x0 << 15)
1436 #define RT5651_MT_EN (0x1 << 15)
1439 #define RT5651_ALC_P_MASK (0x1 << 15)
1440 #define RT5651_ALC_P_SFT 15
1441 #define RT5651_ALC_P_DAC (0x0 << 15)
1442 #define RT5651_ALC_P_ADC (0x1 << 15)
1512 #define RT5651_JD_SPL_MASK (0x1 << 9)
1513 #define RT5651_JD_SPL_SFT 9
1514 #define RT5651_JD_SPL_DIS (0x0 << 9)
1515 #define RT5651_JD_SPL_EN (0x1 << 9)
1538 #define RT5651_JD_TRG_SEL_MASK (0x7 << 9)
1539 #define RT5651_JD_TRG_SEL_SFT 9
1540 #define RT5651_JD_TRG_SEL_GPIO (0x0 << 9)
1541 #define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1542 #define RT5651_JD_TRG_SEL_JD1_2 (0x2 << 9)
1543 #define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
1544 #define RT5651_JD_TRG_SEL_JD3 (0x4 << 9)
1553 #define RT5651_IRQ_JD_MASK (0x1 << 15)
1554 #define RT5651_IRQ_JD_SFT 15
1555 #define RT5651_IRQ_JD_BP (0x0 << 15)
1556 #define RT5651_IRQ_JD_NOR (0x1 << 15)
1565 #define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1566 #define RT5651_JD1_1_IRQ_EN_SFT 9
1585 #define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1586 #define RT5651_IRQ_MB1_OC_SFT 15
1587 #define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1588 #define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1604 #define RT5651_STA_JD3 (0x1 << 15)
1605 #define RT5651_STA_JD3_BIT 15
1616 #define RT5651_STA_GP5 (0x1 << 9)
1617 #define RT5651_STA_GP5_BIT 9
1630 #define RT5651_GP1_PIN_MASK (0x1 << 15)
1631 #define RT5651_GP1_PIN_SFT 15
1632 #define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1633 #define RT5651_GP1_PIN_IRQ (0x1 << 15)
1638 #define RT5651_GPIO_M_MASK (0x1 << 9)
1639 #define RT5651_GPIO_M_SFT 9
1640 #define RT5651_GPIO_M_FLT (0x0 << 9)
1641 #define RT5651_GPIO_M_PH (0x1 << 9)
1688 #define RT5651_GP4_P_MASK (0x1 << 9)
1689 #define RT5651_GP4_P_SFT 9
1690 #define RT5651_GP4_P_NOR (0x0 << 9)
1691 #define RT5651_GP4_P_INV (0x1 << 9)
1768 #define RT5651_SCB_SWAP_MASK (0x1 << 15)
1769 #define RT5651_SCB_SWAP_SFT 15
1770 #define RT5651_SCB_SWAP_DIS (0x0 << 15)
1771 #define RT5651_SCB_SWAP_EN (0x1 << 15)
1778 #define RT5651_BB_MASK (0x1 << 15)
1779 #define RT5651_BB_SFT 15
1780 #define RT5651_BB_DIS (0x0 << 15)
1781 #define RT5651_BB_EN (0x1 << 15)
1788 #define RT5651_M_BB_L_MASK (0x1 << 9)
1789 #define RT5651_M_BB_L_SFT 9
1800 #define RT5651_M_MP3_L_MASK (0x1 << 15)
1801 #define RT5651_M_MP3_L_SFT 15
1830 #define RT5651_3D_CF_MASK (0x1 << 15)
1831 #define RT5651_3D_CF_SFT 15
1832 #define RT5651_3D_CF_DIS (0x0 << 15)
1833 #define RT5651_3D_CF_EN (0x1 << 15)
1848 #define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1849 #define RT5651_M_3D_HRTF_SFT 9
1858 #define RT5651_2ND_HPF_MASK (0x1 << 15)
1859 #define RT5651_2ND_HPF_SFT 15
1860 #define RT5651_2ND_HPF_DIS (0x0 << 15)
1861 #define RT5651_2ND_HPF_EN (0x1 << 15)
1890 #define RT5651_DC_CAL_MASK (0x1 << 9)
1891 #define RT5651_DC_CAL_SFT 9
1892 #define RT5651_DC_CAL_DIS (0x0 << 9)
1893 #define RT5651_DC_CAL_EN (0x1 << 9)
1919 #define RT5651_SV_MASK (0x1 << 15)
1920 #define RT5651_SV_SFT 15
1921 #define RT5651_SV_DIS (0x0 << 15)
1922 #define RT5651_SV_EN (0x1 << 15)
1949 #define RT5651_ZCD_HP_MASK (0x1 << 15)
1950 #define RT5651_ZCD_HP_SFT 15
1951 #define RT5651_ZCD_HP_DIS (0x0 << 15)
1952 #define RT5651_ZCD_HP_EN (0x1 << 15)
1977 #define RT5651_3D_SPK_MASK (0x1 << 15)
1978 #define RT5651_3D_SPK_SFT 15
1979 #define RT5651_3D_SPK_DIS (0x0 << 15)
1980 #define RT5651_3D_SPK_EN (0x1 << 15)
1989 #define RT5651_WND_MASK (0x1 << 15)
1990 #define RT5651_WND_SFT 15
1991 #define RT5651_WND_DIS (0x0 << 15)
1992 #define RT5651_WND_EN (0x1 << 15)
2015 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2017 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */