Lines Matching full:intel

62 - intel: env vars doc out of date
64 - Flickering Intel Uhd 620 Graphics
73 - [vulkan][intel] Implement VK_VALVE_mutable_descriptor_type
79 - FrontFacing input is broken on Intel/Vulkan
113 - intel/vec4: Rework texture handling to not use \`ir_texture_opcode`
559 - intel/fs: Consider nir_var_mem_image for TGM fences
562 - intel/compiler: Rename vec4 test fixtures
563 - intel/compiler: Build all tests in a single binary
575 - intel/compiler: Add helpers to select SIMD for compute shaders
576 - intel/compiler: Use SIMD selection helpers for CS
577 - intel/compiler: Use SIMD selection helpers for variable workgroup size
578 - intel/compiler: Don't use SIMD larger than needed for workgroup
582 - intel/compiler: Make brw_nir_populate_wm_prog_data() static
583 - intel/compiler: Use gl_shader_stage_uses_workgroup() helpers
585 - intel/genxml: Add Mesh Shading structures
586 - intel/genxml: Inline the BODY structs into the instructions
587 - intel/dev: Add an intel_device_info::has_mesh_shading bit
588 - intel/blorp: Add option to emit packets that disable Mesh
601 - intel: Add INTEL_DEBUG=task,mesh
602 - intel/compiler: Properly lower WorkgroupId for Task/Mesh
603 - intel/compiler: Handle per-primitive inputs in FS
604 - intel/compiler: Don't stage Task/Mesh outputs in registers
605 - intel/compiler: Don't lower Mesh/Task I/O to temporaries
606 - intel/compiler: Add structs to hold TUE/MUE
607 - intel/compiler: Make MUE available when setting up FS URB access
608 - intel/compiler: Export brw_nir_lower_simd
609 - intel/compiler: Add backend compiler basics for Task/Mesh
610 - intel/compiler: Lower Task/Mesh local_invocation_{id,index}
611 - intel/compiler: Implement Task Output and Mesh Input
612 - intel/compiler: Implement Mesh Output
615 - intel/compiler: Use a struct for brw_compile_tcs parameters
616 - intel/compiler: Use a struct for brw_compile_tes parameters
617 - intel/compiler: Use a struct for brw_compile_gs parameters
618 - intel/compiler: Use a struct for brw_compile_bs parameters
633 - intel/fs/xehp: Add unit test for handling of RaR deps across multiple pipelines.
636 - intel: Only reserve space for Compute Engine out of URB in Gfx12LP
637 - intel/compiler: Have specific mesh handling in calculate_urb_setup()
638 - intel/compiler: Merge Per-Primitive attribute handling in Mesh case
639 - compiler, intel: Add gl_shader_stage_is_mesh()
640 - intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH
641 - intel/common: Add helper for URB allocation in Mesh pipeline
644 - intel/dev: Enable Mesh Shading for DG2
942 - intel/genxml: cleanup video xml collisions.
943 - intel/genxml: fix some missing address from the 75 xml
944 - intel/genxml: align QM field names across gens.
945 - intel/genxml: fix Picure->Picture typo
946 - intel/genxml: fix gen6 LD->VLD typo.
947 - intel/genxml: generate video headers
962 - intel/compiler: drop glsl options from brw_compiler
974 - intel/compiler: drop shader_info.h from compiler header
975 - intel/crocus: push main/macros.h out to the users
1029 - intel/compiler: remove gfx6 gather wa from backend.
1030 - intel/compiler: don't lower swizzles in backend.
1031 - intel/compiler: drop unused decleration
1052 - intel/genxml/gen4-5: fix more Raster Operation in BLT to be a uint
1077 - intel/compiler: add clamp_pointside to vs/tcs/tes keys.
1085 - intel/brw: drop gl header from the brw backend.
1124 - intel/perf: use a function to do common allocations
1125 - meson: start building intel earlier.
1126 - mesa/st: move intel blackhole noop enable to frontend
1467 - intel: Add missing dep of gen_*_header.py on utils.py.
1535 - pps: increase intel.cfg buffer size
1550 - intel/fs/xehp: Teach SWSB pass about the exec pipeline of FS_OPCODE_PACK_HALF_2x16_SPLIT.
1551 - intel/fs: Add physical fall-through CFG edge for unconditional BREAK instruction.
1552 - intel/dev: Fix size of device info num_subslices array.
1553 - intel/dev: Add support for pixel pipe subslice accounting on multi-slice GPUs.
1554 - intel/dev: Implement DG2 restrictions requiring additional DSSes to be disabled.
1555 - intel/xehp: Implement XeHP workaround Wa_14013910100.
1556 - intel/xehp: Implement XeHP workaround Wa_14014148106.
1557 - intel/xehp: Update 3DSTATE_PS maximum number of threads per PSD.
1558 - intel/fs: Don't assume packed dispatch for fragment shaders on XeHP.
1559 - intel/blorp/gfx12+: Drop unnecessary state cache invalidation from binding table setup.
1560 - intel/genxml: Fix SLICE_HASH_TABLE struct on XeHP.
1562 - intel: Move pixel hashing table computation into common header file.
1563 - intel: Minimal calculation of pixel hash table for arbitrary number of pixel pipes.
1564 - intel: Rename intel_compute_pixel_hash_table() to intel_compute_pixel_hash_table_3way().
1567 - intel/xehp: Switch to coarser cross-slice pixel hashing with table permutation.
1569 - intel/fs/xehp: Merge repeated in-order read dependencies instead of replacement.
1570 - intel/fs: Move legal exec type calculation into helper function in lower_regioning pass.
1571 - intel/fs: Teach the lower_regioning pass how to split instructions of unsuported exec type.
1572 - intel/fs: Take into account region strides during SIMD lowering decision of SHUFFLE.
1573 - intel/fs: Fix destination suboffset calculations for non-trivial strides in SHUFFLE codegen.
1574 - intel/fs: Perform 64-bit SHUFFLE lowering in the lower_regioning pass.
1575 - intel/fs: Perform 64-bit SEL_EXEC lowering in the lower_regioning pass.
1576 - intel/fs: Honor strided source regions specified by the IR for CLUSTER_BROADCAST.
1577 - intel/fs: Perform 64-bit CLUSTER_BROADCAST lowering in the lower_regioning pass.
1637 - intel/compiler/test: Fix build with GCC 7
1729 - intel/compiler: Don't predicate a WHILE if there is a CONT
1730 - intel/compiler: Don't store "scalar stage" bits on Gfx8 or Gfx9
1731 - intel/stub: Suppress warnings about DRM_I915_QUERY_PERF_CONFIG
1732 - intel/stub: Implement DRM_I915_QUERY_ENGINE_INFO
1733 - intel/stub: Implement DRM_I915_QUERY_MEMORY_REGIONS
1734 - intel/stub: Implement I915_PARAM_HAS_USERPTR_PROBE
1735 - intel/fs: Use HF as destination type for F32TOF16 in fquantize2f16
1741 - intel/stub: Silence "initialized field overwritten" warning
1742 - intel/stub: Implement shell versions of DRM_I915_GEM_GET_TILING and DRM_I915_SEM_GET_TILING
1743 - intel/fs: Fix gl_FrontFacing optimization on Gfx12+
1754 - intel/fs: Don't optimize out 1.0*x and -1.0*x
1836 - intel/nir: also allow unknown format for getting the size of a storage image
1850 - intel/compiler: make CLUSTER_BROADCAST always deal with integers
1905 - intel/fs: Stop emitting TGM fences for nir_var_mem_ssbo
1934 - intel: Add has_bit6_swizzle to devinfo
1982 - intel/fs,vec4: Drop uniform compaction and pull constant support
1983 - intel/fs,vec4: Drop support for shader time
1984 - intel/blorp: Stop depending on prog_data binding tables
1985 - intel/fs,vec4: Drop prog_data binding tables
1986 - intel/compiler: Get rid of wm_prog_key::frag_coord_adds_sample_pos
1987 - intel/fs: Drop high_quality_derivatives
1989 - intel/dev: Add gtt_size to devinfo
1996 - intel/fs: Return fs_reg directly from builtin setup helpers
1997 - intel/fs: Rework emit_samplepos_setup()
1998 - intel/fs: Implement the sample_pos_or_center system value
2001 - intel/fs: Be more conservative in split_virtual_grfs
2002 - intel/fs: Use OPT() for split_virtual_grfs
2003 - intel/eu: Don't double-loop as often in brw_set_uip_jip
2004 - Revert "intel/fs: Do cmod prop again after scheduling"
2005 - intel/fs: Reset instruction order before re-scheduling
2006 - intel/fs: Add a NONE scheduling mode
2014 - intel/compiler: Stop using GLuint in brw_compiler.h
2015 - intel/fs: Use compare_func for wm_prog_key::alpha_test_func
2284 - intel: provide pci bus and dev info in base device struct
2285 - intel: use PCI info to compute device uuid
2287 - intel: dump PCI info in intel_dev_info
2288 - intel: remove chipset_id
2289 - intel: add swizzle flag into driver uuid
2313 - intel/genxml: Update genxml to support tessellation/geometry distribution
2314 - intel/dev/test: Assert (verx10 / 10) == ver
2317 - intel/genxml/125: Update COMPUTE_WALKER POSTSYNC_DATA struct
2319 - intel/dev: Add platform enum with DG2 G10 & G11
2320 - intel: Add intel_gem_count_engines
2321 - intel: Add intel_gem_create_context_engines
2329 - intel/l3: Make DG1 urb-size exception more generic
2334 - intel/compiler: Use nir_lower_tex_options::lower_offset_filter for tg4 on XeHP
2335 - intel/genxml/12.5: Remove bt-pool enable from 3DSTATE_BINDING_TABLE_POOL_ALLOC
2337 - intel/compiler: Adjust TCS instance-id for dg2+
2339 - intel: Add device info for DG2
2340 - intel: Add \*disabled* device ids for DG2
2341 - intel/devinfo: Adjust L3 banks for DG2
2344 - intel/dev: Add max_threads_per_psd field to devinfo for gfx8+
2346 - intel/dev: Add intel_hwconfig_types.h from random post on the internet
2347 - intel/dev: Add intel_print_hwconfig_table()
2348 - intel/dev: Print urb size with intel_dev_info
2349 - intel/dev: Add intel_device_info::apply_hwconfig
2350 - intel/dev: Set intel_device_info::apply_hwconfig for DG2
2351 - intel/dev: Apply settings from hwconfig if devinfo::apply_hwconfig is set
2352 - intel/dev: Recalculate max_cs_threads after applying hwconfig changes
2353 - intel/gem: Return length from intel_i915_query_alloc
2354 - intel/dev: Add DG1 PCI id 0x4909
2355 - intel/dev: Add device ids for ADL-N
2356 - intel/dev: Add device info for RPL
2357 - intel/genxml: Extend length of 3DSTATE_WM_HZ_OP for gfx12.5
2358 - intel/genxml: Extend length of 3DSTATE_DEPTH_BUFFER for gfx12.5
2360 - intel/fs: Assert that old pull-const code is not used if devinfo->has_lsc
2417 - intel: Drop Tigerlake revision 0 workarounds
2419 - intel/genxml: Fix Indirect Object Access Upper Bound on Gfx4
2420 - intel/genxml: Add an "mbz" data type
2421 - intel/genxml: Drop "Hierarchical Depth Buffer MOCS" field
2422 - intel/genxml: Change 3DSTATE_CONSTANT_XS::MOCS to be MBZ on Gfx8.
2458 - intel/genxml: Add an field option for nonzero="true"
2459 - intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+
2460 - intel/genxml: Include blitter commands in gen*_pack.h
2461 - intel/genxml: Allow MI_FLUSH_DW on the blitter
2462 - intel/genxml: Add XY_BLOCK_COPY_BLT on Tigerlake and later.
2464 - intel/genxml: Simplify prefix handling for field value lists
2465 - intel/genxml: Collapse leading underscores on prefixed value defines
2466 - intel/genxml: Fix MI_FLUSH_DW to actually specify the length properly
2467 - intel/genxml: Fix XY_BLOCK_COPY_BLT destination tiling field type
2468 - intel/genxml: Decode VALIGN/HALIGN values in XY_BLOCK_COPY_BLT
2478 - intel/vec4: Use ir_texture_opcode less in emit_texture()
2479 - intel/vec4: Use nir_texop in emit_texture instead of translating
2480 - intel/vec4: Inline emit_texture and move helpers to brw_vec4_nir.cpp
2481 - intel/compiler: Use uppercase enum values in brw_ir_performance.cpp
2482 - intel/fs: Reuse the same FS input slot for VUE header fields.
2486 - intel: Allow copy engine class in intel_gem_create_context_engines()
2487 - intel/genxml: Add XY_BLOCK_COPY_BLT Color Depth enum values
2488 - intel/dev: Add a has_flat_ccs flag
2546 - pps: add an intel config file
2548 - intel/dev: printout timestamp period
2549 - intel/pps: provide accurate min sampling period
2550 - intel/pps: reuse timestamp_frequency from intel_device_info
2551 - intel/dev: fix HSW GT3 number of subslices in slice1
2552 - intel/dev: don't forget to set max_eu_per_subslice in generated topology
2553 - intel/dev: reuse internal functions to set mask
2554 - intel/dev: fix subslice/eu total computations with some fused configurations
2555 - intel/perf: fix perf equation subslice mask generation for gfx12+
2556 - intel/devinfo: use compatible type for ARRAY_SIZE
2557 - intel/devinfo: fix wrong offset computation
2558 - intel: remove 2 preproduction pci-id for ADLS
2559 - intel: move away from booleans to identify platforms
2560 - intel/dev: also test crocus & i915 pci-ids
2565 - intel/fs: fix shader call lowering pass
2567 - intel/perf: add a helper to read timestamp from reports
2569 - intel/ds: drop timestamp correlation code
2570 - intel/perf: track end timestamp of queries
2571 - intel/ds: drop unused constructors
2572 - intel/ds: isolate intel/perf from the pps-producer
2573 - intel/pps: tweak intel config some more
2574 - intel/ds: remove verbose messages
2575 - intel: move timestamp scaling helper to intel/perf
2581 - intel/nir: preserve access value when duping intrinsic
2589 - intel/debug: reclaim 7 unused bits from classic driver
2597 - intel/devinfo: adjust subslice array size
2601 - intel/dev: fixup chv workaround
2603 - intel/devinfo: printout pixel pipes in info printout
2604 - intel/devinfo: printout devinfo struct size
2605 - intel/devinfo: add a helper to check for slice availability
2606 - intel/devinfo: drop num_eus_per_subslice field
2608 - intel/dev: extract slice/subslice total computation
2609 - intel/devinfo: split out l3/pixelpipes counting
2610 - intel/devinfo: deal with i915 topology query change
2611 - intel/fs: disable VRS when omask is written
2615 - intel/dev,perf: Use a single timescale function
2616 - intel/blorp: add measure_end entry point
2618 - intel/ds: reuse intel_ioctl()
2619 - intel/ds: allow user to select metric set at start time
2620 - intel/ds: don't forget to reset upper dword timestamp read
2621 - intel/ds: use the right i915_drm.h include location
2622 - intel/ds: use a per GPU clock ID
2626 - tools/pps: limit intel cfg to 250ms of sampling
2628 - intel/dev: fix ppipe_mask computation
2634 - intel/ci: expected failure for 1.3 with older CTS
2640 - intel/tracepoint: simplify tracepoint descriptions
2646 - intel/dev: details CPS feature support
2650 - intel/compiler: add a new pass to lower shading rate into HW format
2651 - intel/compiler: add primitive rate output support
2655 - intel/fs: don't set allow_sample_mask for CS intrinsics
2656 - intel/nir: fix shader call lowering
2659 - anv/genxml/intel/fs: fix binding shader record entry
2661 - intel/fs: fix total_scratch computation
2713 - intel: fix INTEL_DEBUG environment variable on 32-bit systems
2714 - intel/decoder: Dump Task/Mesh shaders
2716 - intel/compiler: extract brw_nir_load_global_const out of rt code
2717 - intel/compiler: Get mesh_global_addr from the Inline Parameter for Task/Mesh
2718 - intel/compiler: Load draw_id from XP0 in Task/Mesh shaders
2726 - intel/compiler: disable workaround not applicable to gfx >= 11
2740 - intel/compiler: handle gl_[Clip|Cull]Distance in mesh shaders
2741 - intel/compiler: handle gl_[Clip|Cull]Distance from mesh in fragment shaders
2742 - intel/compiler: Use Task/Mesh InlineData for the first few push constants
2750 - intel/compiler: fix array & struct IO lowering in mesh shaders
2752 - intel/compiler: ignore per-primitive attrs when calculating flat input mask
3019 - intel/genxml: capitalize decoder mode select properly
3367 - intel/isl: Allow creating non-Y-tiled ASTC surfaces
3372 - intel/isl: Unify fmt checks in isl_surf_supports_ccs
3375 - intel/isl: Restore CCS_E support for YUYV and UYVY
3377 - intel/isl: Drop extra devinfo checks for CCS support
3378 - intel/isl: Require aux map for some 64K alignment
3379 - intel/blorp: Modify the SKL+ CCS resolve rectangle
3380 - intel/blorp: Modify get_fast_clear_rect for XeHP
3402 - intel/isl: Rework HiZ image align calculations
3403 - intel/isl: Update comment for the XeHP HiZ block
3404 - intel/isl: Use a new HiZ format on XeHP+
3405 - intel/isl: Require Y-tiling for depth on gfx4-5
3406 - intel/isl: Allow HiZ with Tile4/64 surfaces
3407 - intel/isl: Return false more in isl_surf_get_hiz_surf
3410 - intel: Rename the PSD bit in PIPE_CONTROL for XeHP
3414 - intel/isl: Don't check pitch in isl_surf_get_mcs_surf
3415 - intel/isl: Strengthen MCS SINT format restriction
3416 - Revert "intel/isl: Don't reconfigure aux surfaces for MCS"
3417 - intel/gen125.xml: Increase Auxiliary Surface Pitch
3418 - intel/isl: Allow creating MCS in Tile4 memory
3429 - intel/isl: Support YUV pipe-to-isl format mapping
3432 - intel: Rename a RenderCompressionFormat field
3433 - intel/isl: Support the XeHP media compression format
3438 - intel/isl: Simplify Z-buffer tiling config during emit
3439 - intel/isl: Fix depth buffer TiledSurface programming
3440 - intel/isl: Add more PRM text for HiZ/STC requirement
3483 - intel/fs: Assert the GPU supports 64bit ops if present at lower_scoreboard time.
3661 - intel/compiler: Assert that unsupported tg4 offsets were lowered for XeHP
3662 - intel: Emit 3DSTATE_BINDING_TABLE_POOL_ALLOC for XeHP
3823 - intel/fs: OpImageQueryLod does not support arrayed images as an operand
3867 - intel/compiler: Set correct cache policy for A64 byte scattered read
3868 - intel/genxml: Add new Primitive ID Not Required bit field to 3DSTATE_DS
3869 - intel/compiler: Track primitive id in domain/evaluation shader
3874 - intel/compiler: Set correct return format for brw_SAMPLE
3875 - intel/compiler: Don't hardcode padding source type to 32bit
3876 - intel/compiler: Fix instruction size written calculation
3877 - intel/compiler: Add helper to support half float payload with padding
3878 - intel/fs: Define and set correct sampler simd mode
3879 - intel/compiler: Prepare disasm for 16-bit sampler params
3881 - intel/genxml: Add L1 Cache Control bit field
3882 - intel/genxml: Add Un-Typed Data-Port Cache Flush field to pipe control
4096 - intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
4264 - intel/compiler: Handle new sampler descriptor fields for 16bit sampler
4265 - intel/compiler/fs: Add support for 16-bit sampler msg payload
4266 - intel/compiler: Demote sampler params to 16-bit for CMS/UMS/MCS
4267 - intel/compiler: Prepare ld2dms_w for 4 mcs components
4268 - intel/compiler: Add new variant for TXF_CMS_W
4269 - intel/compiler: Deprecate ld2dms and use ld2dms_w instead
4278 - intel/fs: Fix a cmod prop bug when cmod is set to inst that doesn't support it
4309 - intel/compiler: Change selected_simd return type to int.
4310 - intel/compiler: Initialize SIMDSelectionTest member error.