Lines Matching full:intel

64 - The Finals fails to launch with DX12 on Intel Arc unless "force_vk_vendor" is set to -1.
74 - intel: Require 64KB alignment when using CCS and multiple engines
84 - Large regression in \`glbench --tests context` on Intel
92 - Compiling Mesa with X in custom prefix fails in Intel Vulkan driver
213 - hasvk: Support builiding on non-Intel
214 - crocus: Support building on non-Intel
534 - intel/l3: Adjust URB weight calculation for gfx12.5+.
673 - intel/compiler: Remove unused parameter from brw_nir_adjust_payload()
674 - intel/compiler: Take more precise params in brw_nir_optimize()
675 - intel/compiler: Remove unused parameter from brw_nir_analyze_ubo_ranges()
676 - intel/compiler: Clarify the asserts in nir_load_workgroup_id lowering
677 - intel/compiler: Rework opt_split_sends to not rely/modify LOAD_PAYLOAD
678 - intel/compiler: Re-enable opt_zero_samples() for Gfx7+
679 - intel/compiler: Re-enable opt_zero_samples() in many cases for Gfx12.5
680 - intel/compiler: Remove is_tex()
681 - intel/compiler: Use linear allocator in parts of brw_schedule_instructions
682 - intel/compiler: Remove reference to brw_isa_info from schedule_node
683 - intel/compiler: Allocate all schedule_nodes at once
684 - intel/compiler: Use array to iterate the scheduler nodes
685 - intel/compiler: Add only available instructions to scheduling list
686 - intel/compiler: Extract scheduling related basic functions
687 - intel/compiler: Cache issue_time information
688 - intel/compiler: Remove virtual calls from scheduler
689 - intel/compiler: Move FS specific fields to fs_instruction_scheduler
690 - intel/compiler: Merge child/latency arrays in schedule_node
691 - intel/compiler: Tidy up code in scheduler related to reads_remaining
692 - intel/compiler: Move earlier scheduler code that is not mode-specific
693 - intel/compiler: Separate schedule_node temporary data
694 - intel/compiler: Make scheduler classes take an external mem_ctx
695 - intel/compiler: Reuse same scheduler for all pre-RA scheduling modes
696 - intel/compiler: Clear up block instructions before re-adding them
697 - intel/compiler: Simplify allocation of NIR related arrays
698 - intel/compiler: Prefer ctor/dtors in some Google Tests
699 - intel/compiler: Don't use fs_visitor::bld in tests
700 - intel/compiler: Don't use fs_visitor::bld in fs_reg_alloc
701 - intel/compiler: Don't use fs_visitor::bld in thread payload classes
702 - intel/compiler: Add a few more helpers to fs_builder
703 - intel/compiler: Allow dumping CFG to a specific FILE*
704 - intel/compiler: Sort lists of succs and preds in CFG dump output
705 - intel/compiler: Add a few tests to opt_predicated_break
708 - intel/compiler: Refactor program exit in intel_clc
709 - intel/compiler: Use single variable instead of dynarray
710 - intel/compiler: Fix memory leaks in intel_clc
711 - intel/compiler: Remove the linking step in intel_clc
712 - intel/compiler: Remove unused headers
713 - intel/compiler: Move NIR emission code to brw_fs_nir.cpp
714 - intel/compiler: Make a NIR intrinsic emission functions static
715 - intel/compiler: Make more functions in NIR conversion static
716 - intel/compiler: Make functions for NIR control flow conversion static
717 - intel/compiler: Make setup functions of NIR emission static
718 - intel/compiler: Make non-intrinsic NIR conversion functions static
719 - intel/compiler: Make NIR atomic conversion functions static
720 - intel/compiler: Make NIR resources helpers static
721 - intel/compiler: Move nir_ssa_value into a local structure
722 - intel/compiler: Move remaining NIR conversion fields to nir_to_brw_state
723 - intel/compiler: Stop using fs_visitor::bld field in NIR conversion
724 - intel/compiler: Annotate and use nir_to_brw_state::bld
725 - intel/compiler: Don't use fs_visitor::bld in remaining places
726 - intel/compiler: Remove fs_visitor::bld
727 - intel/compiler: Make fs_visitor not depend on fs_builder
728 - intel/compiler: Make fs_builder include fs_visitor and not the other way
729 - intel/compiler: Add ctor to fs_builder that just takes the shader
730 - intel/compiler: Create and use nir_to_brw() function
731 - intel/compiler: Use reference instead of pointer for nir_to_brw_state
732 - intel/compiler: Use reference instead of pointer for fs_visitor
736 - intel/compiler: Use C helpers to access builtin types
738 - intel/compiler: Use glsl_type C helpers
748 - intel/cmat: Add pass to lower cooperative matrix to subgroup operations
749 - intel/dev: Add cooperative matrix configuration information
754 - intel/fs: Only allocate acp_entry if we are adding one
755 - intel/fs: Use linear allocator in opt_copy_propagation
756 - intel/fs: Use linear allocator in fs_live_variables
758 - intel/compiler: Use INTEL_DEBUG=cs to ask for brw_compiler output
761 - intel/compiler: Fix rebuilding the CFG in fs_combine_constants
974 - intel/compiler: move gen5 final pass to actually be final pass
977 - intel/compiler: fix release build unused variable.
978 - intel/compiler: revert part of "Move earlier scheduler code that is not mode-specific"
988 - intel/compiler: reemit boolean resolve for inverted if on gen5
1168 - intel/ci: fix gl/vk dependencies in hsw jobs
1169 - intel/dev: use libdrm.h wrapper to support builds without libdrm
1183 - intel/perf: fix regex escaping
1184 - intel/ci: fix .hasvk-manual-rules
1245 - intel/ci: fix yaml indentation
1246 - intel/ci: deduplicate common intel files rules
1247 - intel/ci: expand first level of common intel files
1248 - intel/ci: anv changes should only trigger anv jobs
1249 - intel/ci: hasvk changes should only trigger hasvk jobs
1250 - intel/ci: run only the relevant jobs when changing the ci expectations
1428 - nak: Copy the optimization loop from Intel
1939 - intel/vec4: Use MESA_PRIM_* instead of GL_*
2070 - driconf: add Dying Light 2 to Intel XeSS workaround
2071 - driconf: add Witcher3 to Intel XeSS workaround
2083 - intel/l3/gfx11+: Add tile cache partition to intel_l3_config struct.
2084 - intel/l3: Define helper for obtaining the size of an L3 partition in KB.
2085 - intel/l3: Set up L3FullWayAllocationEnable config if ALL partition has over 126 ways.
2086 - intel/dg2: Import L3 cache configurations.
2087 - intel/mtl: Import L3 cache configurations.
2088 - intel/xehp+: Add TBIMR-related genxml definitions.
2089 - intel/xehp+: Import algorithm for TBIMR tiling parameter calculation.
2090 - intel/xehp+: Add dynamic state flags controlling whether TBIMR is enabled during 3D primitives.
2091 - intel/xehp+: Define driconf option for selectively disabling TBIMR.
2095 - intel/xehp: Adjust TBIMR performance chicken bits.
2096 - intel/xehp+: Adjust TBIMR batch size based on slice count.
2097 - intel/xehp+: Use TBIMR tile box check in order to avoid performance regressions.
2098 - intel/xehp: Enable TBIMR by default.
2099 - intel/eu/xe2+: Add support for 10-bit SWSB representation on Xe2+ platforms.
2100 - intel/fs/xe2+: Add comment reminding us to take advantage of the 32 SBID tokens.
2101 - intel/fs/xe2+: Teach SWSB pass about the behavior of double precision instructions.
2102 - intel/fs/xe2+: Handle extended math instructions as in-order in SWSB pass.
2103 - intel/eu/xe2+: Add definition for size of GRF space on Xe2.
2104 - intel/fs/xe2+: Don't special case SEL_EXEC in inferred_exec_pipe().
2105 - intel: Improve N-way pixel hashing computation to handle pixel pipes with asymmetric processing p…
2106 - intel/compiler: Add max_polygons FS compilation parameter.
2107 - intel/compiler: Add multipolygon dispatch fields to brw_wm_prog_data.
2108 - intel/compiler: Add polygon count statistic to brw_compile_stats.
2109 - intel/fs: Add separate constructor of fs_visitor for fragment shaders.
2110 - intel/fs: Map all GS input attributes to ATTR register number 0.
2111 - intel/fs: Map all VS input attributes to ATTR register number 0.
2112 - intel/fs: Map all TES input attributes to ATTR register number 0.
2113 - intel/fs: Assert fs_reg::nr is always zero for ATTR registers in geometry stages.
2114 - intel/fs: Consider ATTR registers with different fs_reg::nr as belonging to disjoint register spa…
2115 - intel/fs: Provide component index explicitly to interp_reg().
2116 - intel/fs: Pass builder to per_primitive_reg().
2117 - intel/fs: Fix fs_reg::component_size() to handle two-dimensional register regions.
2118 - intel/fs: Rework layout of FS vertex setup data in ATTR file to support multi-polygon dispatch.
2119 - intel/fs: Don't copy-propagate ATTR registers in multi-polygon FS shaders when invalid.
2120 - intel/compiler: Don't change types for copies from ATTR file.
2121 - intel/fs/gfx12+: Don't set nir_divergence_single_prim_per_subgroup option for fragment shaders.
2122 - intel/fs/gfx12: Don't consider multipolygon PS to have packed dispatch.
2123 - intel/fs: No need to copy null destinations in lower_simd_width.
2124 - intel/fs: Fix PS thread payload setup for depth_w_coef_reg.
2125 - intel/fs/gfx12: Implement multi-polygon format of back/front-facing flag in PS payload.
2126 - intel/fs/gfx12: Implement multi-polygon format of render target array index in PS payload.
2127 - intel: Add debug flag for enabling dual-SIMD8 fragment shader dispatch.
2128 - intel/compiler: Attempt to build dual-SIMD8 variant of fragment shaders on gfx12+ platforms.
2129 - intel/genxml: Add 3DSTATE_PS definitions needed for dual-SIMD8 dispatch on Gfx12+.
2130 - intel/gfx12: Enable SIMD8 dispatch in 3DSTATE_PS for FS multipolygon dispatch.
2133 - intel/fs/xe2+: Stop building SIMD8 compute-like shaders (CS/BS/TS/MS).
2134 - intel/fs/xe2+: Stop building SIMD8 fragment shaders.
2135 - intel/fs/xe2+: Stop building SIMD8 shaders for geometry stages (VS/TCS/TES/GS).
2136 - intel/eu/xe2+: Add helpers for constructing registers in 512b units.
2137 - intel/fs/xe2+: Implement PS thread payload register offset setup.
2138 - intel/fs/xe2+: Fix for new layout of X/Y pixel coordinates in PS payload.
2139 - intel/fs/xe2+: Update uses of pixel/sample mask from PS thread payload.
2140 - intel/fs/xe2+: Update location of sample ID fields in PS payload.
2141 - intel/fs/xe2+: Update poly info PS payload for new multi-polygon dispatch format.
2142 - intel/fs: Add support for vector payload values to fetch_payload_reg().
2143 - intel/fs/xe2+: Enable new format of barycentrics in PS payload.
2144 - intel/fs/xe2+: Update for new layout of vertex setup data in PS payload.
2145 - intel/fs/xe2+: Implement support for multi-polygon vertex setup data in PS payload.
2146 - intel/fs/xe2+: Implement layout of mesh shading per-primitive inputs in PS thread payloads.
2147 - intel/fs: Plumb shader instead of compiler to get_lowered_simd_width() and friends.
2148 - intel/fs/xe2+: Lower SIMD width of instructions that access ATTR file from SIMD2x8/4x8 FS.
2149 - intel: Add debug flags for enabling Xe2+ multipolygon fragment shader dispatch modes.
2150 - intel/fs/xe2+: Attempt to build quad-SIMD8 and dual-SIMD16 FS variants on Xe2+ platforms.
2151 - intel/xe2+: Implement fragment shader dispatch state setup.
2152 - intel/compiler/xe2: Don't disassemble non-existent fields.
2333 - intel/vec4: Don't emit an empty ELSE
2334 - intel/compiler: Add basic CFG validation
2335 - intel/compiler: Limit scope of cur_endif variable
2336 - intel/compiler: Delete bidirectional block links in opt_predicated_break
2337 - intel/compiler: Don't create extra CFG links in opt_predicated_break
2338 - intel/compiler: Don't create extra CFG links when deleting a block
2339 - intel/compiler: Don't promote CFG link types when removing a block
2340 - intel/fs: Don't add MOV instructions to DO blocks in combine constants
2341 - intel/compiler: Verify that DO is alone in the block
2343 - intel/fs/xe2+: Pass correct dispatch_width to fs_generator for geometry-processing stages.
2344 - intel/cmat: Update get_slice_type for packed slices
2345 - intel/cmat: Add lowering for cmat_insert and cmat_extract
2346 - intel/cmat: Enable packed formats for unary, length, and construct
2347 - intel/cmat: Enable packed formats for binary ops
2348 - intel/cmat: Enable packed formats for scalar ops
2349 - intel/cmat: Add lowering for cmat_bitcast
2350 - intel/cmat: Lower cmat_load and cmat_store
2351 - intel/compiler: Initial bits for DPAS instruction
2352 - intel/disasm: Disassembly support for DPAS
2353 - intel/compiler: Validation for DPAS instructions
2354 - intel/fs: Fix scoreboarding for DPAS
2355 - intel/fs: DPAS lowering
2356 - intel/fs: nir: Add nir_intrinsic_dpas_intel
2362 - intel/dev: Advertise integer configs with saturatingAccumulation too
2363 - intel/dev: Enable VK_KHR_cooperative_matrix on all Gfx9+ GPUs
2364 - intel/cmat: Generate better code for nir_intrinsic_cmat_insert
2365 - intel/compiler: Disable DPAS instructions on MTL
2366 - intel/compiler: Track lower_dpas flag in brw_get_compiler_config_value
2367 - intel/compiler: Track mue_compaction and mue_header_packing flags in brw_get_compiler_config_value
2389 - intel: make CLOCK_TAI optional for non-Linux
2390 - intel: make CLOCK_BOOTTIME optional for non-Linux
2478 - intel/isl: Add a debug option to override modifer list
2479 - intel: Move mod_plane_is_clear_color() into isl
2480 - intel/vulkan: Report clear color in subresource layout
2481 - intel/vulkan: Allow modifiers supporting fast clear
2482 - intel/vulkan: Specify offset when creating aux state tracker
2483 - intel/vulkan: Import aux state tracking buffer
2484 - intel/vulkan: Remove private binding on fast clear region
2485 - intel/vulkan: Use the last 2 dwords of clear color struct
2486 - intel/vulkan: Correct a comment about an offset in fast clear
2487 - intel/vulkan: Update comment of a workaround of modifiers
2488 - intel/vulkan: Add COMPRESSED_CLEAR state in layout translation
2489 - intel/isl: Add Gfx 12.x RC_CCS_CC into modifier scores
2501 - intel/common: add directory prefix to intel_gem.h include
2506 - intel/l3: Use devinfo->urb.size when cfg urb-size is 0.
2508 - intel/dev/wa: Raise error if mesa_defs.json contains unknown platforms
2509 - intel/dev: Rename mtl-m to mtl-u
2510 - intel/dev: Rename mtl-p to mtl-h
2511 - intel/compiler: Define XE2 compiler enum
2512 - intel/genxml: Update COMPUTE_WALKER for xe2
2515 - intel/genxml: Update INTERFACE_DESCRIPTOR_DATA for xe2
2518 - intel/genxml: Update 3DSTATE_TE for xe2
2520 - intel/genxml: Add UNIFIED_COMPRESSION_FORMAT enum for xe2
2522 - anv, blorp, iris, intel/genxml: Update 3DSTATE_VS for xe2
2523 - anv, blorp, iris, intel/genxml: Update 3DSTATE_PS_EXTRA for xe2
2524 - intel/batch_decoder: Update 3DSTATE_PS decoding for xe2
2525 - anv, iris, intel/genxml: Update 3DSTATE_GS for xe2
2526 - anv, iris, intel/genxml: Update 3DSTATE_HS for xe2
2527 - intel/compiler: Pass max_polygons to copy-prop from fs_visitor.
2528 - intel/xe2+: Implement brw_wm_state_simd_width_for_ksp() on Xe2+.
2529 - intel/genxml/gfx125: Move L1_CACHE_CONTROL to enum
2530 - intel/genxml/gfx125: Move STATE_SURFACE_TYPE to enum
2552 - intel: Add more information about the PAT entry used
2553 - intel: Update MTL scanout PAT entry
2554 - intel: Add a write combining PAT entry
2561 - intel/common: Add intel_gem_read_correlate_cpu_gpu_timestamp()
2564 - intel/common/xe: Re implement xe_gem_read_render_timestamp() with xe_gem_read_correlate_cpu_gpu_t…
2566 - intel: Sync xe_drm.h
2567 - intel: Sync xe_drm.h
2569 - intel: Rename PAT entries
2570 - intel: Share function to do device query in Xe KMD
2574 - intel: Add PAT entries for gfx12 and newer
2575 - intel: Sync xe_drm.h
2576 - intel: Enable has_set_pat_uapi for Xe
2582 - intel/dev: Adjust prefetch_size values for Xe2 engines
2585 - intel: Sync xe_drm.h take 2 part 3
2586 - intel/isl: Set mocs.blitter_dst/src for MTL
2591 - intel/genxml/xe2: Update PIPE_CONTROL
2592 - intel/genxml/xe2: Update PIPELINE_SELECT
2593 - intel: Sync xe_drm.h final part
2598 - intel/isl/xe2: Enable route of Sampler LD message to LSC
2730 - intel/compiler: Delete unused emit_dummy_fs()
2731 - intel/compiler: Delete unused repclear shader uniform handling
2732 - intel/compiler: Delete repclear shader's special case for 1 color target
2733 - intel/compiler: Drop unused saturate handling in repclear shader
2734 - intel/compiler: Convert the repclear shader to use send-from-GRF
2735 - intel/compiler: Assert that FS_OPCODE_[REP\_]FB_WRITE is for pre-Gfx7
2746 - intel/fs: Allow omitting the destination of A64 untyped atomics
2747 - intel/fs: Drop opt_register_renaming()
2818 - intel/fs: fix dynamic interpolation mode selection
2821 - intel/fs: Xe2 fix for ExBSO on UGM
2832 - intel/ds: use improved timestamp correlation if available
2834 - intel: fix PXP status check
2840 - intel/fs: fix residency handling on Xe2
2842 - intel/fs: rerun divergence analysis prior to convert_from_ssa
2843 - intel/nir/rt: fix reportIntersection() hitT handling
2848 - intel/decoder: handle 3DPRIMITIVE_EXTENDED in accumulated prints
2849 - intel/blorp: move Wa_18019816803 out of blorp code
2852 - intel/perf: fix querying of configurations
2853 - intel/fs: fix incorrect register flag interaction with dynamic interpolator mode
2854 - intel/fs: reuse set_predicate()
2855 - intel/aux_map: introduce ref count of L1 entries
2859 - intel/ds: add trace of buffer markers
2860 - intel/tools: add hang_replay tool
2861 - intel/hang_replay: add the ability to pass the context image to sim-drm
2862 - intel: add error2hangdump tool
2863 - intel/aubinator_error_decode: bump max buffers to 1024
2864 - intel/error_decode: map i915 gfx12.5 register names to our names
2865 - intel/tools: hang viewer/editor
2872 - intel/hang_replay: fix compile race with generated files
2873 - intel/tools: 32bit compile fixes
2893 - intel/fs: fix depth compute state for unchanged depth layout
2896 - intel/aux_map: fix fallback unmapping range on failure
3185 - intel: remove workaround for preproduction DG2 steppings
3186 - intel/dev: improve descriptions of workaround macros.
3187 - intel/dev: poison macros for workarounds fixed at a stepping
3188 - intel: remove MTL a0 workarounds
3189 - intel/dev: update workaround definitions to latest defect status
3246 - zink: Force 128 fs input components under Venus for Intel
3256 - intel: Only validate inst compaction if debugging a shader stage
3405 - intel/genxml: add the Gen12+ TR-TT registers
3433 - intel/tools: fix compilation of intel_hang_viewer on 32 bits
3560 - intel/compiler: use nir_lower_fp16_casts
3650 - intel/compiler: migrate WA 14013672992 to use WA framework
3658 - intel/dev: Add a bit for when the HW can do a indirect draw/dispatch unroll
3666 - intel/genxml: Add the preferred slm size enum for xe2
3667 - intel: Set a preferred SLM size for LNL
3668 - intel/genxml: Update COMPUTE_WALKER_BODY for xe2
3669 - intel/genxml: Update IDD for new fields
3674 - intel/compiler: use the proper enum type to store the op
3675 - intel/compiler: infer the number of operands using lsc_op_num_data_values
3678 - intel/fs/xe2+: Lift CPS dispatch width restrictions on Xe2+.
3679 - intel/compiler: Update disassembly for new LSC cache enums
3731 - intel/compiler: Adjust assertion in lower_get_buffer_size() for Xe2
3732 - intel/fs: Adjust destination size for image size intrinsic
3733 - intel/fs: Adjust destination size for global load constant on Xe2+
3734 - intel/fs: Adjust destination size for load ubo on Xe2+
3735 - intel/genxml: Add BCS/VD0 aux table base address register
3743 - intel/fs: Check fs_visitor instance before using it
3944 - intel/xe: Correct DRM_XE_EXEC_QUEUE_SET_PROPERTY's ioctl
4041 - intel/fs: Don't optimize DW*1 MUL if it stores value to the accumulator
4042 - intel/compiler: Add variable to dump binaries of all compiled shaders
4043 - intel/disasm: Print half-float values instead of placeholder
4044 - intel/compiler: Set flag reg to 0 when disabling predication
4045 - intel/disasm: Print src1_len correctly depending on ExDesc type
4046 - intel/fs: Set group 0 for Wa_14010017096 MOV instruction
4047 - intel/eu/validate: Validate that the ExecSize is a factor of chosen ChanOff
4048 - intel/tools/i965_asm: Add SWSB handling
4049 - intel/tools/i965_asm: Handle HF immediates
4050 - intel/tools/i965_asm: Handle sync instruction
4051 - intel/tools/i965_asm: Allow neg and abs modifiers on accumulator register
4052 - intel/tools/i965_asm: Don't override flag reg from cond modifier
4053 - intel/tools/i965_asm: Allow src0 and src2 of ternary instructions to be imm
4054 - intel/tools/i965_asm: Implement gfx12 and gfx12.5 send/sendc
4055 - intel/tools/i965_asm: Add dp4a and add3 instructions
4056 - intel/tools/i965_asm: Don't set src0 for break and while on gfx12
4057 - intel/tools/tests: Fix sends indirect argument in gfx9 test
4058 - intel/tools/tests: Unbreak i965_asm tests
4059 - intel/tools/tests: Add i965_asm tests for gfx12 and gfx12.5
4068 - intel/dev: provide intel_device_info_is_adln helper
4072 - intel/dev: fix intel_device_info_is_adln check
4240 - intel/disasm: Remove duplicate variable reg_file
4360 - intel: Remove unused ALIGN macro
4364 - intel: Generate source file with utf-8 encoding from mako template
4393 - intel: Avoid use align as variable, replace it with other names
4394 - intel: Use ALIGN_POT instead of ALIGN inside macro define
4395 - intel: Cleanup duplicate ALIGN macro defines
4396 - intel,crocus,iris: Use align64 instead of ALIGN for 64 bit value parameter
4414 - intel/genxml: Remove 3DSTATE_CLEAR_PARAMS instruction (xe2)
4415 - intel/genxml: update 3DSTATE_WM_HZ_OP instruction (xe2)
4416 - intel/genxml: update 3DSTATE_DEPTH_BUFFER instruction (xe2)
4417 - intel/isl: update 3DSTATE_STENCIL_BUFFER (xe2)
4418 - intel/genxml: Add RENDER_SURFACE_STATE for xe2