Lines Matching full:nir
7 #include "nir/nir.h"
8 #include "nir/nir_xfb_info.h"
9 #include "nir/radv_nir.h"
24 radv_use_vs_prolog(const nir_shader *nir, in radv_use_vs_prolog() argument
27 return gfx_state->vs.has_prolog && nir->info.inputs_read; in radv_use_vs_prolog()
31 radv_use_per_attribute_vb_descs(const nir_shader *nir, in radv_use_per_attribute_vb_descs() argument
35 return stage_key->vertex_robustness1 || radv_use_vs_prolog(nir, gfx_state); in radv_use_per_attribute_vb_descs()
39 gather_load_vs_input_info(const nir_shader *nir, const nir_intrinsic_instr *intrin, struct radv_sha… in gather_load_vs_input_info() argument
57 if (radv_use_per_attribute_vb_descs(nir, gfx_state, stage_key)) in gather_load_vs_input_info()
67 gather_load_fs_input_info(const nir_shader *nir, const nir_intrinsic_instr *intrin, struct radv_sha… in gather_load_fs_input_info() argument
88 const bool per_primitive = nir->info.per_primitive_inputs & BITFIELD64_BIT(location); in gather_load_fs_input_info()
117 gather_intrinsic_load_input_info(const nir_shader *nir, const nir_intrinsic_instr *instr, struct ra… in gather_intrinsic_load_input_info() argument
121 switch (nir->info.stage) { in gather_intrinsic_load_input_info()
123 gather_load_vs_input_info(nir, instr, info, gfx_state, stage_key); in gather_intrinsic_load_input_info()
126 gather_load_fs_input_info(nir, instr, info, gfx_state); in gather_intrinsic_load_input_info()
134 gather_intrinsic_store_output_info(const nir_shader *nir, const nir_intrinsic_instr *instr, in gather_intrinsic_store_output_info() argument
144 switch (nir->info.stage) { in gather_intrinsic_store_output_info()
186 if (nir->info.stage == MESA_SHADER_GEOMETRY) { in gather_intrinsic_store_output_info()
193 unsigned clip_array_mask = BITFIELD_MASK(nir->info.clip_distance_array_size); in gather_intrinsic_store_output_info()
200 gather_push_constant_info(const nir_shader *nir, const nir_intrinsic_instr *instr, struct radv_shad… in gather_push_constant_info() argument
218 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr, struct radv_shader_i… in gather_intrinsic_info() argument
290 gather_push_constant_info(nir, instr, info); in gather_intrinsic_info()
310 gather_intrinsic_load_input_info(nir, instr, info, gfx_state, stage_key); in gather_intrinsic_info()
314 gather_intrinsic_store_output_info(nir, instr, info, consider_force_vrs); in gather_intrinsic_info()
331 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr, struct radv_shader_info *info) in gather_tex_info() argument
348 gather_info_block(const nir_shader *nir, const nir_block *block, struct radv_shader_info *info, in gather_info_block() argument
355 …gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info, gfx_state, stage_key, consider_for… in gather_info_block()
358 gather_tex_info(nir, nir_instr_as_tex(instr), info); in gather_info_block()
367 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info) in gather_xfb_info() argument
371 if (!nir->xfb_info) in gather_xfb_info()
374 const nir_xfb_info *xfb = nir->xfb_info; in gather_xfb_info()
409 radv_get_output_masks(const struct nir_shader *nir, const struct radv_graphics_state_key *gfx_state, in radv_get_output_masks() argument
417 *per_prim_mask = nir->info.outputs_written & nir->info.per_primitive_outputs & ~special_mask; in radv_get_output_masks()
418 *per_vtx_mask = nir->info.outputs_written & ~nir->info.per_primitive_outputs & ~special_mask; in radv_get_output_masks()
421 if (nir->info.stage == MESA_SHADER_MESH && gfx_state->has_multiview_view_index) in radv_get_output_masks()
426 radv_set_vs_output_param(struct radv_device *device, const struct nir_shader *nir, in radv_set_vs_output_param() argument
434 radv_get_output_masks(nir, gfx_state, &per_vtx_mask, &per_prim_mask); in radv_set_vs_output_param()
442 …export_prim_id && info->is_ngg && pdev->info.gfx_level >= GFX10_3 && nir->info.stage == MESA_SHADE… in radv_set_vs_output_param()
445 (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL); in radv_set_vs_output_param()
461 if (nir->info.outputs_written & VARYING_BIT_CLIP_DIST0) in radv_set_vs_output_param()
463 if (nir->info.outputs_written & VARYING_BIT_CLIP_DIST1) in radv_set_vs_output_param()
549 /* Create a mask of driver locations mapped from NIR semantics. */ in radv_gather_unlinked_io_mask()
581 gather_shader_info_vs(struct radv_device *device, const nir_shader *nir, in gather_shader_info_vs() argument
585 if (radv_use_vs_prolog(nir, gfx_state)) { in gather_shader_info_vs()
594 info->vs.use_per_attribute_vb_descs = radv_use_per_attribute_vb_descs(nir, gfx_state, stage_key); in gather_shader_info_vs()
610 …um_verts_per_prim = gfx_state->ia.topology == V_008958_DI_PT_NONE && info->is_ngg && nir->xfb_info; in gather_shader_info_vs()
613 …info->vs.num_linked_outputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.outputs_writt… in gather_shader_info_vs()
623 info->vs.num_outputs = nir->num_outputs; in gather_shader_info_vs()
632 gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir, in gather_shader_info_tcs() argument
637 … nir_gather_tcs_info(nir, &info->tcs.info, nir->info.tess._primitive_mode, nir->info.tess.spacing); in gather_shader_info_tcs()
639 info->tcs.tcs_outputs_read = nir->info.outputs_read; in gather_shader_info_tcs()
640 info->tcs.tcs_outputs_written = nir->info.outputs_written; in gather_shader_info_tcs()
641 info->tcs.tcs_patch_outputs_read = nir->info.patch_inputs_read; in gather_shader_info_tcs()
642 info->tcs.tcs_patch_outputs_written = nir->info.patch_outputs_written; in gather_shader_info_tcs()
643 info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out; in gather_shader_info_tcs()
648 …info->tcs.num_linked_inputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.inputs_read)); in gather_shader_info_tcs()
651 … nir->info.outputs_written & ~(VARYING_BIT_TESS_LEVEL_OUTER | VARYING_BIT_TESS_LEVEL_INNER))); in gather_shader_info_tcs()
653 … radv_gather_unlinked_patch_io_mask(nir->info.outputs_written, nir->info.patch_outputs_written)); in gather_shader_info_tcs()
658 radv_get_tess_wg_info(pdev, &nir->info, gfx_state->ts.patch_control_points, in gather_shader_info_tcs()
667 gather_shader_info_tes(struct radv_device *device, const nir_shader *nir, struct radv_shader_info *… in gather_shader_info_tes() argument
670 info->tes._primitive_mode = nir->info.tess._primitive_mode; in gather_shader_info_tes()
671 info->tes.spacing = nir->info.tess.spacing; in gather_shader_info_tes()
672 info->tes.ccw = nir->info.tess.ccw; in gather_shader_info_tes()
673 info->tes.point_mode = nir->info.tess.point_mode; in gather_shader_info_tes()
674 info->tes.tcs_vertices_out = nir->info.tess.tcs_vertices_out; in gather_shader_info_tes()
676 !!(nir->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER)); in gather_shader_info_tes()
680 nir->info.inputs_read & ~(VARYING_BIT_TESS_LEVEL_OUTER | VARYING_BIT_TESS_LEVEL_INNER))); in gather_shader_info_tes()
682 radv_gather_unlinked_patch_io_mask(nir->info.inputs_read, nir->info.patch_inputs_read)); in gather_shader_info_tes()
685 …info->tes.num_linked_outputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.outputs_writ… in gather_shader_info_tes()
693 info->tes.num_outputs = nir->num_outputs; in gather_shader_info_tes()
835 gather_shader_info_gs(struct radv_device *device, const nir_shader *nir, struct radv_shader_info *i… in gather_shader_info_gs() argument
837 unsigned add_clip = nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4; in gather_shader_info_gs()
838 info->gs.gsvs_vertex_size = (util_bitcount64(nir->info.outputs_written) + add_clip) * 16; in gather_shader_info_gs()
839 info->gs.max_gsvs_emit_size = info->gs.gsvs_vertex_size * nir->info.gs.vertices_out; in gather_shader_info_gs()
841 info->gs.vertices_in = nir->info.gs.vertices_in; in gather_shader_info_gs()
842 info->gs.vertices_out = nir->info.gs.vertices_out; in gather_shader_info_gs()
843 info->gs.input_prim = nir->info.gs.input_primitive; in gather_shader_info_gs()
844 info->gs.output_prim = nir->info.gs.output_primitive; in gather_shader_info_gs()
845 info->gs.invocations = nir->info.gs.invocations; in gather_shader_info_gs()
846 …info->gs.max_stream = nir->info.gs.active_stream_mask ? util_last_bit(nir->info.gs.active_stream_m… in gather_shader_info_gs()
862 … info->gs.num_linked_inputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.inputs_read)); in gather_shader_info_gs()
872 gather_shader_info_mesh(struct radv_device *device, const nir_shader *nir, in gather_shader_info_mesh() argument
877 info->ms.output_prim = nir->info.mesh.primitive_type; in gather_shader_info_mesh()
907 ngg_info->max_out_verts = nir->info.mesh.max_vertices_out; in gather_shader_info_mesh()
910 ngg_info->prim_amp_factor = nir->info.mesh.max_primitives_out; in gather_shader_info_mesh()
918 calc_mesh_workgroup_size(const struct radv_device *device, const nir_shader *nir, struct radv_shade… in calc_mesh_workgroup_size() argument
921 …unsigned api_workgroup_size = ac_compute_cs_workgroup_size(nir->info.workgroup_size, false, UINT32… in calc_mesh_workgroup_size()
936 gather_shader_info_fs(const struct radv_device *device, const nir_shader *nir, in gather_shader_info_fs() argument
941 info->ps.num_inputs = util_bitcount64(nir->info.inputs_read); in gather_shader_info_fs()
942 info->ps.can_discard = nir->info.fs.uses_discard; in gather_shader_info_fs()
944 nir->info.fs.early_fragment_tests || in gather_shader_info_fs()
945 …(nir->info.fs.early_and_late_fragment_tests && nir->info.fs.depth_layout == FRAG_DEPTH_LAYOUT_NONE… in gather_shader_info_fs()
946 nir->info.fs.stencil_front_layout == FRAG_STENCIL_LAYOUT_NONE && in gather_shader_info_fs()
947 nir->info.fs.stencil_back_layout == FRAG_STENCIL_LAYOUT_NONE); in gather_shader_info_fs()
948 info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage; in gather_shader_info_fs()
949 info->ps.depth_layout = nir->info.fs.depth_layout; in gather_shader_info_fs()
950 info->ps.uses_sample_shading = nir->info.fs.uses_sample_shading; in gather_shader_info_fs()
951 info->ps.uses_fbfetch_output = nir->info.fs.uses_fbfetch_output; in gather_shader_info_fs()
952 info->ps.writes_memory = nir->info.writes_memory; in gather_shader_info_fs()
953 info->ps.has_pcoord = nir->info.inputs_read & VARYING_BIT_PNTC; in gather_shader_info_fs()
954 info->ps.prim_id_input = nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID; in gather_shader_info_fs()
955 info->ps.reads_layer = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LAYER_ID); in gather_shader_info_fs()
956 info->ps.viewport_index_input = nir->info.inputs_read & VARYING_BIT_VIEWPORT; in gather_shader_info_fs()
957 info->ps.writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH); in gather_shader_info_fs()
958 info->ps.writes_stencil = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL); in gather_shader_info_fs()
959 … info->ps.writes_sample_mask = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK); in gather_shader_info_fs()
960 …info->ps.reads_sample_mask_in = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK… in gather_shader_info_fs()
961 info->ps.reads_sample_id = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID); in gather_shader_info_fs()
962 …info->ps.reads_frag_shading_rate = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_SHA… in gather_shader_info_fs()
963 info->ps.reads_front_face = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE) | in gather_shader_info_fs()
964 … BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE_FSIGN); in gather_shader_info_fs()
965 …info->ps.reads_barycentric_model = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENT… in gather_shader_info_fs()
966 …info->ps.reads_fully_covered = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FULLY_COVERE… in gather_shader_info_fs()
974 info->ps.writes_memory || nir->info.fs.needs_quad_helper_invocations || in gather_shader_info_fs()
975 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) || in gather_shader_info_fs()
976 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PIXEL_COORD) || in gather_shader_info_fs()
977 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_POINT_COORD) || in gather_shader_info_fs()
978 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) || in gather_shader_info_fs()
979 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) || in gather_shader_info_fs()
980 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN) || in gather_shader_info_fs()
981 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_HELPER_INVOCATION)); in gather_shader_info_fs()
984 …info->ps.pops && (nir->info.fs.sample_interlock_ordered || nir->info.fs.sample_interlock_unordered… in gather_shader_info_fs()
1023 (nir->info.fs.sample_interlock_ordered || nir->info.fs.sample_interlock_unordered || in gather_shader_info_fs()
1024 nir->info.fs.pixel_interlock_ordered || nir->info.fs.pixel_interlock_unordered)); in gather_shader_info_fs()
1028 gather_shader_info_rt(const nir_shader *nir, struct radv_shader_info *info) in gather_shader_info_rt() argument
1039 gather_shader_info_cs(struct radv_device *device, const nir_shader *nir, const struct radv_shader_s… in gather_shader_info_cs() argument
1047 …unsigned local_size = nir->info.workgroup_size[0] * nir->info.workgroup_size[1] * nir->info.workgr… in gather_shader_info_cs()
1054 stage_key->subgroup_require_full || nir->info.cs.has_cooperative_matrix || in gather_shader_info_cs()
1055 …(default_wave_size == 32 && nir->info.uses_wide_subgroup_intrinsics && local_size % RADV_SUBGROUP_… in gather_shader_info_cs()
1076 gather_shader_info_task(struct radv_device *device, const nir_shader *nir, in gather_shader_info_task() argument
1079 gather_shader_info_cs(device, nir, stage_key, info); in gather_shader_info_task()
1098 …nir->info.mesh.ts_mesh_dispatch_dimensions[1] == 1 && nir->info.mesh.ts_mesh_dispatch_dimensions[2… in gather_shader_info_task()
1200 radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, in radv_nir_shader_info_pass() argument
1206 struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions); in radv_nir_shader_info_pass()
1214 gather_info_block(nir, block, info, gfx_state, stage_key, consider_force_vrs); in radv_nir_shader_info_pass()
1217 if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL || in radv_nir_shader_info_pass()
1218 nir->info.stage == MESA_SHADER_GEOMETRY) in radv_nir_shader_info_pass()
1219 gather_xfb_info(nir, info); in radv_nir_shader_info_pass()
1221 if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL || in radv_nir_shader_info_pass()
1222 nir->info.stage == MESA_SHADER_GEOMETRY || nir->info.stage == MESA_SHADER_MESH) { in radv_nir_shader_info_pass()
1226 radv_get_output_masks(nir, gfx_state, &per_vtx_mask, &per_prim_mask); in radv_nir_shader_info_pass()
1229 if (nir->info.stage == MESA_SHADER_MESH && gfx_state->has_multiview_view_index) in radv_nir_shader_info_pass()
1259 info->vs.needs_draw_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); in radv_nir_shader_info_pass()
1260 …info->vs.needs_base_instance |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTAN… in radv_nir_shader_info_pass()
1261 … info->vs.needs_instance_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID); in radv_nir_shader_info_pass()
1262 info->uses_view_index |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VIEW_INDEX); in radv_nir_shader_info_pass()
1263 … info->uses_invocation_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INVOCATION_ID); in radv_nir_shader_info_pass()
1264 info->uses_prim_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID); in radv_nir_shader_info_pass()
1267 …info->cs.uses_grid_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_WORKGROUPS) || in radv_nir_shader_info_pass()
1268 (nir->info.stage == MESA_SHADER_MESH && pdev->info.gfx_level < GFX11); in radv_nir_shader_info_pass()
1269 …info->cs.uses_local_invocation_idx = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_… in radv_nir_shader_info_pass()
1270 … BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_ID) | in radv_nir_shader_info_pass()
1271 … BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_SUBGROUPS) | in radv_nir_shader_info_pass()
1272 radv_shader_should_clear_lds(device, nir); in radv_nir_shader_info_pass()
1274 if (nir->info.stage == MESA_SHADER_COMPUTE || nir->info.stage == MESA_SHADER_TASK || in radv_nir_shader_info_pass()
1275 nir->info.stage == MESA_SHADER_MESH) { in radv_nir_shader_info_pass()
1277 info->cs.block_size[i] = nir->info.workgroup_size[i]; in radv_nir_shader_info_pass()
1284 switch (nir->info.stage) { in radv_nir_shader_info_pass()
1286 gather_shader_info_cs(device, nir, stage_key, info); in radv_nir_shader_info_pass()
1289 gather_shader_info_task(device, nir, stage_key, info); in radv_nir_shader_info_pass()
1292 gather_shader_info_fs(device, nir, gfx_state, info); in radv_nir_shader_info_pass()
1295 gather_shader_info_gs(device, nir, info); in radv_nir_shader_info_pass()
1298 gather_shader_info_tes(device, nir, info); in radv_nir_shader_info_pass()
1301 gather_shader_info_tcs(device, nir, gfx_state, info); in radv_nir_shader_info_pass()
1304 gather_shader_info_vs(device, nir, gfx_state, stage_key, info); in radv_nir_shader_info_pass()
1307 gather_shader_info_mesh(device, nir, stage_key, info); in radv_nir_shader_info_pass()
1310 if (gl_shader_stage_is_rt(nir->info.stage)) in radv_nir_shader_info_pass()
1311 gather_shader_info_rt(nir, info); in radv_nir_shader_info_pass()
1315 info->wave_size = radv_get_wave_size(device, nir->info.stage, info, stage_key); in radv_nir_shader_info_pass()
1316 info->ballot_bit_size = radv_get_ballot_bit_size(device, nir->info.stage, info, stage_key); in radv_nir_shader_info_pass()
1318 switch (nir->info.stage) { in radv_nir_shader_info_pass()
1321 … info->workgroup_size = ac_compute_cs_workgroup_size(nir->info.workgroup_size, false, UINT32_MAX); in radv_nir_shader_info_pass()
1328 …info->cs.uses_full_subgroups = pipeline_type != RADV_PIPELINE_RAY_TRACING && !nir->info.internal && in radv_nir_shader_info_pass()
1376 calc_mesh_workgroup_size(device, nir, info); in radv_nir_shader_info_pass()
1703 ps_inputs_read = fs_stage->nir->info.inputs_read; in radv_determine_ngg_settings()
1708 ps_inputs_read = es_stage->nir->info.outputs_written; in radv_determine_ngg_settings()
1718 … num_vertices_per_prim = es_stage->nir->info.tess.point_mode ? 1 in radv_determine_ngg_settings()
1719 … : es_stage->nir->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES ? 2 in radv_determine_ngg_settings()
1724 …radv_consider_culling(pdev, es_stage->nir, ps_inputs_read, num_vertices_per_prim, &es_stage->info); in radv_determine_ngg_settings()
1726 nir_function_impl *impl = nir_shader_get_entrypoint(es_stage->nir); in radv_determine_ngg_settings()
1750 …radv_set_vs_output_param(device, producer->nir, gfx_state, &producer->info, ps_prim_id_in, ps_clip… in radv_link_shaders_info()
1773 producer->info.gs_inputs_read = consumer->nir->info.inputs_read; in radv_link_shaders_info()
1781 vs_stage->info.vs.tcs_inputs_via_lds = tcs_stage->nir->info.inputs_read; in radv_link_shaders_info()
1801 …vs_stage->nir->info.float_controls_execution_mode == tcs_stage->nir->info.float_controls_execution… in radv_link_shaders_info()
1804 vs_stage->info.vs.tcs_inputs_via_temp = vs_stage->nir->info.outputs_written & in radv_link_shaders_info()
1805 … ~vs_stage->nir->info.outputs_accessed_indirectly & in radv_link_shaders_info()
1806 … tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read; in radv_link_shaders_info()
1807 …vs_stage->info.vs.tcs_inputs_via_lds = tcs_stage->nir->info.tess.tcs_cross_invocation_inputs_read | in radv_link_shaders_info()
1808 … (tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read & in radv_link_shaders_info()
1809 … tcs_stage->nir->info.inputs_read_indirectly) | in radv_link_shaders_info()
1810 … (tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read & in radv_link_shaders_info()
1811 … vs_stage->nir->info.outputs_accessed_indirectly); in radv_link_shaders_info()
1823 tcs_stage->info.tcs.tes_inputs_read = tes_stage->nir->info.inputs_read; in radv_link_shaders_info()
1824 tcs_stage->info.tcs.tes_patch_inputs_read = tes_stage->nir->info.patch_inputs_read; in radv_link_shaders_info()
1825 tcs_stage->info.tes._primitive_mode = tes_stage->nir->info.tess._primitive_mode; in radv_link_shaders_info()
1875 …struct radv_shader_stage *next_stage = stages[MESA_SHADER_FRAGMENT].nir ? &stages[MESA_SHADER_FRAG… in radv_nir_shader_info_link()
1879 if (!stages[s].nir) in radv_nir_shader_info_link()
1888 if (stages[MESA_SHADER_VERTEX].nir && stages[MESA_SHADER_TESS_CTRL].nir) { in radv_nir_shader_info_link()
1893 …if ((stages[MESA_SHADER_VERTEX].nir || stages[MESA_SHADER_TESS_EVAL].nir) && stages[MESA_SHADER_GE… in radv_nir_shader_info_link()
1894 …gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADE… in radv_nir_shader_info_link()