1 /* 2 * Copyright (c) 2023 Institute of Parallel And Distributed Systems (IPADS), Shanghai Jiao Tong University (SJTU) 3 * Licensed under the Mulan PSL v2. 4 * You can use this software according to the terms and conditions of the Mulan PSL v2. 5 * You may obtain a copy of Mulan PSL v2 at: 6 * http://license.coscl.org.cn/MulanPSL2 7 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR 8 * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR 9 * PURPOSE. 10 * See the Mulan PSL v2 for more details. 11 */ 12 #ifndef ARCH_AARCH64_ARCH_MACHINE_REGISTER_H 13 #define ARCH_AARCH64_ARCH_MACHINE_REGISTER_H 14 15 #include <common/macro.h> 16 17 #define SPSR_EL1_DEBUG BIT(9) /* Debug mask */ 18 #define SPSR_EL1_SERROR BIT(8) /* SERROR mask */ 19 #define SPSR_EL1_IRQ BIT(7) /* IRQ mask */ 20 #define SPSR_EL1_FIQ BIT(6) /* FIQ mask */ 21 22 /* 23 * In AArch64, CTR_EL0 provides informantion about the architecture of the caches. 24 */ 25 /* Instruction cache invalidation requirements for data to instruction coherence */ 26 #define CTR_EL0_DIC BIT(29) 27 /* Data cache clean requirements for instruction to data coherence */ 28 #define CTR_EL0_IDC BIT(28) 29 /* Level 1 instruction cache indexing and tagging policy */ 30 #define CTR_EL0_L1Ip_MASK 0b11 31 #define CTR_EL0_L1Ip_SHIFT 14 32 33 /* 34 * In AArch64, SPSR_EL1 35 * [9:6] DAIF mask bits (Debug exception, SError interrupt, IRQ interrupt, FIQ interrupt. 36 * [3:0] exception level and selected Stack Pointer (the following three choices). 37 */ 38 #define SPSR_EL1_EL0t 0b0000 39 #define SPSR_EL1_EL1t 0b0100 40 #define SPSR_EL1_EL1h 0b0101 41 42 /* SPSR_EL1 DEFAULT */ 43 #define SPSR_EL1_KERNEL SPSR_EL1_EL1h 44 #define SPSR_EL1_USER SPSR_EL1_EL0t 45 46 #define SCTLR_EL1_I \ 47 BIT(12) /* Instruction access Cacheability control, for accesses at EL0 and EL1 */ 48 #define SCTLR_EL1_nAA \ 49 BIT(6) /* Non-aligned access. This bit controls generation of Alignment faults at EL1 and EL0 under certain conditions */ 50 #define SCTLR_EL1_SA0 BIT(4) /* SP Alignment check enable for EL0 */ 51 #define SCTLR_EL1_SA BIT(3) /* SP Alignment check */ 52 #define SCTLR_EL1_C BIT(2) /* Cacheability control for data accesses */ 53 #define SCTLR_EL1_A BIT(1) /* Alignment check enable */ 54 #define SCTLR_EL1_M \ 55 BIT(0) /* MMU enable for EL1 and EL0 stage 1 address translation */ 56 57 /* SCTLR_EL2 System Control Register aarch64 */ 58 59 #define SCTLR_EL2_DSSBS BIT(44) 60 #define SCTLR_EL2_EnIA BIT(31) 61 #define SCTLR_EL2_EnIB BIT(30) 62 #define SCTLR_EL2_EnDA BIT(27) 63 #define SCTLR_EL2_EE BIT(25) 64 #define SCTLR_EL2_EIS BIT(22) 65 #define SCTLR_EL2_IESB BIT(21) 66 #define SCTLR_EL2_WXN BIT(19) 67 #define SCTLR_EL2_EnDB BIT(13) 68 #define SCTLR_EL2_I BIT(12) 69 #define SCTLR_EL2_EOS BIT(11) 70 #define SCTLR_EL2_nAA BIT(6) 71 #define SCTLR_EL2_SA BIT(3) 72 #define SCTLR_EL2_C BIT(2) 73 #define SCTLR_EL2_A BIT(1) 74 #define SCTLR_EL2_M BIT(0) 75 76 #define SCTLR_EL2_FLAGS \ 77 (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C | SCTLR_EL2_SA | SCTLR_EL2_I \ 78 | SCTLR_EL2_IESB) 79 80 #define SCTLR_EL2_RES1 \ 81 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | (BIT(18)) | (BIT(22)) \ 82 | (BIT(23)) | (BIT(28)) | (BIT(29))) 83 84 #ifndef __ASM__ 85 /* Types of the registers */ 86 enum reg_type { 87 X0 = 0, /* 0x00 */ 88 X1 = 1, /* 0x08 */ 89 X2 = 2, /* 0x10 */ 90 X3 = 3, /* 0x18 */ 91 X4 = 4, /* 0x20 */ 92 X5 = 5, /* 0x28 */ 93 X6 = 6, /* 0x30 */ 94 X7 = 7, /* 0x38 */ 95 X8 = 8, /* 0x40 */ 96 X9 = 9, /* 0x48 */ 97 X10 = 10, /* 0x50 */ 98 X11 = 11, /* 0x58 */ 99 X12 = 12, /* 0x60 */ 100 X13 = 13, /* 0x68 */ 101 X14 = 14, /* 0x70 */ 102 X15 = 15, /* 0x78 */ 103 X16 = 16, /* 0x80 */ 104 X17 = 17, /* 0x88 */ 105 X18 = 18, /* 0x90 */ 106 X19 = 19, /* 0x98 */ 107 X20 = 20, /* 0xa0 */ 108 X21 = 21, /* 0xa8 */ 109 X22 = 22, /* 0xb0 */ 110 X23 = 23, /* 0xb8 */ 111 X24 = 24, /* 0xc0 */ 112 X25 = 25, /* 0xc8 */ 113 X26 = 26, /* 0xd0 */ 114 X27 = 27, /* 0xd8 */ 115 X28 = 28, /* 0xe0 */ 116 X29 = 29, /* 0xe8 */ 117 X30 = 30, /* 0xf0 */ 118 SP_EL0 = 31, /* 0xf8 */ 119 ELR_EL1 = 32, /* 0x100 NEXT PC */ 120 SPSR_EL1 = 33, /* 0x108 */ 121 }; 122 #endif /* ASMCODE */ 123 124 #define REG_NUM (34) 125 126 /* In bytes */ 127 #define SZ_U64 8 128 #define ARCH_EXEC_CONT_SIZE (REG_NUM * SZ_U64) 129 130 #endif /* ARCH_AARCH64_ARCH_MACHINE_REGISTER_H */