1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions. 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: sbpcmcia.h 647676 2016-07-07 02:59:05Z $ 29 */ 30 31 #ifndef _SBPCMCIA_H 32 #define _SBPCMCIA_H 33 34 /* All the addresses that are offsets in attribute space are divided 35 * by two to account for the fact that odd bytes are invalid in 36 * attribute space and our read/write routines make the space appear 37 * as if they didn't exist. Still we want to show the original numbers 38 * as documented in the hnd_pcmcia core manual. 39 */ 40 41 /* PCMCIA Function Configuration Registers */ 42 #define PCMCIA_FCR (0x700 / 2) 43 44 #define FCR0_OFF 0 45 #define FCR1_OFF (0x40 / 2) 46 #define FCR2_OFF (0x80 / 2) 47 #define FCR3_OFF (0xc0 / 2) 48 49 #define PCMCIA_FCR0 (0x700 / 2) 50 #define PCMCIA_FCR1 (0x740 / 2) 51 #define PCMCIA_FCR2 (0x780 / 2) 52 #define PCMCIA_FCR3 (0x7c0 / 2) 53 54 /* Standard PCMCIA FCR registers */ 55 56 #define PCMCIA_COR 0 57 58 #define COR_RST 0x80 59 #define COR_LEV 0x40 60 #define COR_IRQEN 0x04 61 #define COR_BLREN 0x01 62 #define COR_FUNEN 0x01 63 64 #define PCICIA_FCSR (2 / 2) 65 #define PCICIA_PRR (4 / 2) 66 #define PCICIA_SCR (6 / 2) 67 #define PCICIA_ESR (8 / 2) 68 69 #define PCM_MEMOFF 0x0000 70 #define F0_MEMOFF 0x1000 71 #define F1_MEMOFF 0x2000 72 #define F2_MEMOFF 0x3000 73 #define F3_MEMOFF 0x4000 74 75 /* Memory base in the function fcr's */ 76 #define MEM_ADDR0 (0x728 / 2) 77 #define MEM_ADDR1 (0x72a / 2) 78 #define MEM_ADDR2 (0x72c / 2) 79 80 /* PCMCIA base plus Srom access in fcr0: */ 81 #define PCMCIA_ADDR0 (0x072e / 2) 82 #define PCMCIA_ADDR1 (0x0730 / 2) 83 #define PCMCIA_ADDR2 (0x0732 / 2) 84 85 #define MEM_SEG (0x0734 / 2) 86 #define SROM_CS (0x0736 / 2) 87 #define SROM_DATAL (0x0738 / 2) 88 #define SROM_DATAH (0x073a / 2) 89 #define SROM_ADDRL (0x073c / 2) 90 #define SROM_ADDRH (0x073e / 2) 91 #define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */ 92 #define SROM_INFO (0x07be / 2) /* Corerev >= 6 */ 93 94 /* Values for srom_cs: */ 95 #define SROM_IDLE 0 96 #define SROM_WRITE 1 97 #define SROM_READ 2 98 #define SROM_WEN 4 99 #define SROM_WDS 7 100 #define SROM_DONE 8 101 102 /* Fields in srom_info: */ 103 #define SRI_SZ_MASK 0x03 104 #define SRI_BLANK 0x04 105 #define SRI_OTP 0x80 106 107 #define SROM16K_BANK_SEL_MASK (3 << 11) 108 #define SROM16K_BANK_SHFT_MASK 11 109 #define SROM16K_ADDR_SEL_MASK ((1 << SROM16K_BANK_SHFT_MASK) - 1) 110 #define SROM_PRSNT_MASK 0x1 111 #define SROM_SUPPORT_SHIFT_MASK 30 112 #define SROM_SUPPORTED (0x1 << SROM_SUPPORT_SHIFT_MASK) 113 #define SROM_SIZE_MASK 0x00000006 114 #define SROM_SIZE_2K 2 115 #define SROM_SIZE_512 1 116 #define SROM_SIZE_128 0 117 #define SROM_SIZE_SHFT_MASK 1 118 119 /* Standard tuples we know about */ 120 121 #define CISTPL_NULL 0x00 122 #define CISTPL_END 0xff /* End of the CIS tuple chain */ 123 124 #define CISTPL_BRCM_HNBU 0x80 125 126 #define HNBU_BOARDREV 0x02 /* One byte board revision */ 127 128 #define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */ 129 130 #define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */ 131 132 /* sbtmstatelow */ 133 #define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */ 134 #define SBTML_INT_EN 0x20000 /* enable sb interrupt */ 135 136 /* sbtmstatehigh */ 137 #define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */ 138 #endif /* _SBPCMCIA_H */ 139