1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2018-2021 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 /* 23 * This header was originally autogenerated, but it is now ok (and 24 * expected) to have to add to it. 25 */ 26 27 #ifndef _UAPI_GPU_CSF_REGISTERS_H_ 28 #define _UAPI_GPU_CSF_REGISTERS_H_ 29 30 /* 31 * Begin register sets 32 */ 33 34 /* DOORBELLS base address */ 35 #define DOORBELLS_BASE 0x0080000 36 #define DOORBELLS_REG(r) (DOORBELLS_BASE + (r)) 37 38 /* CS_KERNEL_INPUT_BLOCK base address */ 39 #define CS_KERNEL_INPUT_BLOCK_BASE 0x0000 40 #define CS_KERNEL_INPUT_BLOCK_REG(r) (CS_KERNEL_INPUT_BLOCK_BASE + (r)) 41 42 /* CS_KERNEL_OUTPUT_BLOCK base address */ 43 #define CS_KERNEL_OUTPUT_BLOCK_BASE 0x0000 44 #define CS_KERNEL_OUTPUT_BLOCK_REG(r) (CS_KERNEL_OUTPUT_BLOCK_BASE + (r)) 45 46 /* CS_USER_INPUT_BLOCK base address */ 47 #define CS_USER_INPUT_BLOCK_BASE 0x0000 48 #define CS_USER_INPUT_BLOCK_REG(r) (CS_USER_INPUT_BLOCK_BASE + (r)) 49 50 /* CS_USER_OUTPUT_BLOCK base address */ 51 #define CS_USER_OUTPUT_BLOCK_BASE 0x0000 52 #define CS_USER_OUTPUT_BLOCK_REG(r) (CS_USER_OUTPUT_BLOCK_BASE + (r)) 53 54 /* CSG_INPUT_BLOCK base address */ 55 #define CSG_INPUT_BLOCK_BASE 0x0000 56 #define CSG_INPUT_BLOCK_REG(r) (CSG_INPUT_BLOCK_BASE + (r)) 57 58 /* CSG_OUTPUT_BLOCK base address */ 59 #define CSG_OUTPUT_BLOCK_BASE 0x0000 60 #define CSG_OUTPUT_BLOCK_REG(r) (CSG_OUTPUT_BLOCK_BASE + (r)) 61 62 /* GLB_CONTROL_BLOCK base address */ 63 #define GLB_CONTROL_BLOCK_BASE 0x04000000 64 #define GLB_CONTROL_BLOCK_REG(r) (GLB_CONTROL_BLOCK_BASE + (r)) 65 66 /* GLB_INPUT_BLOCK base address */ 67 #define GLB_INPUT_BLOCK_BASE 0x0000 68 #define GLB_INPUT_BLOCK_REG(r) (GLB_INPUT_BLOCK_BASE + (r)) 69 70 /* GLB_OUTPUT_BLOCK base address */ 71 #define GLB_OUTPUT_BLOCK_BASE 0x0000 72 #define GLB_OUTPUT_BLOCK_REG(r) (GLB_OUTPUT_BLOCK_BASE + (r)) 73 74 /* USER base address */ 75 #define USER_BASE 0x0010000 76 #define USER_REG(r) (USER_BASE + (r)) 77 78 /* End register sets */ 79 80 /* 81 * Begin register offsets 82 */ 83 84 /* DOORBELLS register offsets */ 85 #define DOORBELL_0 0x0000 /* () Doorbell 0 register */ 86 #define DOORBELL(n) (DOORBELL_0 + (n)*65536) 87 #define DOORBELL_REG(n, r) (DOORBELL(n) + DOORBELL_BLOCK_REG(r)) 88 #define DOORBELL_COUNT 1024 89 90 /* DOORBELL_BLOCK register offsets */ 91 #define DB_BLK_DOORBELL 0x0000 /* (WO) Doorbell request */ 92 93 /* CS_KERNEL_INPUT_BLOCK register offsets */ 94 #define CS_REQ 0x0000 /* () CS request flags */ 95 #define CS_CONFIG 0x0004 /* () CS configuration */ 96 #define CS_ACK_IRQ_MASK 0x000C /* () Command steam interrupt mask */ 97 #define CS_BASE_LO 0x0010 /* () Base pointer for the ring buffer, low word */ 98 #define CS_BASE_HI 0x0014 /* () Base pointer for the ring buffer, high word */ 99 #define CS_SIZE 0x0018 /* () Size of the ring buffer */ 100 #define CS_TILER_HEAP_START_LO 0x0020 /* () Pointer to heap start, low word */ 101 #define CS_TILER_HEAP_START_HI 0x0024 /* () Pointer to heap start, high word */ 102 #define CS_TILER_HEAP_END_LO 0x0028 /* () Tiler heap descriptor address, low word */ 103 #define CS_TILER_HEAP_END_HI 0x002C /* () Tiler heap descriptor address, high word */ 104 #define CS_USER_INPUT_LO 0x0030 /* () CS user mode input page address, low word */ 105 #define CS_USER_INPUT_HI 0x0034 /* () CS user mode input page address, high word */ 106 #define CS_USER_OUTPUT_LO 0x0038 /* () CS user mode input page address, low word */ 107 #define CS_USER_OUTPUT_HI 0x003C /* () CS user mode input page address, high word */ 108 #define CS_INSTR_CONFIG 0x0040 /* () Instrumentation buffer configuration */ 109 #define CS_INSTR_BUFFER_SIZE 0x0044 /* () Instrumentation buffer size */ 110 #define CS_INSTR_BUFFER_BASE_LO 0x0048 /* () Instrumentation buffer base pointer, low word */ 111 #define CS_INSTR_BUFFER_BASE_HI 0x004C /* () Instrumentation buffer base pointer, high word */ 112 #define CS_INSTR_BUFFER_OFFSET_POINTER_LO 0x0050 /* () Instrumentation buffer pointer to insert offset, low word */ 113 #define CS_INSTR_BUFFER_OFFSET_POINTER_HI 0x0054 /* () Instrumentation buffer pointer to insert offset, high word */ 114 115 /* CS_KERNEL_OUTPUT_BLOCK register offsets */ 116 #define CS_ACK 0x0000 /* () CS acknowledge flags */ 117 #define CS_STATUS_CMD_PTR_LO 0x0040 /* () Program pointer current value, low word */ 118 #define CS_STATUS_CMD_PTR_HI 0x0044 /* () Program pointer current value, high word */ 119 #define CS_STATUS_WAIT 0x0048 /* () Wait condition status register */ 120 #define CS_STATUS_REQ_RESOURCE 0x004C /* () Indicates the resources requested by the CS */ 121 #define CS_STATUS_WAIT_SYNC_POINTER_LO 0x0050 /* () Sync object pointer, low word */ 122 #define CS_STATUS_WAIT_SYNC_POINTER_HI 0x0054 /* () Sync object pointer, high word */ 123 #define CS_STATUS_WAIT_SYNC_VALUE 0x0058 /* () Sync object test value */ 124 #define CS_STATUS_SCOREBOARDS 0x005C /* () Scoreboard status */ 125 #define CS_STATUS_BLOCKED_REASON 0x0060 /* () Blocked reason */ 126 #define CS_FAULT 0x0080 /* () Recoverable fault information */ 127 #define CS_FATAL 0x0084 /* () Unrecoverable fault information */ 128 #define CS_FAULT_INFO_LO 0x0088 /* () Additional information about a recoverable fault, low word */ 129 #define CS_FAULT_INFO_HI 0x008C /* () Additional information about a recoverable fault, high word */ 130 #define CS_FATAL_INFO_LO 0x0090 /* () Additional information about a non-recoverable fault, low word */ 131 #define CS_FATAL_INFO_HI 0x0094 /* () Additional information about a non-recoverable fault, high word */ 132 #define CS_HEAP_VT_START 0x00C0 /* () Number of vertex/tiling operations started */ 133 #define CS_HEAP_VT_END 0x00C4 /* () Number of vertex/tiling operations completed */ 134 #define CS_HEAP_FRAG_END 0x00CC /* () Number of fragment completed */ 135 #define CS_HEAP_ADDRESS_LO 0x00D0 /* () Heap address, low word */ 136 #define CS_HEAP_ADDRESS_HI 0x00D4 /* () Heap address, high word */ 137 138 /* CS_USER_INPUT_BLOCK register offsets */ 139 #define CS_INSERT_LO 0x0000 /* () Current insert offset for ring buffer, low word */ 140 #define CS_INSERT_HI 0x0004 /* () Current insert offset for ring buffer, high word */ 141 #define CS_EXTRACT_INIT_LO 0x0008 /* () Initial extract offset for ring buffer, low word */ 142 #define CS_EXTRACT_INIT_HI 0x000C /* () Initial extract offset for ring buffer, high word */ 143 144 /* CS_USER_OUTPUT_BLOCK register offsets */ 145 #define CS_EXTRACT_LO 0x0000 /* () Current extract offset for ring buffer, low word */ 146 #define CS_EXTRACT_HI 0x0004 /* () Current extract offset for ring buffer, high word */ 147 #define CS_ACTIVE 0x0008 /* () Initial extract offset when the CS is started */ 148 149 /* CSG_INPUT_BLOCK register offsets */ 150 #define CSG_REQ 0x0000 /* () CSG request */ 151 #define CSG_ACK_IRQ_MASK 0x0004 /* () Global acknowledge interrupt mask */ 152 #define CSG_DB_REQ 0x0008 /* () Global doorbell request */ 153 #define CSG_IRQ_ACK 0x000C /* () CS IRQ acknowledge */ 154 #define CSG_ALLOW_COMPUTE_LO 0x0020 /* () Allowed compute endpoints, low word */ 155 #define CSG_ALLOW_COMPUTE_HI 0x0024 /* () Allowed compute endpoints, high word */ 156 #define CSG_ALLOW_FRAGMENT_LO 0x0028 /* () Allowed fragment endpoints, low word */ 157 #define CSG_ALLOW_FRAGMENT_HI 0x002C /* () Allowed fragment endpoints, high word */ 158 #define CSG_ALLOW_OTHER 0x0030 /* () Allowed other endpoints */ 159 #define CSG_EP_REQ 0x0034 /* () Maximum number of endpoints allowed */ 160 #define CSG_SUSPEND_BUF_LO 0x0040 /* () Normal mode suspend buffer, low word */ 161 #define CSG_SUSPEND_BUF_HI 0x0044 /* () Normal mode suspend buffer, high word */ 162 #define CSG_PROTM_SUSPEND_BUF_LO 0x0048 /* () Protected mode suspend buffer, low word */ 163 #define CSG_PROTM_SUSPEND_BUF_HI 0x004C /* () Protected mode suspend buffer, high word */ 164 #define CSG_CONFIG 0x0050 /* () CSG configuration options */ 165 #define CSG_ITER_TRACE_CONFIG 0x0054 /* () CSG trace configuration */ 166 167 /* CSG_OUTPUT_BLOCK register offsets */ 168 #define CSG_ACK 0x0000 /* () CSG acknowledge flags */ 169 #define CSG_DB_ACK 0x0008 /* () CS kernel doorbell acknowledge flags */ 170 #define CSG_IRQ_REQ 0x000C /* () CS interrupt request flags */ 171 #define CSG_STATUS_EP_CURRENT 0x0010 /* () Endpoint allocation status register */ 172 #define CSG_STATUS_EP_REQ 0x0014 /* () Endpoint request status register */ 173 #define CSG_RESOURCE_DEP 0x001C /* () Current resource dependencies */ 174 175 /* GLB_CONTROL_BLOCK register offsets */ 176 #define GLB_VERSION 0x0000 /* () Global interface version */ 177 #define GLB_FEATURES 0x0004 /* () Global interface features */ 178 #define GLB_INPUT_VA 0x0008 /* () Address of GLB_INPUT_BLOCK */ 179 #define GLB_OUTPUT_VA 0x000C /* () Address of GLB_OUTPUT_BLOCK */ 180 #define GLB_GROUP_NUM 0x0010 /* () Number of CSG interfaces */ 181 #define GLB_GROUP_STRIDE 0x0014 /* () Stride between CSG interfaces */ 182 #define GLB_PRFCNT_SIZE 0x0018 /* () Size of CSF performance counters */ 183 #define GLB_INSTR_FEATURES \ 184 0x001C /* () TRACE_POINT instrumentation. (csf >= 1.1.0) */ 185 #define GROUP_CONTROL_0 0x1000 /* () CSG control and capabilities */ 186 #define GROUP_CONTROL(n) (GROUP_CONTROL_0 + (n)*256) 187 #define GROUP_CONTROL_REG(n, r) (GROUP_CONTROL(n) + GROUP_CONTROL_BLOCK_REG(r)) 188 #define GROUP_CONTROL_COUNT 16 189 190 /* STREAM_CONTROL_BLOCK register offsets */ 191 #define STREAM_FEATURES 0x0000 /* () CSI features */ 192 #define STREAM_INPUT_VA 0x0004 /* () Address of CS_KERNEL_INPUT_BLOCK */ 193 #define STREAM_OUTPUT_VA 0x0008 /* () Address of CS_KERNEL_OUTPUT_BLOCK */ 194 195 /* GROUP_CONTROL_BLOCK register offsets */ 196 #define GROUP_FEATURES 0x0000 /* () CSG interface features */ 197 #define GROUP_INPUT_VA 0x0004 /* () Address of CSG_INPUT_BLOCK */ 198 #define GROUP_OUTPUT_VA 0x0008 /* () Address of CSG_OUTPUT_BLOCK */ 199 #define GROUP_SUSPEND_SIZE 0x000C /* () Size of CSG suspend buffer */ 200 #define GROUP_PROTM_SUSPEND_SIZE 0x0010 /* () Size of CSG protected-mode suspend buffer */ 201 #define GROUP_STREAM_NUM 0x0014 /* () Number of CS interfaces */ 202 #define GROUP_STREAM_STRIDE 0x0018 /* () Stride between CS interfaces */ 203 #define STREAM_CONTROL_0 0x0040 /* () CS control and capabilities */ 204 #define STREAM_CONTROL(n) (STREAM_CONTROL_0 + (n)*12) 205 #define STREAM_CONTROL_REG(n, r) (STREAM_CONTROL(n) + STREAM_CONTROL_BLOCK_REG(r)) 206 #define STREAM_CONTROL_COUNT 16 207 208 /* GLB_INPUT_BLOCK register offsets */ 209 #define GLB_REQ 0x0000 /* () Global request */ 210 #define GLB_ACK_IRQ_MASK 0x0004 /* () Global acknowledge interrupt mask */ 211 #define GLB_DB_REQ 0x0008 /* () Global doorbell request */ 212 #define GLB_PROGRESS_TIMER 0x0010 /* () Global progress timeout */ 213 #define GLB_PWROFF_TIMER 0x0014 /* () Global shader core power off timer */ 214 #define GLB_ALLOC_EN_LO 0x0018 /* () Global shader core allocation enable mask, low word */ 215 #define GLB_ALLOC_EN_HI 0x001C /* () Global shader core allocation enable mask, high word */ 216 217 #define GLB_PRFCNT_JASID 0x0024 /* () Performance counter address space */ 218 #define GLB_PRFCNT_BASE_LO 0x0028 /* () Performance counter buffer address, low word */ 219 #define GLB_PRFCNT_BASE_HI 0x002C /* () Performance counter buffer address, high word */ 220 #define GLB_PRFCNT_EXTRACT 0x0030 /* () Performance counter buffer extract index */ 221 #define GLB_PRFCNT_CONFIG 0x0040 /* () Performance counter configuration */ 222 #define GLB_PRFCNT_CSG_SELECT 0x0044 /* () CSG performance counting enable */ 223 #define GLB_PRFCNT_FW_EN 0x0048 /* () Performance counter enable for firmware */ 224 #define GLB_PRFCNT_CSG_EN 0x004C /* () Performance counter enable for CSG */ 225 #define GLB_PRFCNT_CSF_EN 0x0050 /* () Performance counter enable for CSF */ 226 #define GLB_PRFCNT_SHADER_EN 0x0054 /* () Performance counter enable for shader cores */ 227 #define GLB_PRFCNT_TILER_EN 0x0058 /* () Performance counter enable for tiler */ 228 #define GLB_PRFCNT_MMU_L2_EN 0x005C /* () Performance counter enable for MMU/L2 cache */ 229 230 #define GLB_DEBUG_FWUTF_DESTROY 0x0FE0 /* () Test fixture destroy function address */ 231 #define GLB_DEBUG_FWUTF_TEST 0x0FE4 /* () Test index */ 232 #define GLB_DEBUG_FWUTF_FIXTURE 0x0FE8 /* () Test fixture index */ 233 #define GLB_DEBUG_FWUTF_CREATE 0x0FEC /* () Test fixture create function address */ 234 #define GLB_DEBUG_ACK_IRQ_MASK 0x0FF8 /* () Global debug acknowledge interrupt mask */ 235 #define GLB_DEBUG_REQ 0x0FFC /* () Global debug request */ 236 237 /* GLB_OUTPUT_BLOCK register offsets */ 238 #define GLB_ACK 0x0000 /* () Global acknowledge */ 239 #define GLB_DB_ACK 0x0008 /* () Global doorbell acknowledge */ 240 #define GLB_HALT_STATUS 0x0010 /* () Global halt status */ 241 #define GLB_PRFCNT_STATUS 0x0014 /* () Performance counter status */ 242 #define GLB_PRFCNT_INSERT 0x0018 /* () Performance counter buffer insert index */ 243 #define GLB_DEBUG_FWUTF_RESULT 0x0FE0 /* () Firmware debug test result */ 244 #define GLB_DEBUG_ACK 0x0FFC /* () Global debug acknowledge */ 245 246 /* USER register offsets */ 247 #define LATEST_FLUSH 0x0000 /* () Flush ID of latest clean-and-invalidate operation */ 248 249 /* End register offsets */ 250 251 /* CS_KERNEL_INPUT_BLOCK register set definitions */ 252 /* GLB_VERSION register */ 253 #define GLB_VERSION_PATCH_SHIFT (0) 254 #define GLB_VERSION_PATCH_MASK ((0xFFFF) << GLB_VERSION_PATCH_SHIFT) 255 #define GLB_VERSION_PATCH_GET(reg_val) (((reg_val)&GLB_VERSION_PATCH_MASK) >> GLB_VERSION_PATCH_SHIFT) 256 #define GLB_VERSION_PATCH_SET(reg_val, value) \ 257 (((reg_val) & ~GLB_VERSION_PATCH_MASK) | (((value) << GLB_VERSION_PATCH_SHIFT) & GLB_VERSION_PATCH_MASK)) 258 #define GLB_VERSION_MINOR_SHIFT (16) 259 #define GLB_VERSION_MINOR_MASK ((0xFF) << GLB_VERSION_MINOR_SHIFT) 260 #define GLB_VERSION_MINOR_GET(reg_val) (((reg_val)&GLB_VERSION_MINOR_MASK) >> GLB_VERSION_MINOR_SHIFT) 261 #define GLB_VERSION_MINOR_SET(reg_val, value) \ 262 (((reg_val) & ~GLB_VERSION_MINOR_MASK) | (((value) << GLB_VERSION_MINOR_SHIFT) & GLB_VERSION_MINOR_MASK)) 263 #define GLB_VERSION_MAJOR_SHIFT (24) 264 #define GLB_VERSION_MAJOR_MASK ((0xFF) << GLB_VERSION_MAJOR_SHIFT) 265 #define GLB_VERSION_MAJOR_GET(reg_val) (((reg_val)&GLB_VERSION_MAJOR_MASK) >> GLB_VERSION_MAJOR_SHIFT) 266 #define GLB_VERSION_MAJOR_SET(reg_val, value) \ 267 (((reg_val) & ~GLB_VERSION_MAJOR_MASK) | (((value) << GLB_VERSION_MAJOR_SHIFT) & GLB_VERSION_MAJOR_MASK)) 268 269 /* CS_REQ register */ 270 #define CS_REQ_STATE_SHIFT 0 271 #define CS_REQ_STATE_MASK (0x7 << CS_REQ_STATE_SHIFT) 272 #define CS_REQ_STATE_GET(reg_val) (((reg_val)&CS_REQ_STATE_MASK) >> CS_REQ_STATE_SHIFT) 273 #define CS_REQ_STATE_SET(reg_val, value) \ 274 (((reg_val) & ~CS_REQ_STATE_MASK) | (((value) << CS_REQ_STATE_SHIFT) & CS_REQ_STATE_MASK)) 275 /* CS_REQ_STATE values */ 276 #define CS_REQ_STATE_STOP 0x0 277 #define CS_REQ_STATE_START 0x1 278 /* End of CS_REQ_STATE values */ 279 #define CS_REQ_EXTRACT_EVENT_SHIFT 4 280 #define CS_REQ_EXTRACT_EVENT_MASK (0x1 << CS_REQ_EXTRACT_EVENT_SHIFT) 281 #define CS_REQ_EXTRACT_EVENT_GET(reg_val) (((reg_val)&CS_REQ_EXTRACT_EVENT_MASK) >> CS_REQ_EXTRACT_EVENT_SHIFT) 282 #define CS_REQ_EXTRACT_EVENT_SET(reg_val, value) \ 283 (((reg_val) & ~CS_REQ_EXTRACT_EVENT_MASK) | (((value) << CS_REQ_EXTRACT_EVENT_SHIFT) & CS_REQ_EXTRACT_EVENT_MASK)) 284 285 #define CS_REQ_IDLE_SYNC_WAIT_SHIFT 8 286 #define CS_REQ_IDLE_SYNC_WAIT_MASK (0x1 << CS_REQ_IDLE_SYNC_WAIT_SHIFT) 287 #define CS_REQ_IDLE_SYNC_WAIT_GET(reg_val) (((reg_val)&CS_REQ_IDLE_SYNC_WAIT_MASK) >> CS_REQ_IDLE_SYNC_WAIT_SHIFT) 288 #define CS_REQ_IDLE_SYNC_WAIT_SET(reg_val, value) \ 289 (((reg_val) & ~CS_REQ_IDLE_SYNC_WAIT_MASK) | \ 290 (((value) << CS_REQ_IDLE_SYNC_WAIT_SHIFT) & CS_REQ_IDLE_SYNC_WAIT_MASK)) 291 #define CS_REQ_IDLE_PROTM_PEND_SHIFT 9 292 #define CS_REQ_IDLE_PROTM_PEND_MASK (0x1 << CS_REQ_IDLE_PROTM_PEND_SHIFT) 293 #define CS_REQ_IDLE_PROTM_PEND_GET(reg_val) (((reg_val)&CS_REQ_IDLE_PROTM_PEND_MASK) >> CS_REQ_IDLE_PROTM_PEND_SHIFT) 294 #define CS_REQ_IDLE_PROTM_PEND_SET(reg_val, value) \ 295 (((reg_val) & ~CS_REQ_IDLE_PROTM_PEND_MASK) | \ 296 (((value) << CS_REQ_IDLE_PROTM_PEND_SHIFT) & CS_REQ_IDLE_PROTM_PEND_MASK)) 297 #define CS_REQ_IDLE_EMPTY_SHIFT 10 298 #define CS_REQ_IDLE_EMPTY_MASK (0x1 << CS_REQ_IDLE_EMPTY_SHIFT) 299 #define CS_REQ_IDLE_EMPTY_GET(reg_val) (((reg_val)&CS_REQ_IDLE_EMPTY_MASK) >> CS_REQ_IDLE_EMPTY_SHIFT) 300 #define CS_REQ_IDLE_EMPTY_SET(reg_val, value) \ 301 (((reg_val) & ~CS_REQ_IDLE_EMPTY_MASK) | (((value) << CS_REQ_IDLE_EMPTY_SHIFT) & CS_REQ_IDLE_EMPTY_MASK)) 302 #define CS_REQ_IDLE_RESOURCE_REQ_SHIFT 11 303 #define CS_REQ_IDLE_RESOURCE_REQ_MASK (0x1 << CS_REQ_IDLE_RESOURCE_REQ_SHIFT) 304 #define CS_REQ_IDLE_RESOURCE_REQ_GET(reg_val) \ 305 (((reg_val)&CS_REQ_IDLE_RESOURCE_REQ_MASK) >> CS_REQ_IDLE_RESOURCE_REQ_SHIFT) 306 #define CS_REQ_IDLE_RESOURCE_REQ_SET(reg_val, value) \ 307 (((reg_val) & ~CS_REQ_IDLE_RESOURCE_REQ_MASK) | \ 308 (((value) << CS_REQ_IDLE_RESOURCE_REQ_SHIFT) & CS_REQ_IDLE_RESOURCE_REQ_MASK)) 309 #define CS_REQ_TILER_OOM_SHIFT 26 310 #define CS_REQ_TILER_OOM_MASK (0x1 << CS_REQ_TILER_OOM_SHIFT) 311 #define CS_REQ_TILER_OOM_GET(reg_val) (((reg_val)&CS_REQ_TILER_OOM_MASK) >> CS_REQ_TILER_OOM_SHIFT) 312 #define CS_REQ_TILER_OOM_SET(reg_val, value) \ 313 (((reg_val) & ~CS_REQ_TILER_OOM_MASK) | (((value) << CS_REQ_TILER_OOM_SHIFT) & CS_REQ_TILER_OOM_MASK)) 314 #define CS_REQ_PROTM_PEND_SHIFT 27 315 #define CS_REQ_PROTM_PEND_MASK (0x1 << CS_REQ_PROTM_PEND_SHIFT) 316 #define CS_REQ_PROTM_PEND_GET(reg_val) (((reg_val)&CS_REQ_PROTM_PEND_MASK) >> CS_REQ_PROTM_PEND_SHIFT) 317 #define CS_REQ_PROTM_PEND_SET(reg_val, value) \ 318 (((reg_val) & ~CS_REQ_PROTM_PEND_MASK) | (((value) << CS_REQ_PROTM_PEND_SHIFT) & CS_REQ_PROTM_PEND_MASK)) 319 #define CS_REQ_FATAL_SHIFT 30 320 #define CS_REQ_FATAL_MASK (0x1 << CS_REQ_FATAL_SHIFT) 321 #define CS_REQ_FATAL_GET(reg_val) (((reg_val)&CS_REQ_FATAL_MASK) >> CS_REQ_FATAL_SHIFT) 322 #define CS_REQ_FATAL_SET(reg_val, value) \ 323 (((reg_val) & ~CS_REQ_FATAL_MASK) | (((value) << CS_REQ_FATAL_SHIFT) & CS_REQ_FATAL_MASK)) 324 #define CS_REQ_FAULT_SHIFT 31 325 #define CS_REQ_FAULT_MASK (0x1 << CS_REQ_FAULT_SHIFT) 326 #define CS_REQ_FAULT_GET(reg_val) (((reg_val)&CS_REQ_FAULT_MASK) >> CS_REQ_FAULT_SHIFT) 327 #define CS_REQ_FAULT_SET(reg_val, value) \ 328 (((reg_val) & ~CS_REQ_FAULT_MASK) | (((value) << CS_REQ_FAULT_SHIFT) & CS_REQ_FAULT_MASK)) 329 330 /* CS_CONFIG register */ 331 #define CS_CONFIG_PRIORITY_SHIFT 0 332 #define CS_CONFIG_PRIORITY_MASK (0xF << CS_CONFIG_PRIORITY_SHIFT) 333 #define CS_CONFIG_PRIORITY_GET(reg_val) (((reg_val)&CS_CONFIG_PRIORITY_MASK) >> CS_CONFIG_PRIORITY_SHIFT) 334 #define CS_CONFIG_PRIORITY_SET(reg_val, value) \ 335 (((reg_val) & ~CS_CONFIG_PRIORITY_MASK) | (((value) << CS_CONFIG_PRIORITY_SHIFT) & CS_CONFIG_PRIORITY_MASK)) 336 #define CS_CONFIG_USER_DOORBELL_SHIFT 8 337 #define CS_CONFIG_USER_DOORBELL_MASK (0xFF << CS_CONFIG_USER_DOORBELL_SHIFT) 338 #define CS_CONFIG_USER_DOORBELL_GET(reg_val) (((reg_val)&CS_CONFIG_USER_DOORBELL_MASK) >> CS_CONFIG_USER_DOORBELL_SHIFT) 339 #define CS_CONFIG_USER_DOORBELL_SET(reg_val, value) \ 340 (((reg_val) & ~CS_CONFIG_USER_DOORBELL_MASK) | \ 341 (((value) << CS_CONFIG_USER_DOORBELL_SHIFT) & CS_CONFIG_USER_DOORBELL_MASK)) 342 343 /* CS_ACK_IRQ_MASK register */ 344 #define CS_ACK_IRQ_MASK_STATE_SHIFT 0 345 #define CS_ACK_IRQ_MASK_STATE_MASK (0x7 << CS_ACK_IRQ_MASK_STATE_SHIFT) 346 #define CS_ACK_IRQ_MASK_STATE_GET(reg_val) (((reg_val)&CS_ACK_IRQ_MASK_STATE_MASK) >> CS_ACK_IRQ_MASK_STATE_SHIFT) 347 #define CS_ACK_IRQ_MASK_STATE_SET(reg_val, value) \ 348 (((reg_val) & ~CS_ACK_IRQ_MASK_STATE_MASK) | \ 349 (((value) << CS_ACK_IRQ_MASK_STATE_SHIFT) & CS_ACK_IRQ_MASK_STATE_MASK)) 350 /* CS_ACK_IRQ_MASK_STATE values */ 351 #define CS_ACK_IRQ_MASK_STATE_DISABLED 0x0 352 #define CS_ACK_IRQ_MASK_STATE_ENABLED 0x7 353 /* End of CS_ACK_IRQ_MASK_STATE values */ 354 #define CS_ACK_IRQ_MASK_EXTRACT_EVENT_SHIFT 4 355 #define CS_ACK_IRQ_MASK_EXTRACT_EVENT_MASK (0x1 << CS_ACK_IRQ_MASK_EXTRACT_EVENT_SHIFT) 356 #define CS_ACK_IRQ_MASK_EXTRACT_EVENT_GET(reg_val) \ 357 (((reg_val)&CS_ACK_IRQ_MASK_EXTRACT_EVENT_MASK) >> CS_ACK_IRQ_MASK_EXTRACT_EVENT_SHIFT) 358 #define CS_ACK_IRQ_MASK_EXTRACT_EVENT_SET(reg_val, value) \ 359 (((reg_val) & ~CS_ACK_IRQ_MASK_EXTRACT_EVENT_MASK) | \ 360 (((value) << CS_ACK_IRQ_MASK_EXTRACT_EVENT_SHIFT) & CS_ACK_IRQ_MASK_EXTRACT_EVENT_MASK)) 361 #define CS_ACK_IRQ_MASK_TILER_OOM_SHIFT 26 362 #define CS_ACK_IRQ_MASK_TILER_OOM_MASK (0x1 << CS_ACK_IRQ_MASK_TILER_OOM_SHIFT) 363 #define CS_ACK_IRQ_MASK_TILER_OOM_GET(reg_val) \ 364 (((reg_val)&CS_ACK_IRQ_MASK_TILER_OOM_MASK) >> CS_ACK_IRQ_MASK_TILER_OOM_SHIFT) 365 #define CS_ACK_IRQ_MASK_TILER_OOM_SET(reg_val, value) \ 366 (((reg_val) & ~CS_ACK_IRQ_MASK_TILER_OOM_MASK) | \ 367 (((value) << CS_ACK_IRQ_MASK_TILER_OOM_SHIFT) & CS_ACK_IRQ_MASK_TILER_OOM_MASK)) 368 #define CS_ACK_IRQ_MASK_PROTM_PEND_SHIFT 27 369 #define CS_ACK_IRQ_MASK_PROTM_PEND_MASK (0x1 << CS_ACK_IRQ_MASK_PROTM_PEND_SHIFT) 370 #define CS_ACK_IRQ_MASK_PROTM_PEND_GET(reg_val) \ 371 (((reg_val)&CS_ACK_IRQ_MASK_PROTM_PEND_MASK) >> CS_ACK_IRQ_MASK_PROTM_PEND_SHIFT) 372 #define CS_ACK_IRQ_MASK_PROTM_PEND_SET(reg_val, value) \ 373 (((reg_val) & ~CS_ACK_IRQ_MASK_PROTM_PEND_MASK) | \ 374 (((value) << CS_ACK_IRQ_MASK_PROTM_PEND_SHIFT) & CS_ACK_IRQ_MASK_PROTM_PEND_MASK)) 375 #define CS_ACK_IRQ_MASK_FATAL_SHIFT 30 376 #define CS_ACK_IRQ_MASK_FATAL_MASK (0x1 << CS_ACK_IRQ_MASK_FATAL_SHIFT) 377 #define CS_ACK_IRQ_MASK_FATAL_GET(reg_val) (((reg_val)&CS_ACK_IRQ_MASK_FATAL_MASK) >> CS_ACK_IRQ_MASK_FATAL_SHIFT) 378 #define CS_ACK_IRQ_MASK_FATAL_SET(reg_val, value) \ 379 (((reg_val) & ~CS_ACK_IRQ_MASK_FATAL_MASK) | \ 380 (((value) << CS_ACK_IRQ_MASK_FATAL_SHIFT) & CS_ACK_IRQ_MASK_FATAL_MASK)) 381 #define CS_ACK_IRQ_MASK_FAULT_SHIFT 31 382 #define CS_ACK_IRQ_MASK_FAULT_MASK (0x1 << CS_ACK_IRQ_MASK_FAULT_SHIFT) 383 #define CS_ACK_IRQ_MASK_FAULT_GET(reg_val) (((reg_val)&CS_ACK_IRQ_MASK_FAULT_MASK) >> CS_ACK_IRQ_MASK_FAULT_SHIFT) 384 #define CS_ACK_IRQ_MASK_FAULT_SET(reg_val, value) \ 385 (((reg_val) & ~CS_ACK_IRQ_MASK_FAULT_MASK) | \ 386 (((value) << CS_ACK_IRQ_MASK_FAULT_SHIFT) & CS_ACK_IRQ_MASK_FAULT_MASK)) 387 388 /* CS_BASE register */ 389 #define CS_BASE_POINTER_SHIFT 0 390 #define CS_BASE_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CS_BASE_POINTER_SHIFT) 391 #define CS_BASE_POINTER_GET(reg_val) (((reg_val)&CS_BASE_POINTER_MASK) >> CS_BASE_POINTER_SHIFT) 392 #define CS_BASE_POINTER_SET(reg_val, value) \ 393 (((reg_val) & ~CS_BASE_POINTER_MASK) | (((value) << CS_BASE_POINTER_SHIFT) & CS_BASE_POINTER_MASK)) 394 395 /* CS_SIZE register */ 396 #define CS_SIZE_SIZE_SHIFT 0 397 #define CS_SIZE_SIZE_MASK (0xFFFFFFFF << CS_SIZE_SIZE_SHIFT) 398 #define CS_SIZE_SIZE_GET(reg_val) (((reg_val)&CS_SIZE_SIZE_MASK) >> CS_SIZE_SIZE_SHIFT) 399 #define CS_SIZE_SIZE_SET(reg_val, value) \ 400 (((reg_val) & ~CS_SIZE_SIZE_MASK) | (((value) << CS_SIZE_SIZE_SHIFT) & CS_SIZE_SIZE_MASK)) 401 402 /* CS_TILER_HEAP_START register */ 403 #define CS_TILER_HEAP_START_POINTER_SHIFT 0 404 #define CS_TILER_HEAP_START_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CS_TILER_HEAP_START_POINTER_SHIFT) 405 #define CS_TILER_HEAP_START_POINTER_GET(reg_val) \ 406 (((reg_val)&CS_TILER_HEAP_START_POINTER_MASK) >> CS_TILER_HEAP_START_POINTER_SHIFT) 407 #define CS_TILER_HEAP_START_POINTER_SET(reg_val, value) \ 408 (((reg_val) & ~CS_TILER_HEAP_START_POINTER_MASK) | \ 409 (((value) << CS_TILER_HEAP_START_POINTER_SHIFT) & CS_TILER_HEAP_START_POINTER_MASK)) 410 /* HeapChunkPointer nested in CS_TILER_HEAP_START_POINTER */ 411 /* End of HeapChunkPointer nested in CS_TILER_HEAP_START_POINTER */ 412 413 /* CS_TILER_HEAP_END register */ 414 #define CS_TILER_HEAP_END_POINTER_SHIFT 0 415 #define CS_TILER_HEAP_END_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CS_TILER_HEAP_END_POINTER_SHIFT) 416 #define CS_TILER_HEAP_END_POINTER_GET(reg_val) \ 417 (((reg_val)&CS_TILER_HEAP_END_POINTER_MASK) >> CS_TILER_HEAP_END_POINTER_SHIFT) 418 #define CS_TILER_HEAP_END_POINTER_SET(reg_val, value) \ 419 (((reg_val) & ~CS_TILER_HEAP_END_POINTER_MASK) | \ 420 (((value) << CS_TILER_HEAP_END_POINTER_SHIFT) & CS_TILER_HEAP_END_POINTER_MASK)) 421 /* HeapChunkPointer nested in CS_TILER_HEAP_END_POINTER */ 422 /* End of HeapChunkPointer nested in CS_TILER_HEAP_END_POINTER */ 423 424 /* CS_USER_INPUT register */ 425 #define CS_USER_INPUT_POINTER_SHIFT 0 426 #define CS_USER_INPUT_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CS_USER_INPUT_POINTER_SHIFT) 427 #define CS_USER_INPUT_POINTER_GET(reg_val) (((reg_val)&CS_USER_INPUT_POINTER_MASK) >> CS_USER_INPUT_POINTER_SHIFT) 428 #define CS_USER_INPUT_POINTER_SET(reg_val, value) \ 429 (((reg_val) & ~CS_USER_INPUT_POINTER_MASK) | \ 430 (((value) << CS_USER_INPUT_POINTER_SHIFT) & CS_USER_INPUT_POINTER_MASK)) 431 432 /* CS_USER_OUTPUT register */ 433 #define CS_USER_OUTPUT_POINTER_SHIFT 0 434 #define CS_USER_OUTPUT_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CS_USER_OUTPUT_POINTER_SHIFT) 435 #define CS_USER_OUTPUT_POINTER_GET(reg_val) (((reg_val)&CS_USER_OUTPUT_POINTER_MASK) >> CS_USER_OUTPUT_POINTER_SHIFT) 436 #define CS_USER_OUTPUT_POINTER_SET(reg_val, value) \ 437 (((reg_val) & ~CS_USER_OUTPUT_POINTER_MASK) | \ 438 (((value) << CS_USER_OUTPUT_POINTER_SHIFT) & CS_USER_OUTPUT_POINTER_MASK)) 439 440 /* CS_INSTR_CONFIG register */ 441 #define CS_INSTR_CONFIG_JASID_SHIFT (0) 442 #define CS_INSTR_CONFIG_JASID_MASK ((u32)0xF << CS_INSTR_CONFIG_JASID_SHIFT) 443 #define CS_INSTR_CONFIG_JASID_GET(reg_val) (((reg_val)&CS_INSTR_CONFIG_JASID_MASK) >> CS_INSTR_CONFIG_JASID_SHIFT) 444 #define CS_INSTR_CONFIG_JASID_SET(reg_val, value) \ 445 (((reg_val) & ~CS_INSTR_CONFIG_JASID_MASK) | \ 446 (((value) << CS_INSTR_CONFIG_JASID_SHIFT) & CS_INSTR_CONFIG_JASID_MASK)) 447 #define CS_INSTR_CONFIG_EVENT_SIZE_SHIFT (4) 448 #define CS_INSTR_CONFIG_EVENT_SIZE_MASK ((u32)0xF << CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) 449 #define CS_INSTR_CONFIG_EVENT_SIZE_GET(reg_val) \ 450 (((reg_val)&CS_INSTR_CONFIG_EVENT_SIZE_MASK) >> CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) 451 #define CS_INSTR_CONFIG_EVENT_SIZE_SET(reg_val, value) \ 452 (((reg_val) & ~CS_INSTR_CONFIG_EVENT_SIZE_MASK) | \ 453 (((value) << CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) & CS_INSTR_CONFIG_EVENT_SIZE_MASK)) 454 #define CS_INSTR_CONFIG_EVENT_STATE_SHIFT (16) 455 #define CS_INSTR_CONFIG_EVENT_STATE_MASK ((u32)0xFF << CS_INSTR_CONFIG_EVENT_STATE_SHIFT) 456 #define CS_INSTR_CONFIG_EVENT_STATE_GET(reg_val) \ 457 (((reg_val)&CS_INSTR_CONFIG_EVENT_STATE_MASK) >> CS_INSTR_CONFIG_EVENT_STATE_SHIFT) 458 #define CS_INSTR_CONFIG_EVENT_STATE_SET(reg_val, value) \ 459 (((reg_val) & ~CS_INSTR_CONFIG_EVENT_STATE_MASK) | \ 460 (((value) << CS_INSTR_CONFIG_EVENT_STATE_SHIFT) & CS_INSTR_CONFIG_EVENT_STATE_MASK)) 461 462 /* CS_INSTR_BUFFER_SIZE register */ 463 #define CS_INSTR_BUFFER_SIZE_SIZE_SHIFT (0) 464 #define CS_INSTR_BUFFER_SIZE_SIZE_MASK ((u32)0xFFFFFFFF << CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) 465 #define CS_INSTR_BUFFER_SIZE_SIZE_GET(reg_val) \ 466 (((reg_val)&CS_INSTR_BUFFER_SIZE_SIZE_MASK) >> CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) 467 #define CS_INSTR_BUFFER_SIZE_SIZE_SET(reg_val, value) \ 468 (((reg_val) & ~CS_INSTR_BUFFER_SIZE_SIZE_MASK) | \ 469 (((value) << CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) & CS_INSTR_BUFFER_SIZE_SIZE_MASK)) 470 471 /* CS_INSTR_BUFFER_BASE register */ 472 #define CS_INSTR_BUFFER_BASE_POINTER_SHIFT (0) 473 #define CS_INSTR_BUFFER_BASE_POINTER_MASK ((u64)0xFFFFFFFFFFFFFFFF << CS_INSTR_BUFFER_BASE_POINTER_SHIFT) 474 #define CS_INSTR_BUFFER_BASE_POINTER_GET(reg_val) \ 475 (((reg_val)&CS_INSTR_BUFFER_BASE_POINTER_MASK) >> CS_INSTR_BUFFER_BASE_POINTER_SHIFT) 476 #define CS_INSTR_BUFFER_BASE_POINTER_SET(reg_val, value) \ 477 (((reg_val) & ~CS_INSTR_BUFFER_BASE_POINTER_MASK) | \ 478 (((value) << CS_INSTR_BUFFER_BASE_POINTER_SHIFT) & CS_INSTR_BUFFER_BASE_POINTER_MASK)) 479 480 /* CS_INSTR_BUFFER_OFFSET_POINTER register */ 481 #define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT (0) 482 #define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK \ 483 ((u64)0xFFFFFFFFFFFFFFFF) << CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) 484 #define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_GET(reg_val) \ 485 (((reg_val)&CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK) >> CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) 486 #define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SET(reg_val, value) \ 487 (((reg_val) & ~CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK) | \ 488 (((value) << CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) & CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK)) 489 490 /* End of CS_KERNEL_INPUT_BLOCK register set definitions */ 491 492 /* CS_KERNEL_OUTPUT_BLOCK register set definitions */ 493 494 /* CS_ACK register */ 495 #define CS_ACK_STATE_SHIFT 0 496 #define CS_ACK_STATE_MASK (0x7 << CS_ACK_STATE_SHIFT) 497 #define CS_ACK_STATE_GET(reg_val) (((reg_val)&CS_ACK_STATE_MASK) >> CS_ACK_STATE_SHIFT) 498 #define CS_ACK_STATE_SET(reg_val, value) \ 499 (((reg_val) & ~CS_ACK_STATE_MASK) | (((value) << CS_ACK_STATE_SHIFT) & CS_ACK_STATE_MASK)) 500 /* CS_ACK_STATE values */ 501 #define CS_ACK_STATE_STOP 0x0 502 #define CS_ACK_STATE_START 0x1 503 /* End of CS_ACK_STATE values */ 504 #define CS_ACK_EXTRACT_EVENT_SHIFT 4 505 #define CS_ACK_EXTRACT_EVENT_MASK (0x1 << CS_ACK_EXTRACT_EVENT_SHIFT) 506 #define CS_ACK_EXTRACT_EVENT_GET(reg_val) (((reg_val)&CS_ACK_EXTRACT_EVENT_MASK) >> CS_ACK_EXTRACT_EVENT_SHIFT) 507 #define CS_ACK_EXTRACT_EVENT_SET(reg_val, value) \ 508 (((reg_val) & ~CS_ACK_EXTRACT_EVENT_MASK) | (((value) << CS_ACK_EXTRACT_EVENT_SHIFT) & CS_ACK_EXTRACT_EVENT_MASK)) 509 #define CS_ACK_TILER_OOM_SHIFT 26 510 #define CS_ACK_TILER_OOM_MASK (0x1 << CS_ACK_TILER_OOM_SHIFT) 511 #define CS_ACK_TILER_OOM_GET(reg_val) (((reg_val)&CS_ACK_TILER_OOM_MASK) >> CS_ACK_TILER_OOM_SHIFT) 512 #define CS_ACK_TILER_OOM_SET(reg_val, value) \ 513 (((reg_val) & ~CS_ACK_TILER_OOM_MASK) | (((value) << CS_ACK_TILER_OOM_SHIFT) & CS_ACK_TILER_OOM_MASK)) 514 #define CS_ACK_PROTM_PEND_SHIFT 27 515 #define CS_ACK_PROTM_PEND_MASK (0x1 << CS_ACK_PROTM_PEND_SHIFT) 516 #define CS_ACK_PROTM_PEND_GET(reg_val) (((reg_val)&CS_ACK_PROTM_PEND_MASK) >> CS_ACK_PROTM_PEND_SHIFT) 517 #define CS_ACK_PROTM_PEND_SET(reg_val, value) \ 518 (((reg_val) & ~CS_ACK_PROTM_PEND_MASK) | (((value) << CS_ACK_PROTM_PEND_SHIFT) & CS_ACK_PROTM_PEND_MASK)) 519 #define CS_ACK_FATAL_SHIFT 30 520 #define CS_ACK_FATAL_MASK (0x1 << CS_ACK_FATAL_SHIFT) 521 #define CS_ACK_FATAL_GET(reg_val) (((reg_val)&CS_ACK_FATAL_MASK) >> CS_ACK_FATAL_SHIFT) 522 #define CS_ACK_FATAL_SET(reg_val, value) \ 523 (((reg_val) & ~CS_ACK_FATAL_MASK) | (((value) << CS_ACK_FATAL_SHIFT) & CS_ACK_FATAL_MASK)) 524 #define CS_ACK_FAULT_SHIFT 31 525 #define CS_ACK_FAULT_MASK (0x1 << CS_ACK_FAULT_SHIFT) 526 #define CS_ACK_FAULT_GET(reg_val) (((reg_val)&CS_ACK_FAULT_MASK) >> CS_ACK_FAULT_SHIFT) 527 #define CS_ACK_FAULT_SET(reg_val, value) \ 528 (((reg_val) & ~CS_ACK_FAULT_MASK) | (((value) << CS_ACK_FAULT_SHIFT) & CS_ACK_FAULT_MASK)) 529 530 /* CS_STATUS_CMD_PTR register */ 531 #define CS_STATUS_CMD_PTR_POINTER_SHIFT 0 532 #define CS_STATUS_CMD_PTR_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CS_STATUS_CMD_PTR_POINTER_SHIFT) 533 #define CS_STATUS_CMD_PTR_POINTER_GET(reg_val) \ 534 (((reg_val)&CS_STATUS_CMD_PTR_POINTER_MASK) >> CS_STATUS_CMD_PTR_POINTER_SHIFT) 535 #define CS_STATUS_CMD_PTR_POINTER_SET(reg_val, value) \ 536 (((reg_val) & ~CS_STATUS_CMD_PTR_POINTER_MASK) | \ 537 (((value) << CS_STATUS_CMD_PTR_POINTER_SHIFT) & CS_STATUS_CMD_PTR_POINTER_MASK)) 538 539 /* CS_STATUS_WAIT register */ 540 #define CS_STATUS_WAIT_SB_MASK_SHIFT 0 541 #define CS_STATUS_WAIT_SB_MASK_MASK (0xFFFF << CS_STATUS_WAIT_SB_MASK_SHIFT) 542 #define CS_STATUS_WAIT_SB_MASK_GET(reg_val) (((reg_val)&CS_STATUS_WAIT_SB_MASK_MASK) >> CS_STATUS_WAIT_SB_MASK_SHIFT) 543 #define CS_STATUS_WAIT_SB_MASK_SET(reg_val, value) \ 544 (((reg_val) & ~CS_STATUS_WAIT_SB_MASK_MASK) | \ 545 (((value) << CS_STATUS_WAIT_SB_MASK_SHIFT) & CS_STATUS_WAIT_SB_MASK_MASK)) 546 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT 24 547 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK (0xF << CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT) 548 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_GET(reg_val) \ 549 (((reg_val)&CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK) >> CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT) 550 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SET(reg_val, value) \ 551 (((reg_val) & ~CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK) | \ 552 (((value) << CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT) & CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK)) 553 /* CS_STATUS_WAIT_SYNC_WAIT_CONDITION values */ 554 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_LE 0x0 555 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_GT 0x1 556 /* End of CS_STATUS_WAIT_SYNC_WAIT_CONDITION values */ 557 #define CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT 28 558 #define CS_STATUS_WAIT_PROGRESS_WAIT_MASK (0x1 << CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT) 559 #define CS_STATUS_WAIT_PROGRESS_WAIT_GET(reg_val) \ 560 (((reg_val)&CS_STATUS_WAIT_PROGRESS_WAIT_MASK) >> CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT) 561 #define CS_STATUS_WAIT_PROGRESS_WAIT_SET(reg_val, value) \ 562 (((reg_val) & ~CS_STATUS_WAIT_PROGRESS_WAIT_MASK) | \ 563 (((value) << CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT) & CS_STATUS_WAIT_PROGRESS_WAIT_MASK)) 564 #define CS_STATUS_WAIT_PROTM_PEND_SHIFT 29 565 #define CS_STATUS_WAIT_PROTM_PEND_MASK (0x1 << CS_STATUS_WAIT_PROTM_PEND_SHIFT) 566 #define CS_STATUS_WAIT_PROTM_PEND_GET(reg_val) \ 567 (((reg_val)&CS_STATUS_WAIT_PROTM_PEND_MASK) >> CS_STATUS_WAIT_PROTM_PEND_SHIFT) 568 #define CS_STATUS_WAIT_PROTM_PEND_SET(reg_val, value) \ 569 (((reg_val) & ~CS_STATUS_WAIT_PROTM_PEND_MASK) | \ 570 (((value) << CS_STATUS_WAIT_PROTM_PEND_SHIFT) & CS_STATUS_WAIT_PROTM_PEND_MASK)) 571 #define CS_STATUS_WAIT_SYNC_WAIT_SHIFT 31 572 #define CS_STATUS_WAIT_SYNC_WAIT_MASK (0x1 << CS_STATUS_WAIT_SYNC_WAIT_SHIFT) 573 #define CS_STATUS_WAIT_SYNC_WAIT_GET(reg_val) \ 574 (((reg_val)&CS_STATUS_WAIT_SYNC_WAIT_MASK) >> CS_STATUS_WAIT_SYNC_WAIT_SHIFT) 575 #define CS_STATUS_WAIT_SYNC_WAIT_SET(reg_val, value) \ 576 (((reg_val) & ~CS_STATUS_WAIT_SYNC_WAIT_MASK) | \ 577 (((value) << CS_STATUS_WAIT_SYNC_WAIT_SHIFT) & CS_STATUS_WAIT_SYNC_WAIT_MASK)) 578 579 /* CS_STATUS_REQ_RESOURCE register */ 580 #define CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SHIFT 0 581 #define CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_MASK (0x1 << CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SHIFT) 582 #define CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_GET(reg_val) \ 583 (((reg_val)&CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_MASK) >> CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SHIFT) 584 #define CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SET(reg_val, value) \ 585 (((reg_val) & ~CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_MASK) | \ 586 (((value) << CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SHIFT) & CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_MASK)) 587 #define CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SHIFT 1 588 #define CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_MASK (0x1 << CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SHIFT) 589 #define CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_GET(reg_val) \ 590 (((reg_val)&CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_MASK) >> CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SHIFT) 591 #define CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SET(reg_val, value) \ 592 (((reg_val) & ~CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_MASK) | \ 593 (((value) << CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SHIFT) & CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_MASK)) 594 #define CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SHIFT 2 595 #define CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_MASK (0x1 << CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SHIFT) 596 #define CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_GET(reg_val) \ 597 (((reg_val)&CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_MASK) >> CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SHIFT) 598 #define CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SET(reg_val, value) \ 599 (((reg_val) & ~CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_MASK) | \ 600 (((value) << CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SHIFT) & CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_MASK)) 601 #define CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SHIFT 3 602 #define CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_MASK (0x1 << CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SHIFT) 603 #define CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_GET(reg_val) \ 604 (((reg_val)&CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_MASK) >> CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SHIFT) 605 #define CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SET(reg_val, value) \ 606 (((reg_val) & ~CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_MASK) | \ 607 (((value) << CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SHIFT) & CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_MASK)) 608 609 /* CS_STATUS_WAIT_SYNC_POINTER register */ 610 #define CS_STATUS_WAIT_SYNC_POINTER_POINTER_SHIFT 0 611 #define CS_STATUS_WAIT_SYNC_POINTER_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CS_STATUS_WAIT_SYNC_POINTER_POINTER_SHIFT) 612 #define CS_STATUS_WAIT_SYNC_POINTER_POINTER_GET(reg_val) \ 613 (((reg_val)&CS_STATUS_WAIT_SYNC_POINTER_POINTER_MASK) >> CS_STATUS_WAIT_SYNC_POINTER_POINTER_SHIFT) 614 #define CS_STATUS_WAIT_SYNC_POINTER_POINTER_SET(reg_val, value) \ 615 (((reg_val) & ~CS_STATUS_WAIT_SYNC_POINTER_POINTER_MASK) | \ 616 (((value) << CS_STATUS_WAIT_SYNC_POINTER_POINTER_SHIFT) & CS_STATUS_WAIT_SYNC_POINTER_POINTER_MASK)) 617 618 /* CS_STATUS_WAIT_SYNC_VALUE register */ 619 #define CS_STATUS_WAIT_SYNC_VALUE_VALUE_SHIFT 0 620 #define CS_STATUS_WAIT_SYNC_VALUE_VALUE_MASK (0xFFFFFFFF << CS_STATUS_WAIT_SYNC_VALUE_VALUE_SHIFT) 621 #define CS_STATUS_WAIT_SYNC_VALUE_VALUE_GET(reg_val) \ 622 (((reg_val)&CS_STATUS_WAIT_SYNC_VALUE_VALUE_MASK) >> CS_STATUS_WAIT_SYNC_VALUE_VALUE_SHIFT) 623 #define CS_STATUS_WAIT_SYNC_VALUE_VALUE_SET(reg_val, value) \ 624 (((reg_val) & ~CS_STATUS_WAIT_SYNC_VALUE_VALUE_MASK) | \ 625 (((value) << CS_STATUS_WAIT_SYNC_VALUE_VALUE_SHIFT) & CS_STATUS_WAIT_SYNC_VALUE_VALUE_MASK)) 626 627 /* CS_STATUS_SCOREBOARDS register */ 628 #define CS_STATUS_SCOREBOARDS_NONZERO_SHIFT (0) 629 #define CS_STATUS_SCOREBOARDS_NONZERO_MASK \ 630 ((0xFFFF) << CS_STATUS_SCOREBOARDS_NONZERO_SHIFT) 631 #define CS_STATUS_SCOREBOARDS_NONZERO_GET(reg_val) \ 632 (((reg_val)&CS_STATUS_SCOREBOARDS_NONZERO_MASK) >> \ 633 CS_STATUS_SCOREBOARDS_NONZERO_SHIFT) 634 #define CS_STATUS_SCOREBOARDS_NONZERO_SET(reg_val, value) \ 635 (((reg_val) & ~CS_STATUS_SCOREBOARDS_NONZERO_MASK) | \ 636 (((value) << CS_STATUS_SCOREBOARDS_NONZERO_SHIFT) & \ 637 CS_STATUS_SCOREBOARDS_NONZERO_MASK)) 638 639 /* CS_STATUS_BLOCKED_REASON register */ 640 #define CS_STATUS_BLOCKED_REASON_REASON_SHIFT (0) 641 #define CS_STATUS_BLOCKED_REASON_REASON_MASK \ 642 ((0xF) << CS_STATUS_BLOCKED_REASON_REASON_SHIFT) 643 #define CS_STATUS_BLOCKED_REASON_REASON_GET(reg_val) \ 644 (((reg_val)&CS_STATUS_BLOCKED_REASON_REASON_MASK) >> \ 645 CS_STATUS_BLOCKED_REASON_REASON_SHIFT) 646 #define CS_STATUS_BLOCKED_REASON_REASON_SET(reg_val, value) \ 647 (((reg_val) & ~CS_STATUS_BLOCKED_REASON_REASON_MASK) | \ 648 (((value) << CS_STATUS_BLOCKED_REASON_REASON_SHIFT) & \ 649 CS_STATUS_BLOCKED_REASON_REASON_MASK)) 650 /* CS_STATUS_BLOCKED_REASON_reason values */ 651 #define CS_STATUS_BLOCKED_REASON_REASON_UNBLOCKED 0x0 652 #define CS_STATUS_BLOCKED_REASON_REASON_WAIT 0x1 653 #define CS_STATUS_BLOCKED_REASON_REASON_PROGRESS_WAIT 0x2 654 #define CS_STATUS_BLOCKED_REASON_REASON_SYNC_WAIT 0x3 655 #define CS_STATUS_BLOCKED_REASON_REASON_DEFERRED 0x4 656 #define CS_STATUS_BLOCKED_REASON_REASON_RESOURCE 0x5 657 #define CS_STATUS_BLOCKED_REASON_REASON_FLUSH 0x6 658 /* End of CS_STATUS_BLOCKED_REASON_reason values */ 659 660 /* CS_FAULT register */ 661 #define CS_FAULT_EXCEPTION_TYPE_SHIFT 0 662 #define CS_FAULT_EXCEPTION_TYPE_MASK (0xFF << CS_FAULT_EXCEPTION_TYPE_SHIFT) 663 #define CS_FAULT_EXCEPTION_TYPE_GET(reg_val) (((reg_val)&CS_FAULT_EXCEPTION_TYPE_MASK) >> CS_FAULT_EXCEPTION_TYPE_SHIFT) 664 #define CS_FAULT_EXCEPTION_TYPE_SET(reg_val, value) \ 665 (((reg_val) & ~CS_FAULT_EXCEPTION_TYPE_MASK) | \ 666 (((value) << CS_FAULT_EXCEPTION_TYPE_SHIFT) & CS_FAULT_EXCEPTION_TYPE_MASK)) 667 /* CS_FAULT_EXCEPTION_TYPE values */ 668 #define CS_FAULT_EXCEPTION_TYPE_KABOOM 0x05 669 #define CS_FAULT_EXCEPTION_TYPE_CS_RESOURCE_TERMINATED 0x0F 670 #define CS_FAULT_EXCEPTION_TYPE_CS_BUS_FAULT 0x48 671 #define CS_FAULT_EXCEPTION_TYPE_CS_INHERIT_FAULT 0x4B 672 #define CS_FAULT_EXCEPTION_TYPE_INSTR_INVALID_PC 0x50 673 #define CS_FAULT_EXCEPTION_TYPE_INSTR_INVALID_ENC 0x51 674 #define CS_FAULT_EXCEPTION_TYPE_INSTR_BARRIER_FAULT 0x55 675 #define CS_FAULT_EXCEPTION_TYPE_DATA_INVALID_FAULT 0x58 676 #define CS_FAULT_EXCEPTION_TYPE_TILE_RANGE_FAULT 0x59 677 #define CS_FAULT_EXCEPTION_TYPE_ADDR_RANGE_FAULT 0x5A 678 #define CS_FAULT_EXCEPTION_TYPE_IMPRECISE_FAULT 0x5B 679 #define CS_FAULT_EXCEPTION_TYPE_RESOURCE_EVICTION_TIMEOUT 0x69 680 /* End of CS_FAULT_EXCEPTION_TYPE values */ 681 #define CS_FAULT_EXCEPTION_DATA_SHIFT 8 682 #define CS_FAULT_EXCEPTION_DATA_MASK (0xFFFFFF << CS_FAULT_EXCEPTION_DATA_SHIFT) 683 #define CS_FAULT_EXCEPTION_DATA_GET(reg_val) (((reg_val)&CS_FAULT_EXCEPTION_DATA_MASK) >> CS_FAULT_EXCEPTION_DATA_SHIFT) 684 #define CS_FAULT_EXCEPTION_DATA_SET(reg_val, value) \ 685 (((reg_val) & ~CS_FAULT_EXCEPTION_DATA_MASK) | \ 686 (((value) << CS_FAULT_EXCEPTION_DATA_SHIFT) & CS_FAULT_EXCEPTION_DATA_MASK)) 687 688 /* CS_FATAL register */ 689 #define CS_FATAL_EXCEPTION_TYPE_SHIFT 0 690 #define CS_FATAL_EXCEPTION_TYPE_MASK (0xFF << CS_FATAL_EXCEPTION_TYPE_SHIFT) 691 #define CS_FATAL_EXCEPTION_TYPE_GET(reg_val) (((reg_val)&CS_FATAL_EXCEPTION_TYPE_MASK) >> CS_FATAL_EXCEPTION_TYPE_SHIFT) 692 #define CS_FATAL_EXCEPTION_TYPE_SET(reg_val, value) \ 693 (((reg_val) & ~CS_FATAL_EXCEPTION_TYPE_MASK) | \ 694 (((value) << CS_FATAL_EXCEPTION_TYPE_SHIFT) & CS_FATAL_EXCEPTION_TYPE_MASK)) 695 /* CS_FATAL_EXCEPTION_TYPE values */ 696 #define CS_FATAL_EXCEPTION_TYPE_CS_CONFIG_FAULT 0x40 697 #define CS_FATAL_EXCEPTION_TYPE_CS_ENDPOINT_FAULT 0x44 698 #define CS_FATAL_EXCEPTION_TYPE_CS_BUS_FAULT 0x48 699 #define CS_FATAL_EXCEPTION_TYPE_CS_INVALID_INSTRUCTION 0x49 700 #define CS_FATAL_EXCEPTION_TYPE_CS_CALL_STACK_OVERFLOW 0x4A 701 #define CS_FATAL_EXCEPTION_TYPE_FIRMWARE_INTERNAL_ERROR 0x68 702 /* End of CS_FATAL_EXCEPTION_TYPE values */ 703 #define CS_FATAL_EXCEPTION_DATA_SHIFT 8 704 #define CS_FATAL_EXCEPTION_DATA_MASK (0xFFFFFF << CS_FATAL_EXCEPTION_DATA_SHIFT) 705 #define CS_FATAL_EXCEPTION_DATA_GET(reg_val) (((reg_val)&CS_FATAL_EXCEPTION_DATA_MASK) >> CS_FATAL_EXCEPTION_DATA_SHIFT) 706 #define CS_FATAL_EXCEPTION_DATA_SET(reg_val, value) \ 707 (((reg_val) & ~CS_FATAL_EXCEPTION_DATA_MASK) | \ 708 (((value) << CS_FATAL_EXCEPTION_DATA_SHIFT) & CS_FATAL_EXCEPTION_DATA_MASK)) 709 710 /* CS_FAULT_INFO register */ 711 #define CS_FAULT_INFO_EXCEPTION_DATA_SHIFT 0 712 #define CS_FAULT_INFO_EXCEPTION_DATA_MASK (0xFFFFFFFFFFFFFFFF << CS_FAULT_INFO_EXCEPTION_DATA_SHIFT) 713 #define CS_FAULT_INFO_EXCEPTION_DATA_GET(reg_val) \ 714 (((reg_val)&CS_FAULT_INFO_EXCEPTION_DATA_MASK) >> CS_FAULT_INFO_EXCEPTION_DATA_SHIFT) 715 #define CS_FAULT_INFO_EXCEPTION_DATA_SET(reg_val, value) \ 716 (((reg_val) & ~CS_FAULT_INFO_EXCEPTION_DATA_MASK) | \ 717 (((value) << CS_FAULT_INFO_EXCEPTION_DATA_SHIFT) & CS_FAULT_INFO_EXCEPTION_DATA_MASK)) 718 719 /* CS_FATAL_INFO register */ 720 #define CS_FATAL_INFO_EXCEPTION_DATA_SHIFT 0 721 #define CS_FATAL_INFO_EXCEPTION_DATA_MASK (0xFFFFFFFFFFFFFFFF << CS_FATAL_INFO_EXCEPTION_DATA_SHIFT) 722 #define CS_FATAL_INFO_EXCEPTION_DATA_GET(reg_val) \ 723 (((reg_val)&CS_FATAL_INFO_EXCEPTION_DATA_MASK) >> CS_FATAL_INFO_EXCEPTION_DATA_SHIFT) 724 #define CS_FATAL_INFO_EXCEPTION_DATA_SET(reg_val, value) \ 725 (((reg_val) & ~CS_FATAL_INFO_EXCEPTION_DATA_MASK) | \ 726 (((value) << CS_FATAL_INFO_EXCEPTION_DATA_SHIFT) & CS_FATAL_INFO_EXCEPTION_DATA_MASK)) 727 728 /* CS_HEAP_VT_START register */ 729 #define CS_HEAP_VT_START_VALUE_SHIFT 0 730 #define CS_HEAP_VT_START_VALUE_MASK (0xFFFFFFFF << CS_HEAP_VT_START_VALUE_SHIFT) 731 #define CS_HEAP_VT_START_VALUE_GET(reg_val) (((reg_val)&CS_HEAP_VT_START_VALUE_MASK) >> CS_HEAP_VT_START_VALUE_SHIFT) 732 #define CS_HEAP_VT_START_VALUE_SET(reg_val, value) \ 733 (((reg_val) & ~CS_HEAP_VT_START_VALUE_MASK) | \ 734 (((value) << CS_HEAP_VT_START_VALUE_SHIFT) & CS_HEAP_VT_START_VALUE_MASK)) 735 736 /* CS_HEAP_VT_END register */ 737 #define CS_HEAP_VT_END_VALUE_SHIFT 0 738 #define CS_HEAP_VT_END_VALUE_MASK (0xFFFFFFFF << CS_HEAP_VT_END_VALUE_SHIFT) 739 #define CS_HEAP_VT_END_VALUE_GET(reg_val) (((reg_val)&CS_HEAP_VT_END_VALUE_MASK) >> CS_HEAP_VT_END_VALUE_SHIFT) 740 #define CS_HEAP_VT_END_VALUE_SET(reg_val, value) \ 741 (((reg_val) & ~CS_HEAP_VT_END_VALUE_MASK) | (((value) << CS_HEAP_VT_END_VALUE_SHIFT) & CS_HEAP_VT_END_VALUE_MASK)) 742 743 /* CS_HEAP_FRAG_END register */ 744 #define CS_HEAP_FRAG_END_VALUE_SHIFT 0 745 #define CS_HEAP_FRAG_END_VALUE_MASK (0xFFFFFFFF << CS_HEAP_FRAG_END_VALUE_SHIFT) 746 #define CS_HEAP_FRAG_END_VALUE_GET(reg_val) (((reg_val)&CS_HEAP_FRAG_END_VALUE_MASK) >> CS_HEAP_FRAG_END_VALUE_SHIFT) 747 #define CS_HEAP_FRAG_END_VALUE_SET(reg_val, value) \ 748 (((reg_val) & ~CS_HEAP_FRAG_END_VALUE_MASK) | \ 749 (((value) << CS_HEAP_FRAG_END_VALUE_SHIFT) & CS_HEAP_FRAG_END_VALUE_MASK)) 750 751 /* CS_HEAP_ADDRESS register */ 752 #define CS_HEAP_ADDRESS_POINTER_SHIFT 0 753 #define CS_HEAP_ADDRESS_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CS_HEAP_ADDRESS_POINTER_SHIFT) 754 #define CS_HEAP_ADDRESS_POINTER_GET(reg_val) (((reg_val)&CS_HEAP_ADDRESS_POINTER_MASK) >> CS_HEAP_ADDRESS_POINTER_SHIFT) 755 #define CS_HEAP_ADDRESS_POINTER_SET(reg_val, value) \ 756 (((reg_val) & ~CS_HEAP_ADDRESS_POINTER_MASK) | \ 757 (((value) << CS_HEAP_ADDRESS_POINTER_SHIFT) & CS_HEAP_ADDRESS_POINTER_MASK)) 758 /* End of CS_KERNEL_OUTPUT_BLOCK register set definitions */ 759 760 /* CS_USER_INPUT_BLOCK register set definitions */ 761 762 /* CS_INSERT register */ 763 #define CS_INSERT_VALUE_SHIFT 0 764 #define CS_INSERT_VALUE_MASK (0xFFFFFFFFFFFFFFFF << CS_INSERT_VALUE_SHIFT) 765 #define CS_INSERT_VALUE_GET(reg_val) (((reg_val)&CS_INSERT_VALUE_MASK) >> CS_INSERT_VALUE_SHIFT) 766 #define CS_INSERT_VALUE_SET(reg_val, value) \ 767 (((reg_val) & ~CS_INSERT_VALUE_MASK) | (((value) << CS_INSERT_VALUE_SHIFT) & CS_INSERT_VALUE_MASK)) 768 769 /* CS_EXTRACT_INIT register */ 770 #define CS_EXTRACT_INIT_VALUE_SHIFT 0 771 #define CS_EXTRACT_INIT_VALUE_MASK (0xFFFFFFFFFFFFFFFF << CS_EXTRACT_INIT_VALUE_SHIFT) 772 #define CS_EXTRACT_INIT_VALUE_GET(reg_val) (((reg_val)&CS_EXTRACT_INIT_VALUE_MASK) >> CS_EXTRACT_INIT_VALUE_SHIFT) 773 #define CS_EXTRACT_INIT_VALUE_SET(reg_val, value) \ 774 (((reg_val) & ~CS_EXTRACT_INIT_VALUE_MASK) | \ 775 (((value) << CS_EXTRACT_INIT_VALUE_SHIFT) & CS_EXTRACT_INIT_VALUE_MASK)) 776 /* End of CS_USER_INPUT_BLOCK register set definitions */ 777 778 /* CS_USER_OUTPUT_BLOCK register set definitions */ 779 780 /* CS_EXTRACT register */ 781 #define CS_EXTRACT_VALUE_SHIFT 0 782 #define CS_EXTRACT_VALUE_MASK (0xFFFFFFFFFFFFFFFF << CS_EXTRACT_VALUE_SHIFT) 783 #define CS_EXTRACT_VALUE_GET(reg_val) (((reg_val)&CS_EXTRACT_VALUE_MASK) >> CS_EXTRACT_VALUE_SHIFT) 784 #define CS_EXTRACT_VALUE_SET(reg_val, value) \ 785 (((reg_val) & ~CS_EXTRACT_VALUE_MASK) | (((value) << CS_EXTRACT_VALUE_SHIFT) & CS_EXTRACT_VALUE_MASK)) 786 787 /* CS_ACTIVE register */ 788 #define CS_ACTIVE_HW_ACTIVE_SHIFT 0 789 #define CS_ACTIVE_HW_ACTIVE_MASK (0x1 << CS_ACTIVE_HW_ACTIVE_SHIFT) 790 #define CS_ACTIVE_HW_ACTIVE_GET(reg_val) (((reg_val)&CS_ACTIVE_HW_ACTIVE_MASK) >> CS_ACTIVE_HW_ACTIVE_SHIFT) 791 #define CS_ACTIVE_HW_ACTIVE_SET(reg_val, value) \ 792 (((reg_val) & ~CS_ACTIVE_HW_ACTIVE_MASK) | (((value) << CS_ACTIVE_HW_ACTIVE_SHIFT) & CS_ACTIVE_HW_ACTIVE_MASK)) 793 /* End of CS_USER_OUTPUT_BLOCK register set definitions */ 794 795 /* CSG_INPUT_BLOCK register set definitions */ 796 797 /* CSG_REQ register */ 798 #define CSG_REQ_STATE_SHIFT 0 799 #define CSG_REQ_STATE_MASK (0x7 << CSG_REQ_STATE_SHIFT) 800 #define CSG_REQ_STATE_GET(reg_val) (((reg_val)&CSG_REQ_STATE_MASK) >> CSG_REQ_STATE_SHIFT) 801 #define CSG_REQ_STATE_SET(reg_val, value) \ 802 (((reg_val) & ~CSG_REQ_STATE_MASK) | (((value) << CSG_REQ_STATE_SHIFT) & CSG_REQ_STATE_MASK)) 803 /* CSG_REQ_STATE values */ 804 #define CSG_REQ_STATE_TERMINATE 0x0 805 #define CSG_REQ_STATE_START 0x1 806 #define CSG_REQ_STATE_SUSPEND 0x2 807 #define CSG_REQ_STATE_RESUME 0x3 808 /* End of CSG_REQ_STATE values */ 809 #define CSG_REQ_EP_CFG_SHIFT 4 810 #define CSG_REQ_EP_CFG_MASK (0x1 << CSG_REQ_EP_CFG_SHIFT) 811 #define CSG_REQ_EP_CFG_GET(reg_val) (((reg_val)&CSG_REQ_EP_CFG_MASK) >> CSG_REQ_EP_CFG_SHIFT) 812 #define CSG_REQ_EP_CFG_SET(reg_val, value) \ 813 (((reg_val) & ~CSG_REQ_EP_CFG_MASK) | (((value) << CSG_REQ_EP_CFG_SHIFT) & CSG_REQ_EP_CFG_MASK)) 814 #define CSG_REQ_STATUS_UPDATE_SHIFT 5 815 #define CSG_REQ_STATUS_UPDATE_MASK (0x1 << CSG_REQ_STATUS_UPDATE_SHIFT) 816 #define CSG_REQ_STATUS_UPDATE_GET(reg_val) (((reg_val)&CSG_REQ_STATUS_UPDATE_MASK) >> CSG_REQ_STATUS_UPDATE_SHIFT) 817 #define CSG_REQ_STATUS_UPDATE_SET(reg_val, value) \ 818 (((reg_val) & ~CSG_REQ_STATUS_UPDATE_MASK) | \ 819 (((value) << CSG_REQ_STATUS_UPDATE_SHIFT) & CSG_REQ_STATUS_UPDATE_MASK)) 820 #define CSG_REQ_SYNC_UPDATE_SHIFT 28 821 #define CSG_REQ_SYNC_UPDATE_MASK (0x1 << CSG_REQ_SYNC_UPDATE_SHIFT) 822 #define CSG_REQ_SYNC_UPDATE_GET(reg_val) (((reg_val)&CSG_REQ_SYNC_UPDATE_MASK) >> CSG_REQ_SYNC_UPDATE_SHIFT) 823 #define CSG_REQ_SYNC_UPDATE_SET(reg_val, value) \ 824 (((reg_val) & ~CSG_REQ_SYNC_UPDATE_MASK) | (((value) << CSG_REQ_SYNC_UPDATE_SHIFT) & CSG_REQ_SYNC_UPDATE_MASK)) 825 #define CSG_REQ_IDLE_SHIFT 29 826 #define CSG_REQ_IDLE_MASK (0x1 << CSG_REQ_IDLE_SHIFT) 827 #define CSG_REQ_IDLE_GET(reg_val) (((reg_val)&CSG_REQ_IDLE_MASK) >> CSG_REQ_IDLE_SHIFT) 828 #define CSG_REQ_IDLE_SET(reg_val, value) \ 829 (((reg_val) & ~CSG_REQ_IDLE_MASK) | (((value) << CSG_REQ_IDLE_SHIFT) & CSG_REQ_IDLE_MASK)) 830 #define CSG_REQ_DOORBELL_SHIFT 30 831 #define CSG_REQ_DOORBELL_MASK (0x1 << CSG_REQ_DOORBELL_SHIFT) 832 #define CSG_REQ_DOORBELL_GET(reg_val) (((reg_val)&CSG_REQ_DOORBELL_MASK) >> CSG_REQ_DOORBELL_SHIFT) 833 #define CSG_REQ_DOORBELL_SET(reg_val, value) \ 834 (((reg_val) & ~CSG_REQ_DOORBELL_MASK) | (((value) << CSG_REQ_DOORBELL_SHIFT) & CSG_REQ_DOORBELL_MASK)) 835 #define CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT 31 836 #define CSG_REQ_PROGRESS_TIMER_EVENT_MASK (0x1 << CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT) 837 #define CSG_REQ_PROGRESS_TIMER_EVENT_GET(reg_val) \ 838 (((reg_val)&CSG_REQ_PROGRESS_TIMER_EVENT_MASK) >> CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT) 839 #define CSG_REQ_PROGRESS_TIMER_EVENT_SET(reg_val, value) \ 840 (((reg_val) & ~CSG_REQ_PROGRESS_TIMER_EVENT_MASK) | \ 841 (((value) << CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT) & CSG_REQ_PROGRESS_TIMER_EVENT_MASK)) 842 843 /* CSG_ACK_IRQ_MASK register */ 844 #define CSG_ACK_IRQ_MASK_STATE_SHIFT 0 845 #define CSG_ACK_IRQ_MASK_STATE_MASK (0x7 << CSG_ACK_IRQ_MASK_STATE_SHIFT) 846 #define CSG_ACK_IRQ_MASK_STATE_GET(reg_val) (((reg_val)&CSG_ACK_IRQ_MASK_STATE_MASK) >> CSG_ACK_IRQ_MASK_STATE_SHIFT) 847 #define CSG_ACK_IRQ_MASK_STATE_SET(reg_val, value) \ 848 (((reg_val) & ~CSG_ACK_IRQ_MASK_STATE_MASK) | \ 849 (((value) << CSG_ACK_IRQ_MASK_STATE_SHIFT) & CSG_ACK_IRQ_MASK_STATE_MASK)) 850 /* CSG_ACK_IRQ_MASK_STATE values */ 851 #define CSG_ACK_IRQ_MASK_STATE_DISABLED 0x0 852 #define CSG_ACK_IRQ_MASK_STATE_ENABLED 0x7 853 /* End of CSG_ACK_IRQ_MASK_STATE values */ 854 #define CSG_ACK_IRQ_MASK_EP_CFG_SHIFT 4 855 #define CSG_ACK_IRQ_MASK_EP_CFG_MASK (0x1 << CSG_ACK_IRQ_MASK_EP_CFG_SHIFT) 856 #define CSG_ACK_IRQ_MASK_EP_CFG_GET(reg_val) (((reg_val)&CSG_ACK_IRQ_MASK_EP_CFG_MASK) >> CSG_ACK_IRQ_MASK_EP_CFG_SHIFT) 857 #define CSG_ACK_IRQ_MASK_EP_CFG_SET(reg_val, value) \ 858 (((reg_val) & ~CSG_ACK_IRQ_MASK_EP_CFG_MASK) | \ 859 (((value) << CSG_ACK_IRQ_MASK_EP_CFG_SHIFT) & CSG_ACK_IRQ_MASK_EP_CFG_MASK)) 860 #define CSG_ACK_IRQ_MASK_STATUS_UPDATE_SHIFT 5 861 #define CSG_ACK_IRQ_MASK_STATUS_UPDATE_MASK (0x1 << CSG_ACK_IRQ_MASK_STATUS_UPDATE_SHIFT) 862 #define CSG_ACK_IRQ_MASK_STATUS_UPDATE_GET(reg_val) \ 863 (((reg_val)&CSG_ACK_IRQ_MASK_STATUS_UPDATE_MASK) >> CSG_ACK_IRQ_MASK_STATUS_UPDATE_SHIFT) 864 #define CSG_ACK_IRQ_MASK_STATUS_UPDATE_SET(reg_val, value) \ 865 (((reg_val) & ~CSG_ACK_IRQ_MASK_STATUS_UPDATE_MASK) | \ 866 (((value) << CSG_ACK_IRQ_MASK_STATUS_UPDATE_SHIFT) & CSG_ACK_IRQ_MASK_STATUS_UPDATE_MASK)) 867 #define CSG_ACK_IRQ_MASK_SYNC_UPDATE_SHIFT 28 868 #define CSG_ACK_IRQ_MASK_SYNC_UPDATE_MASK (0x1 << CSG_ACK_IRQ_MASK_SYNC_UPDATE_SHIFT) 869 #define CSG_ACK_IRQ_MASK_SYNC_UPDATE_GET(reg_val) \ 870 (((reg_val)&CSG_ACK_IRQ_MASK_SYNC_UPDATE_MASK) >> CSG_ACK_IRQ_MASK_SYNC_UPDATE_SHIFT) 871 #define CSG_ACK_IRQ_MASK_SYNC_UPDATE_SET(reg_val, value) \ 872 (((reg_val) & ~CSG_ACK_IRQ_MASK_SYNC_UPDATE_MASK) | \ 873 (((value) << CSG_ACK_IRQ_MASK_SYNC_UPDATE_SHIFT) & CSG_ACK_IRQ_MASK_SYNC_UPDATE_MASK)) 874 #define CSG_ACK_IRQ_MASK_IDLE_SHIFT 29 875 #define CSG_ACK_IRQ_MASK_IDLE_MASK (0x1 << CSG_ACK_IRQ_MASK_IDLE_SHIFT) 876 #define CSG_ACK_IRQ_MASK_IDLE_GET(reg_val) (((reg_val)&CSG_ACK_IRQ_MASK_IDLE_MASK) >> CSG_ACK_IRQ_MASK_IDLE_SHIFT) 877 #define CSG_ACK_IRQ_MASK_IDLE_SET(reg_val, value) \ 878 (((reg_val) & ~CSG_ACK_IRQ_MASK_IDLE_MASK) | \ 879 (((value) << CSG_ACK_IRQ_MASK_IDLE_SHIFT) & CSG_ACK_IRQ_MASK_IDLE_MASK)) 880 #define CSG_ACK_IRQ_MASK_DOORBELL_SHIFT 30 881 #define CSG_ACK_IRQ_MASK_DOORBELL_MASK (0x1 << CSG_ACK_IRQ_MASK_DOORBELL_SHIFT) 882 #define CSG_ACK_IRQ_MASK_DOORBELL_GET(reg_val) \ 883 (((reg_val)&CSG_ACK_IRQ_MASK_DOORBELL_MASK) >> CSG_ACK_IRQ_MASK_DOORBELL_SHIFT) 884 #define CSG_ACK_IRQ_MASK_DOORBELL_SET(reg_val, value) \ 885 (((reg_val) & ~CSG_ACK_IRQ_MASK_DOORBELL_MASK) | \ 886 (((value) << CSG_ACK_IRQ_MASK_DOORBELL_SHIFT) & CSG_ACK_IRQ_MASK_DOORBELL_MASK)) 887 #define CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SHIFT 31 888 #define CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_MASK (0x1 << CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SHIFT) 889 #define CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_GET(reg_val) \ 890 (((reg_val)&CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_MASK) >> CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SHIFT) 891 #define CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SET(reg_val, value) \ 892 (((reg_val) & ~CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_MASK) | \ 893 (((value) << CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SHIFT) & CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_MASK)) 894 895 /* CSG_EP_REQ register */ 896 #define CSG_EP_REQ_COMPUTE_EP_SHIFT 0 897 #define CSG_EP_REQ_COMPUTE_EP_MASK (0xFF << CSG_EP_REQ_COMPUTE_EP_SHIFT) 898 #define CSG_EP_REQ_COMPUTE_EP_GET(reg_val) (((reg_val)&CSG_EP_REQ_COMPUTE_EP_MASK) >> CSG_EP_REQ_COMPUTE_EP_SHIFT) 899 #define CSG_EP_REQ_COMPUTE_EP_SET(reg_val, value) \ 900 (((reg_val) & ~CSG_EP_REQ_COMPUTE_EP_MASK) | \ 901 (((value) << CSG_EP_REQ_COMPUTE_EP_SHIFT) & CSG_EP_REQ_COMPUTE_EP_MASK)) 902 #define CSG_EP_REQ_FRAGMENT_EP_SHIFT 8 903 #define CSG_EP_REQ_FRAGMENT_EP_MASK (0xFF << CSG_EP_REQ_FRAGMENT_EP_SHIFT) 904 #define CSG_EP_REQ_FRAGMENT_EP_GET(reg_val) (((reg_val)&CSG_EP_REQ_FRAGMENT_EP_MASK) >> CSG_EP_REQ_FRAGMENT_EP_SHIFT) 905 #define CSG_EP_REQ_FRAGMENT_EP_SET(reg_val, value) \ 906 (((reg_val) & ~CSG_EP_REQ_FRAGMENT_EP_MASK) | \ 907 (((value) << CSG_EP_REQ_FRAGMENT_EP_SHIFT) & CSG_EP_REQ_FRAGMENT_EP_MASK)) 908 #define CSG_EP_REQ_TILER_EP_SHIFT 16 909 #define CSG_EP_REQ_TILER_EP_MASK (0xF << CSG_EP_REQ_TILER_EP_SHIFT) 910 #define CSG_EP_REQ_TILER_EP_GET(reg_val) (((reg_val)&CSG_EP_REQ_TILER_EP_MASK) >> CSG_EP_REQ_TILER_EP_SHIFT) 911 #define CSG_EP_REQ_TILER_EP_SET(reg_val, value) \ 912 (((reg_val) & ~CSG_EP_REQ_TILER_EP_MASK) | (((value) << CSG_EP_REQ_TILER_EP_SHIFT) & CSG_EP_REQ_TILER_EP_MASK)) 913 #define CSG_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT 20 914 #define CSG_EP_REQ_EXCLUSIVE_COMPUTE_MASK (0x1 << CSG_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) 915 #define CSG_EP_REQ_EXCLUSIVE_COMPUTE_GET(reg_val) \ 916 (((reg_val)&CSG_EP_REQ_EXCLUSIVE_COMPUTE_MASK) >> CSG_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) 917 #define CSG_EP_REQ_EXCLUSIVE_COMPUTE_SET(reg_val, value) \ 918 (((reg_val) & ~CSG_EP_REQ_EXCLUSIVE_COMPUTE_MASK) | \ 919 (((value) << CSG_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) & CSG_EP_REQ_EXCLUSIVE_COMPUTE_MASK)) 920 #define CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT 21 921 #define CSG_EP_REQ_EXCLUSIVE_FRAGMENT_MASK (0x1 << CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) 922 #define CSG_EP_REQ_EXCLUSIVE_FRAGMENT_GET(reg_val) \ 923 (((reg_val)&CSG_EP_REQ_EXCLUSIVE_FRAGMENT_MASK) >> CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) 924 #define CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SET(reg_val, value) \ 925 (((reg_val) & ~CSG_EP_REQ_EXCLUSIVE_FRAGMENT_MASK) | \ 926 (((value) << CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) & CSG_EP_REQ_EXCLUSIVE_FRAGMENT_MASK)) 927 #define CSG_EP_REQ_PRIORITY_SHIFT 28 928 #define CSG_EP_REQ_PRIORITY_MASK (0xF << CSG_EP_REQ_PRIORITY_SHIFT) 929 #define CSG_EP_REQ_PRIORITY_GET(reg_val) (((reg_val)&CSG_EP_REQ_PRIORITY_MASK) >> CSG_EP_REQ_PRIORITY_SHIFT) 930 #define CSG_EP_REQ_PRIORITY_SET(reg_val, value) \ 931 (((reg_val) & ~CSG_EP_REQ_PRIORITY_MASK) | (((value) << CSG_EP_REQ_PRIORITY_SHIFT) & CSG_EP_REQ_PRIORITY_MASK)) 932 933 /* CSG_SUSPEND_BUF register */ 934 #define CSG_SUSPEND_BUF_POINTER_SHIFT 0 935 #define CSG_SUSPEND_BUF_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CSG_SUSPEND_BUF_POINTER_SHIFT) 936 #define CSG_SUSPEND_BUF_POINTER_GET(reg_val) (((reg_val)&CSG_SUSPEND_BUF_POINTER_MASK) >> CSG_SUSPEND_BUF_POINTER_SHIFT) 937 #define CSG_SUSPEND_BUF_POINTER_SET(reg_val, value) \ 938 (((reg_val) & ~CSG_SUSPEND_BUF_POINTER_MASK) | \ 939 (((value) << CSG_SUSPEND_BUF_POINTER_SHIFT) & CSG_SUSPEND_BUF_POINTER_MASK)) 940 941 /* CSG_PROTM_SUSPEND_BUF register */ 942 #define CSG_PROTM_SUSPEND_BUF_POINTER_SHIFT 0 943 #define CSG_PROTM_SUSPEND_BUF_POINTER_MASK (0xFFFFFFFFFFFFFFFF << CSG_PROTM_SUSPEND_BUF_POINTER_SHIFT) 944 #define CSG_PROTM_SUSPEND_BUF_POINTER_GET(reg_val) \ 945 (((reg_val)&CSG_PROTM_SUSPEND_BUF_POINTER_MASK) >> CSG_PROTM_SUSPEND_BUF_POINTER_SHIFT) 946 #define CSG_PROTM_SUSPEND_BUF_POINTER_SET(reg_val, value) \ 947 (((reg_val) & ~CSG_PROTM_SUSPEND_BUF_POINTER_MASK) | \ 948 (((value) << CSG_PROTM_SUSPEND_BUF_POINTER_SHIFT) & CSG_PROTM_SUSPEND_BUF_POINTER_MASK)) 949 950 951 /* End of CSG_INPUT_BLOCK register set definitions */ 952 953 /* CSG_OUTPUT_BLOCK register set definitions */ 954 955 /* CSG_ACK register */ 956 #define CSG_ACK_STATE_SHIFT 0 957 #define CSG_ACK_STATE_MASK (0x7 << CSG_ACK_STATE_SHIFT) 958 #define CSG_ACK_STATE_GET(reg_val) (((reg_val)&CSG_ACK_STATE_MASK) >> CSG_ACK_STATE_SHIFT) 959 #define CSG_ACK_STATE_SET(reg_val, value) \ 960 (((reg_val) & ~CSG_ACK_STATE_MASK) | (((value) << CSG_ACK_STATE_SHIFT) & CSG_ACK_STATE_MASK)) 961 /* CSG_ACK_STATE values */ 962 #define CSG_ACK_STATE_TERMINATE 0x0 963 #define CSG_ACK_STATE_START 0x1 964 #define CSG_ACK_STATE_SUSPEND 0x2 965 #define CSG_ACK_STATE_RESUME 0x3 966 /* End of CSG_ACK_STATE values */ 967 #define CSG_ACK_EP_CFG_SHIFT 4 968 #define CSG_ACK_EP_CFG_MASK (0x1 << CSG_ACK_EP_CFG_SHIFT) 969 #define CSG_ACK_EP_CFG_GET(reg_val) (((reg_val)&CSG_ACK_EP_CFG_MASK) >> CSG_ACK_EP_CFG_SHIFT) 970 #define CSG_ACK_EP_CFG_SET(reg_val, value) \ 971 (((reg_val) & ~CSG_ACK_EP_CFG_MASK) | (((value) << CSG_ACK_EP_CFG_SHIFT) & CSG_ACK_EP_CFG_MASK)) 972 #define CSG_ACK_STATUS_UPDATE_SHIFT 5 973 #define CSG_ACK_STATUS_UPDATE_MASK (0x1 << CSG_ACK_STATUS_UPDATE_SHIFT) 974 #define CSG_ACK_STATUS_UPDATE_GET(reg_val) (((reg_val)&CSG_ACK_STATUS_UPDATE_MASK) >> CSG_ACK_STATUS_UPDATE_SHIFT) 975 #define CSG_ACK_STATUS_UPDATE_SET(reg_val, value) \ 976 (((reg_val) & ~CSG_ACK_STATUS_UPDATE_MASK) | \ 977 (((value) << CSG_ACK_STATUS_UPDATE_SHIFT) & CSG_ACK_STATUS_UPDATE_MASK)) 978 #define CSG_ACK_SYNC_UPDATE_SHIFT 28 979 #define CSG_ACK_SYNC_UPDATE_MASK (0x1 << CSG_ACK_SYNC_UPDATE_SHIFT) 980 #define CSG_ACK_SYNC_UPDATE_GET(reg_val) (((reg_val)&CSG_ACK_SYNC_UPDATE_MASK) >> CSG_ACK_SYNC_UPDATE_SHIFT) 981 #define CSG_ACK_SYNC_UPDATE_SET(reg_val, value) \ 982 (((reg_val) & ~CSG_ACK_SYNC_UPDATE_MASK) | (((value) << CSG_ACK_SYNC_UPDATE_SHIFT) & CSG_ACK_SYNC_UPDATE_MASK)) 983 #define CSG_ACK_IDLE_SHIFT 29 984 #define CSG_ACK_IDLE_MASK (0x1 << CSG_ACK_IDLE_SHIFT) 985 #define CSG_ACK_IDLE_GET(reg_val) (((reg_val)&CSG_ACK_IDLE_MASK) >> CSG_ACK_IDLE_SHIFT) 986 #define CSG_ACK_IDLE_SET(reg_val, value) \ 987 (((reg_val) & ~CSG_ACK_IDLE_MASK) | (((value) << CSG_ACK_IDLE_SHIFT) & CSG_ACK_IDLE_MASK)) 988 #define CSG_ACK_DOORBELL_SHIFT 30 989 #define CSG_ACK_DOORBELL_MASK (0x1 << CSG_ACK_DOORBELL_SHIFT) 990 #define CSG_ACK_DOORBELL_GET(reg_val) (((reg_val)&CSG_ACK_DOORBELL_MASK) >> CSG_ACK_DOORBELL_SHIFT) 991 #define CSG_ACK_DOORBELL_SET(reg_val, value) \ 992 (((reg_val) & ~CSG_ACK_DOORBELL_MASK) | (((value) << CSG_ACK_DOORBELL_SHIFT) & CSG_ACK_DOORBELL_MASK)) 993 #define CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT 31 994 #define CSG_ACK_PROGRESS_TIMER_EVENT_MASK (0x1 << CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT) 995 #define CSG_ACK_PROGRESS_TIMER_EVENT_GET(reg_val) \ 996 (((reg_val)&CSG_ACK_PROGRESS_TIMER_EVENT_MASK) >> CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT) 997 #define CSG_ACK_PROGRESS_TIMER_EVENT_SET(reg_val, value) \ 998 (((reg_val) & ~CSG_ACK_PROGRESS_TIMER_EVENT_MASK) | \ 999 (((value) << CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT) & CSG_ACK_PROGRESS_TIMER_EVENT_MASK)) 1000 1001 /* CSG_STATUS_EP_CURRENT register */ 1002 #define CSG_STATUS_EP_CURRENT_COMPUTE_EP_SHIFT 0 1003 #define CSG_STATUS_EP_CURRENT_COMPUTE_EP_MASK (0xFF << CSG_STATUS_EP_CURRENT_COMPUTE_EP_SHIFT) 1004 #define CSG_STATUS_EP_CURRENT_COMPUTE_EP_GET(reg_val) \ 1005 (((reg_val)&CSG_STATUS_EP_CURRENT_COMPUTE_EP_MASK) >> CSG_STATUS_EP_CURRENT_COMPUTE_EP_SHIFT) 1006 #define CSG_STATUS_EP_CURRENT_COMPUTE_EP_SET(reg_val, value) \ 1007 (((reg_val) & ~CSG_STATUS_EP_CURRENT_COMPUTE_EP_MASK) | \ 1008 (((value) << CSG_STATUS_EP_CURRENT_COMPUTE_EP_SHIFT) & CSG_STATUS_EP_CURRENT_COMPUTE_EP_MASK)) 1009 #define CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SHIFT 8 1010 #define CSG_STATUS_EP_CURRENT_FRAGMENT_EP_MASK (0xFF << CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SHIFT) 1011 #define CSG_STATUS_EP_CURRENT_FRAGMENT_EP_GET(reg_val) \ 1012 (((reg_val)&CSG_STATUS_EP_CURRENT_FRAGMENT_EP_MASK) >> CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SHIFT) 1013 #define CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SET(reg_val, value) \ 1014 (((reg_val) & ~CSG_STATUS_EP_CURRENT_FRAGMENT_EP_MASK) | \ 1015 (((value) << CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SHIFT) & CSG_STATUS_EP_CURRENT_FRAGMENT_EP_MASK)) 1016 #define CSG_STATUS_EP_CURRENT_TILER_EP_SHIFT 16 1017 #define CSG_STATUS_EP_CURRENT_TILER_EP_MASK (0xF << CSG_STATUS_EP_CURRENT_TILER_EP_SHIFT) 1018 #define CSG_STATUS_EP_CURRENT_TILER_EP_GET(reg_val) \ 1019 (((reg_val)&CSG_STATUS_EP_CURRENT_TILER_EP_MASK) >> CSG_STATUS_EP_CURRENT_TILER_EP_SHIFT) 1020 #define CSG_STATUS_EP_CURRENT_TILER_EP_SET(reg_val, value) \ 1021 (((reg_val) & ~CSG_STATUS_EP_CURRENT_TILER_EP_MASK) | \ 1022 (((value) << CSG_STATUS_EP_CURRENT_TILER_EP_SHIFT) & CSG_STATUS_EP_CURRENT_TILER_EP_MASK)) 1023 1024 /* CSG_STATUS_EP_REQ register */ 1025 #define CSG_STATUS_EP_REQ_COMPUTE_EP_SHIFT 0 1026 #define CSG_STATUS_EP_REQ_COMPUTE_EP_MASK (0xFF << CSG_STATUS_EP_REQ_COMPUTE_EP_SHIFT) 1027 #define CSG_STATUS_EP_REQ_COMPUTE_EP_GET(reg_val) \ 1028 (((reg_val)&CSG_STATUS_EP_REQ_COMPUTE_EP_MASK) >> CSG_STATUS_EP_REQ_COMPUTE_EP_SHIFT) 1029 #define CSG_STATUS_EP_REQ_COMPUTE_EP_SET(reg_val, value) \ 1030 (((reg_val) & ~CSG_STATUS_EP_REQ_COMPUTE_EP_MASK) | \ 1031 (((value) << CSG_STATUS_EP_REQ_COMPUTE_EP_SHIFT) & CSG_STATUS_EP_REQ_COMPUTE_EP_MASK)) 1032 #define CSG_STATUS_EP_REQ_FRAGMENT_EP_SHIFT 8 1033 #define CSG_STATUS_EP_REQ_FRAGMENT_EP_MASK (0xFF << CSG_STATUS_EP_REQ_FRAGMENT_EP_SHIFT) 1034 #define CSG_STATUS_EP_REQ_FRAGMENT_EP_GET(reg_val) \ 1035 (((reg_val)&CSG_STATUS_EP_REQ_FRAGMENT_EP_MASK) >> CSG_STATUS_EP_REQ_FRAGMENT_EP_SHIFT) 1036 #define CSG_STATUS_EP_REQ_FRAGMENT_EP_SET(reg_val, value) \ 1037 (((reg_val) & ~CSG_STATUS_EP_REQ_FRAGMENT_EP_MASK) | \ 1038 (((value) << CSG_STATUS_EP_REQ_FRAGMENT_EP_SHIFT) & CSG_STATUS_EP_REQ_FRAGMENT_EP_MASK)) 1039 #define CSG_STATUS_EP_REQ_TILER_EP_SHIFT 16 1040 #define CSG_STATUS_EP_REQ_TILER_EP_MASK (0xF << CSG_STATUS_EP_REQ_TILER_EP_SHIFT) 1041 #define CSG_STATUS_EP_REQ_TILER_EP_GET(reg_val) \ 1042 (((reg_val)&CSG_STATUS_EP_REQ_TILER_EP_MASK) >> CSG_STATUS_EP_REQ_TILER_EP_SHIFT) 1043 #define CSG_STATUS_EP_REQ_TILER_EP_SET(reg_val, value) \ 1044 (((reg_val) & ~CSG_STATUS_EP_REQ_TILER_EP_MASK) | \ 1045 (((value) << CSG_STATUS_EP_REQ_TILER_EP_SHIFT) & CSG_STATUS_EP_REQ_TILER_EP_MASK)) 1046 #define CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT 20 1047 #define CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_MASK (0x1 << CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) 1048 #define CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_GET(reg_val) \ 1049 (((reg_val)&CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_MASK) >> CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) 1050 #define CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SET(reg_val, value) \ 1051 (((reg_val) & ~CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_MASK) | \ 1052 (((value) << CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) & CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_MASK)) 1053 #define CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT 21 1054 #define CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_MASK (0x1 << CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) 1055 #define CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_GET(reg_val) \ 1056 (((reg_val)&CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_MASK) >> CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) 1057 #define CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SET(reg_val, value) \ 1058 (((reg_val) & ~CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_MASK) | \ 1059 (((value) << CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) & CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_MASK)) 1060 1061 /* End of CSG_OUTPUT_BLOCK register set definitions */ 1062 1063 /* STREAM_CONTROL_BLOCK register set definitions */ 1064 1065 /* STREAM_FEATURES register */ 1066 #define STREAM_FEATURES_WORK_REGISTERS_SHIFT 0 1067 #define STREAM_FEATURES_WORK_REGISTERS_MASK (0xFF << STREAM_FEATURES_WORK_REGISTERS_SHIFT) 1068 #define STREAM_FEATURES_WORK_REGISTERS_GET(reg_val) \ 1069 (((reg_val)&STREAM_FEATURES_WORK_REGISTERS_MASK) >> STREAM_FEATURES_WORK_REGISTERS_SHIFT) 1070 #define STREAM_FEATURES_WORK_REGISTERS_SET(reg_val, value) \ 1071 (((reg_val) & ~STREAM_FEATURES_WORK_REGISTERS_MASK) | \ 1072 (((value) << STREAM_FEATURES_WORK_REGISTERS_SHIFT) & STREAM_FEATURES_WORK_REGISTERS_MASK)) 1073 #define STREAM_FEATURES_SCOREBOARDS_SHIFT 8 1074 #define STREAM_FEATURES_SCOREBOARDS_MASK (0xFF << STREAM_FEATURES_SCOREBOARDS_SHIFT) 1075 #define STREAM_FEATURES_SCOREBOARDS_GET(reg_val) \ 1076 (((reg_val)&STREAM_FEATURES_SCOREBOARDS_MASK) >> STREAM_FEATURES_SCOREBOARDS_SHIFT) 1077 #define STREAM_FEATURES_SCOREBOARDS_SET(reg_val, value) \ 1078 (((reg_val) & ~STREAM_FEATURES_SCOREBOARDS_MASK) | \ 1079 (((value) << STREAM_FEATURES_SCOREBOARDS_SHIFT) & STREAM_FEATURES_SCOREBOARDS_MASK)) 1080 #define STREAM_FEATURES_COMPUTE_SHIFT 16 1081 #define STREAM_FEATURES_COMPUTE_MASK (0x1 << STREAM_FEATURES_COMPUTE_SHIFT) 1082 #define STREAM_FEATURES_COMPUTE_GET(reg_val) (((reg_val)&STREAM_FEATURES_COMPUTE_MASK) >> STREAM_FEATURES_COMPUTE_SHIFT) 1083 #define STREAM_FEATURES_COMPUTE_SET(reg_val, value) \ 1084 (((reg_val) & ~STREAM_FEATURES_COMPUTE_MASK) | \ 1085 (((value) << STREAM_FEATURES_COMPUTE_SHIFT) & STREAM_FEATURES_COMPUTE_MASK)) 1086 #define STREAM_FEATURES_FRAGMENT_SHIFT 17 1087 #define STREAM_FEATURES_FRAGMENT_MASK (0x1 << STREAM_FEATURES_FRAGMENT_SHIFT) 1088 #define STREAM_FEATURES_FRAGMENT_GET(reg_val) \ 1089 (((reg_val)&STREAM_FEATURES_FRAGMENT_MASK) >> STREAM_FEATURES_FRAGMENT_SHIFT) 1090 #define STREAM_FEATURES_FRAGMENT_SET(reg_val, value) \ 1091 (((reg_val) & ~STREAM_FEATURES_FRAGMENT_MASK) | \ 1092 (((value) << STREAM_FEATURES_FRAGMENT_SHIFT) & STREAM_FEATURES_FRAGMENT_MASK)) 1093 #define STREAM_FEATURES_TILER_SHIFT 18 1094 #define STREAM_FEATURES_TILER_MASK (0x1 << STREAM_FEATURES_TILER_SHIFT) 1095 #define STREAM_FEATURES_TILER_GET(reg_val) (((reg_val)&STREAM_FEATURES_TILER_MASK) >> STREAM_FEATURES_TILER_SHIFT) 1096 #define STREAM_FEATURES_TILER_SET(reg_val, value) \ 1097 (((reg_val) & ~STREAM_FEATURES_TILER_MASK) | \ 1098 (((value) << STREAM_FEATURES_TILER_SHIFT) & STREAM_FEATURES_TILER_MASK)) 1099 1100 /* STREAM_INPUT_VA register */ 1101 #define STREAM_INPUT_VA_VALUE_SHIFT 0 1102 #define STREAM_INPUT_VA_VALUE_MASK (0xFFFFFFFF << STREAM_INPUT_VA_VALUE_SHIFT) 1103 #define STREAM_INPUT_VA_VALUE_GET(reg_val) (((reg_val)&STREAM_INPUT_VA_VALUE_MASK) >> STREAM_INPUT_VA_VALUE_SHIFT) 1104 #define STREAM_INPUT_VA_VALUE_SET(reg_val, value) \ 1105 (((reg_val) & ~STREAM_INPUT_VA_VALUE_MASK) | \ 1106 (((value) << STREAM_INPUT_VA_VALUE_SHIFT) & STREAM_INPUT_VA_VALUE_MASK)) 1107 1108 /* STREAM_OUTPUT_VA register */ 1109 #define STREAM_OUTPUT_VA_VALUE_SHIFT 0 1110 #define STREAM_OUTPUT_VA_VALUE_MASK (0xFFFFFFFF << STREAM_OUTPUT_VA_VALUE_SHIFT) 1111 #define STREAM_OUTPUT_VA_VALUE_GET(reg_val) (((reg_val)&STREAM_OUTPUT_VA_VALUE_MASK) >> STREAM_OUTPUT_VA_VALUE_SHIFT) 1112 #define STREAM_OUTPUT_VA_VALUE_SET(reg_val, value) \ 1113 (((reg_val) & ~STREAM_OUTPUT_VA_VALUE_MASK) | \ 1114 (((value) << STREAM_OUTPUT_VA_VALUE_SHIFT) & STREAM_OUTPUT_VA_VALUE_MASK)) 1115 /* End of STREAM_CONTROL_BLOCK register set definitions */ 1116 1117 /* GLB_INPUT_BLOCK register set definitions */ 1118 1119 /* GLB_REQ register */ 1120 #define GLB_REQ_HALT_SHIFT 0 1121 #define GLB_REQ_HALT_MASK (0x1 << GLB_REQ_HALT_SHIFT) 1122 #define GLB_REQ_HALT_GET(reg_val) (((reg_val)&GLB_REQ_HALT_MASK) >> GLB_REQ_HALT_SHIFT) 1123 #define GLB_REQ_HALT_SET(reg_val, value) \ 1124 (((reg_val) & ~GLB_REQ_HALT_MASK) | (((value) << GLB_REQ_HALT_SHIFT) & GLB_REQ_HALT_MASK)) 1125 #define GLB_REQ_CFG_PROGRESS_TIMER_SHIFT 1 1126 #define GLB_REQ_CFG_PROGRESS_TIMER_MASK (0x1 << GLB_REQ_CFG_PROGRESS_TIMER_SHIFT) 1127 #define GLB_REQ_CFG_PROGRESS_TIMER_GET(reg_val) \ 1128 (((reg_val)&GLB_REQ_CFG_PROGRESS_TIMER_MASK) >> GLB_REQ_CFG_PROGRESS_TIMER_SHIFT) 1129 #define GLB_REQ_CFG_PROGRESS_TIMER_SET(reg_val, value) \ 1130 (((reg_val) & ~GLB_REQ_CFG_PROGRESS_TIMER_MASK) | \ 1131 (((value) << GLB_REQ_CFG_PROGRESS_TIMER_SHIFT) & GLB_REQ_CFG_PROGRESS_TIMER_MASK)) 1132 #define GLB_REQ_CFG_ALLOC_EN_SHIFT 2 1133 #define GLB_REQ_CFG_ALLOC_EN_MASK (0x1 << GLB_REQ_CFG_ALLOC_EN_SHIFT) 1134 #define GLB_REQ_CFG_ALLOC_EN_GET(reg_val) (((reg_val)&GLB_REQ_CFG_ALLOC_EN_MASK) >> GLB_REQ_CFG_ALLOC_EN_SHIFT) 1135 #define GLB_REQ_CFG_ALLOC_EN_SET(reg_val, value) \ 1136 (((reg_val) & ~GLB_REQ_CFG_ALLOC_EN_MASK) | (((value) << GLB_REQ_CFG_ALLOC_EN_SHIFT) & GLB_REQ_CFG_ALLOC_EN_MASK)) 1137 #define GLB_REQ_CFG_PWROFF_TIMER_SHIFT 3 1138 #define GLB_REQ_CFG_PWROFF_TIMER_MASK (0x1 << GLB_REQ_CFG_PWROFF_TIMER_SHIFT) 1139 #define GLB_REQ_CFG_PWROFF_TIMER_GET(reg_val) \ 1140 (((reg_val)&GLB_REQ_CFG_PWROFF_TIMER_MASK) >> GLB_REQ_CFG_PWROFF_TIMER_SHIFT) 1141 #define GLB_REQ_CFG_PWROFF_TIMER_SET(reg_val, value) \ 1142 (((reg_val) & ~GLB_REQ_CFG_PWROFF_TIMER_MASK) | \ 1143 (((value) << GLB_REQ_CFG_PWROFF_TIMER_SHIFT) & GLB_REQ_CFG_PWROFF_TIMER_MASK)) 1144 #define GLB_REQ_PROTM_ENTER_SHIFT 4 1145 #define GLB_REQ_PROTM_ENTER_MASK (0x1 << GLB_REQ_PROTM_ENTER_SHIFT) 1146 #define GLB_REQ_PROTM_ENTER_GET(reg_val) (((reg_val)&GLB_REQ_PROTM_ENTER_MASK) >> GLB_REQ_PROTM_ENTER_SHIFT) 1147 #define GLB_REQ_PROTM_ENTER_SET(reg_val, value) \ 1148 (((reg_val) & ~GLB_REQ_PROTM_ENTER_MASK) | (((value) << GLB_REQ_PROTM_ENTER_SHIFT) & GLB_REQ_PROTM_ENTER_MASK)) 1149 #define GLB_REQ_PRFCNT_ENABLE_SHIFT 5 1150 #define GLB_REQ_PRFCNT_ENABLE_MASK (0x1 << GLB_REQ_PRFCNT_ENABLE_SHIFT) 1151 #define GLB_REQ_PRFCNT_ENABLE_GET(reg_val) (((reg_val)&GLB_REQ_PRFCNT_ENABLE_MASK) >> GLB_REQ_PRFCNT_ENABLE_SHIFT) 1152 #define GLB_REQ_PRFCNT_ENABLE_SET(reg_val, value) \ 1153 (((reg_val) & ~GLB_REQ_PRFCNT_ENABLE_MASK) | \ 1154 (((value) << GLB_REQ_PRFCNT_ENABLE_SHIFT) & GLB_REQ_PRFCNT_ENABLE_MASK)) 1155 #define GLB_REQ_PRFCNT_SAMPLE_SHIFT 6 1156 #define GLB_REQ_PRFCNT_SAMPLE_MASK (0x1 << GLB_REQ_PRFCNT_SAMPLE_SHIFT) 1157 #define GLB_REQ_PRFCNT_SAMPLE_GET(reg_val) (((reg_val)&GLB_REQ_PRFCNT_SAMPLE_MASK) >> GLB_REQ_PRFCNT_SAMPLE_SHIFT) 1158 #define GLB_REQ_PRFCNT_SAMPLE_SET(reg_val, value) \ 1159 (((reg_val) & ~GLB_REQ_PRFCNT_SAMPLE_MASK) | \ 1160 (((value) << GLB_REQ_PRFCNT_SAMPLE_SHIFT) & GLB_REQ_PRFCNT_SAMPLE_MASK)) 1161 #define GLB_REQ_COUNTER_ENABLE_SHIFT 7 1162 #define GLB_REQ_COUNTER_ENABLE_MASK (0x1 << GLB_REQ_COUNTER_ENABLE_SHIFT) 1163 #define GLB_REQ_COUNTER_ENABLE_GET(reg_val) (((reg_val)&GLB_REQ_COUNTER_ENABLE_MASK) >> GLB_REQ_COUNTER_ENABLE_SHIFT) 1164 #define GLB_REQ_COUNTER_ENABLE_SET(reg_val, value) \ 1165 (((reg_val) & ~GLB_REQ_COUNTER_ENABLE_MASK) | \ 1166 (((value) << GLB_REQ_COUNTER_ENABLE_SHIFT) & GLB_REQ_COUNTER_ENABLE_MASK)) 1167 #define GLB_REQ_PING_SHIFT 8 1168 #define GLB_REQ_PING_MASK (0x1 << GLB_REQ_PING_SHIFT) 1169 #define GLB_REQ_PING_GET(reg_val) (((reg_val)&GLB_REQ_PING_MASK) >> GLB_REQ_PING_SHIFT) 1170 #define GLB_REQ_PING_SET(reg_val, value) \ 1171 (((reg_val) & ~GLB_REQ_PING_MASK) | (((value) << GLB_REQ_PING_SHIFT) & GLB_REQ_PING_MASK)) 1172 #define GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT 9 1173 #define GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK \ 1174 (0x1 << GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT) 1175 #define GLB_REQ_FIRMWARE_CONFIG_UPDATE_GET(reg_val) \ 1176 (((reg_val)&GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK) >> \ 1177 GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT) 1178 #define GLB_REQ_FIRMWARE_CONFIG_UPDATE_SET(reg_val, value) \ 1179 (((reg_val) & ~GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK) | \ 1180 (((value) << GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT) & \ 1181 GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK)) 1182 #define GLB_REQ_SLEEP_SHIFT 12 1183 #define GLB_REQ_SLEEP_MASK (0x1 << GLB_REQ_SLEEP_SHIFT) 1184 #define GLB_REQ_SLEEP_GET(reg_val) \ 1185 (((reg_val) & GLB_REQ_SLEEP_MASK) >> GLB_REQ_SLEEP_SHIFT) 1186 #define GLB_REQ_SLEEP_SET(reg_val, value) \ 1187 (((reg_val) & ~GLB_REQ_SLEEP_MASK) | \ 1188 (((value) << GLB_REQ_SLEEP_SHIFT) & GLB_REQ_SLEEP_MASK)) 1189 #define GLB_REQ_INACTIVE_COMPUTE_SHIFT 20 1190 #define GLB_REQ_INACTIVE_COMPUTE_MASK (0x1 << GLB_REQ_INACTIVE_COMPUTE_SHIFT) 1191 #define GLB_REQ_INACTIVE_COMPUTE_GET(reg_val) \ 1192 (((reg_val)&GLB_REQ_INACTIVE_COMPUTE_MASK) >> GLB_REQ_INACTIVE_COMPUTE_SHIFT) 1193 #define GLB_REQ_INACTIVE_COMPUTE_SET(reg_val, value) \ 1194 (((reg_val) & ~GLB_REQ_INACTIVE_COMPUTE_MASK) | \ 1195 (((value) << GLB_REQ_INACTIVE_COMPUTE_SHIFT) & GLB_REQ_INACTIVE_COMPUTE_MASK)) 1196 #define GLB_REQ_INACTIVE_FRAGMENT_SHIFT 21 1197 #define GLB_REQ_INACTIVE_FRAGMENT_MASK (0x1 << GLB_REQ_INACTIVE_FRAGMENT_SHIFT) 1198 #define GLB_REQ_INACTIVE_FRAGMENT_GET(reg_val) \ 1199 (((reg_val)&GLB_REQ_INACTIVE_FRAGMENT_MASK) >> GLB_REQ_INACTIVE_FRAGMENT_SHIFT) 1200 #define GLB_REQ_INACTIVE_FRAGMENT_SET(reg_val, value) \ 1201 (((reg_val) & ~GLB_REQ_INACTIVE_FRAGMENT_MASK) | \ 1202 (((value) << GLB_REQ_INACTIVE_FRAGMENT_SHIFT) & GLB_REQ_INACTIVE_FRAGMENT_MASK)) 1203 #define GLB_REQ_INACTIVE_TILER_SHIFT 22 1204 #define GLB_REQ_INACTIVE_TILER_MASK (0x1 << GLB_REQ_INACTIVE_TILER_SHIFT) 1205 #define GLB_REQ_INACTIVE_TILER_GET(reg_val) (((reg_val)&GLB_REQ_INACTIVE_TILER_MASK) >> GLB_REQ_INACTIVE_TILER_SHIFT) 1206 #define GLB_REQ_INACTIVE_TILER_SET(reg_val, value) \ 1207 (((reg_val) & ~GLB_REQ_INACTIVE_TILER_MASK) | \ 1208 (((value) << GLB_REQ_INACTIVE_TILER_SHIFT) & GLB_REQ_INACTIVE_TILER_MASK)) 1209 #define GLB_REQ_PROTM_EXIT_SHIFT 23 1210 #define GLB_REQ_PROTM_EXIT_MASK (0x1 << GLB_REQ_PROTM_EXIT_SHIFT) 1211 #define GLB_REQ_PROTM_EXIT_GET(reg_val) (((reg_val)&GLB_REQ_PROTM_EXIT_MASK) >> GLB_REQ_PROTM_EXIT_SHIFT) 1212 #define GLB_REQ_PROTM_EXIT_SET(reg_val, value) \ 1213 (((reg_val) & ~GLB_REQ_PROTM_EXIT_MASK) | (((value) << GLB_REQ_PROTM_EXIT_SHIFT) & GLB_REQ_PROTM_EXIT_MASK)) 1214 #define GLB_REQ_PRFCNT_THRESHOLD_SHIFT 24 1215 #define GLB_REQ_PRFCNT_THRESHOLD_MASK (0x1 << GLB_REQ_PRFCNT_THRESHOLD_SHIFT) 1216 #define GLB_REQ_PRFCNT_THRESHOLD_GET(reg_val) \ 1217 (((reg_val)&GLB_REQ_PRFCNT_THRESHOLD_MASK) >> \ 1218 GLB_REQ_PRFCNT_THRESHOLD_SHIFT) 1219 #define GLB_REQ_PRFCNT_THRESHOLD_SET(reg_val, value) \ 1220 (((reg_val) & ~GLB_REQ_PRFCNT_THRESHOLD_MASK) | \ 1221 (((value) << GLB_REQ_PRFCNT_THRESHOLD_SHIFT) & \ 1222 GLB_REQ_PRFCNT_THRESHOLD_MASK)) 1223 #define GLB_REQ_PRFCNT_OVERFLOW_SHIFT 25 1224 #define GLB_REQ_PRFCNT_OVERFLOW_MASK (0x1 << GLB_REQ_PRFCNT_OVERFLOW_SHIFT) 1225 #define GLB_REQ_PRFCNT_OVERFLOW_GET(reg_val) \ 1226 (((reg_val)&GLB_REQ_PRFCNT_OVERFLOW_MASK) >> \ 1227 GLB_REQ_PRFCNT_OVERFLOW_SHIFT) 1228 #define GLB_REQ_PRFCNT_OVERFLOW_SET(reg_val, value) \ 1229 (((reg_val) & ~GLB_REQ_PRFCNT_OVERFLOW_MASK) | \ 1230 (((value) << GLB_REQ_PRFCNT_OVERFLOW_SHIFT) & \ 1231 GLB_REQ_PRFCNT_OVERFLOW_MASK)) 1232 #define GLB_REQ_DEBUG_CSF_REQ_SHIFT 30 1233 #define GLB_REQ_DEBUG_CSF_REQ_MASK (0x1 << GLB_REQ_DEBUG_CSF_REQ_SHIFT) 1234 #define GLB_REQ_DEBUG_CSF_REQ_GET(reg_val) (((reg_val)&GLB_REQ_DEBUG_CSF_REQ_MASK) >> GLB_REQ_DEBUG_CSF_REQ_SHIFT) 1235 #define GLB_REQ_DEBUG_CSF_REQ_SET(reg_val, value) \ 1236 (((reg_val) & ~GLB_REQ_DEBUG_CSF_REQ_MASK) | \ 1237 (((value) << GLB_REQ_DEBUG_CSF_REQ_SHIFT) & GLB_REQ_DEBUG_CSF_REQ_MASK)) 1238 #define GLB_REQ_DEBUG_HOST_REQ_SHIFT 31 1239 #define GLB_REQ_DEBUG_HOST_REQ_MASK (0x1 << GLB_REQ_DEBUG_HOST_REQ_SHIFT) 1240 #define GLB_REQ_DEBUG_HOST_REQ_GET(reg_val) (((reg_val)&GLB_REQ_DEBUG_HOST_REQ_MASK) >> GLB_REQ_DEBUG_HOST_REQ_SHIFT) 1241 #define GLB_REQ_DEBUG_HOST_REQ_SET(reg_val, value) \ 1242 (((reg_val) & ~GLB_REQ_DEBUG_HOST_REQ_MASK) | \ 1243 (((value) << GLB_REQ_DEBUG_HOST_REQ_SHIFT) & GLB_REQ_DEBUG_HOST_REQ_MASK)) 1244 1245 /* GLB_ACK_IRQ_MASK register */ 1246 #define GLB_ACK_IRQ_MASK_HALT_SHIFT 0 1247 #define GLB_ACK_IRQ_MASK_HALT_MASK (0x1 << GLB_ACK_IRQ_MASK_HALT_SHIFT) 1248 #define GLB_ACK_IRQ_MASK_HALT_GET(reg_val) (((reg_val)&GLB_ACK_IRQ_MASK_HALT_MASK) >> GLB_ACK_IRQ_MASK_HALT_SHIFT) 1249 #define GLB_ACK_IRQ_MASK_HALT_SET(reg_val, value) \ 1250 (((reg_val) & ~GLB_ACK_IRQ_MASK_HALT_MASK) | \ 1251 (((value) << GLB_ACK_IRQ_MASK_HALT_SHIFT) & GLB_ACK_IRQ_MASK_HALT_MASK)) 1252 #define GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SHIFT 1 1253 #define GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_MASK (0x1 << GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SHIFT) 1254 #define GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_GET(reg_val) \ 1255 (((reg_val)&GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_MASK) >> GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SHIFT) 1256 #define GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SET(reg_val, value) \ 1257 (((reg_val) & ~GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_MASK) | \ 1258 (((value) << GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SHIFT) & GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_MASK)) 1259 #define GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SHIFT 2 1260 #define GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_MASK (0x1 << GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SHIFT) 1261 #define GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_GET(reg_val) \ 1262 (((reg_val)&GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_MASK) >> GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SHIFT) 1263 #define GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SET(reg_val, value) \ 1264 (((reg_val) & ~GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_MASK) | \ 1265 (((value) << GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SHIFT) & GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_MASK)) 1266 #define GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SHIFT 3 1267 #define GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_MASK (0x1 << GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SHIFT) 1268 #define GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_GET(reg_val) \ 1269 (((reg_val)&GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_MASK) >> GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SHIFT) 1270 #define GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SET(reg_val, value) \ 1271 (((reg_val) & ~GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_MASK) | \ 1272 (((value) << GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SHIFT) & GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_MASK)) 1273 #define GLB_ACK_IRQ_MASK_PROTM_ENTER_SHIFT 4 1274 #define GLB_ACK_IRQ_MASK_PROTM_ENTER_MASK (0x1 << GLB_ACK_IRQ_MASK_PROTM_ENTER_SHIFT) 1275 #define GLB_ACK_IRQ_MASK_PROTM_ENTER_GET(reg_val) \ 1276 (((reg_val)&GLB_ACK_IRQ_MASK_PROTM_ENTER_MASK) >> GLB_ACK_IRQ_MASK_PROTM_ENTER_SHIFT) 1277 #define GLB_ACK_IRQ_MASK_PROTM_ENTER_SET(reg_val, value) \ 1278 (((reg_val) & ~GLB_ACK_IRQ_MASK_PROTM_ENTER_MASK) | \ 1279 (((value) << GLB_ACK_IRQ_MASK_PROTM_ENTER_SHIFT) & GLB_ACK_IRQ_MASK_PROTM_ENTER_MASK)) 1280 #define GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SHIFT 5 1281 #define GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_MASK (0x1 << GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SHIFT) 1282 #define GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_GET(reg_val) \ 1283 (((reg_val)&GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_MASK) >> GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SHIFT) 1284 #define GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SET(reg_val, value) \ 1285 (((reg_val) & ~GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_MASK) | \ 1286 (((value) << GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SHIFT) & GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_MASK)) 1287 #define GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SHIFT 6 1288 #define GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_MASK (0x1 << GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SHIFT) 1289 #define GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_GET(reg_val) \ 1290 (((reg_val)&GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_MASK) >> GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SHIFT) 1291 #define GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SET(reg_val, value) \ 1292 (((reg_val) & ~GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_MASK) | \ 1293 (((value) << GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SHIFT) & GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_MASK)) 1294 #define GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SHIFT 7 1295 #define GLB_ACK_IRQ_MASK_COUNTER_ENABLE_MASK (0x1 << GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SHIFT) 1296 #define GLB_ACK_IRQ_MASK_COUNTER_ENABLE_GET(reg_val) \ 1297 (((reg_val)&GLB_ACK_IRQ_MASK_COUNTER_ENABLE_MASK) >> GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SHIFT) 1298 #define GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SET(reg_val, value) \ 1299 (((reg_val) & ~GLB_ACK_IRQ_MASK_COUNTER_ENABLE_MASK) | \ 1300 (((value) << GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SHIFT) & GLB_ACK_IRQ_MASK_COUNTER_ENABLE_MASK)) 1301 #define GLB_ACK_IRQ_MASK_PING_SHIFT 8 1302 #define GLB_ACK_IRQ_MASK_PING_MASK (0x1 << GLB_ACK_IRQ_MASK_PING_SHIFT) 1303 #define GLB_ACK_IRQ_MASK_PING_GET(reg_val) (((reg_val)&GLB_ACK_IRQ_MASK_PING_MASK) >> GLB_ACK_IRQ_MASK_PING_SHIFT) 1304 #define GLB_ACK_IRQ_MASK_PING_SET(reg_val, value) \ 1305 (((reg_val) & ~GLB_ACK_IRQ_MASK_PING_MASK) | \ 1306 (((value) << GLB_ACK_IRQ_MASK_PING_SHIFT) & GLB_ACK_IRQ_MASK_PING_MASK)) 1307 #define GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SHIFT 9 1308 #define GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_MASK \ 1309 (0x1 << GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SHIFT) 1310 #define GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_GET(reg_val) \ 1311 (((reg_val)&GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_MASK) >> \ 1312 GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SHIFT) 1313 #define GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SET(reg_val, value) \ 1314 (((reg_val) & ~GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_MASK) | \ 1315 (((value) << GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SHIFT) & \ 1316 GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_MASK)) 1317 #define GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SHIFT 20 1318 #define GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_MASK (0x1 << GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SHIFT) 1319 #define GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_GET(reg_val) \ 1320 (((reg_val)&GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_MASK) >> GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SHIFT) 1321 #define GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SET(reg_val, value) \ 1322 (((reg_val) & ~GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_MASK) | \ 1323 (((value) << GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SHIFT) & GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_MASK)) 1324 #define GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SHIFT 21 1325 #define GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_MASK (0x1 << GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SHIFT) 1326 #define GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_GET(reg_val) \ 1327 (((reg_val)&GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_MASK) >> GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SHIFT) 1328 #define GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SET(reg_val, value) \ 1329 (((reg_val) & ~GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_MASK) | \ 1330 (((value) << GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SHIFT) & GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_MASK)) 1331 #define GLB_ACK_IRQ_MASK_INACTIVE_TILER_SHIFT 22 1332 #define GLB_ACK_IRQ_MASK_INACTIVE_TILER_MASK (0x1 << GLB_ACK_IRQ_MASK_INACTIVE_TILER_SHIFT) 1333 #define GLB_ACK_IRQ_MASK_INACTIVE_TILER_GET(reg_val) \ 1334 (((reg_val)&GLB_ACK_IRQ_MASK_INACTIVE_TILER_MASK) >> GLB_ACK_IRQ_MASK_INACTIVE_TILER_SHIFT) 1335 #define GLB_ACK_IRQ_MASK_INACTIVE_TILER_SET(reg_val, value) \ 1336 (((reg_val) & ~GLB_ACK_IRQ_MASK_INACTIVE_TILER_MASK) | \ 1337 (((value) << GLB_ACK_IRQ_MASK_INACTIVE_TILER_SHIFT) & GLB_ACK_IRQ_MASK_INACTIVE_TILER_MASK)) 1338 #define GLB_ACK_IRQ_MASK_PROTM_EXIT_SHIFT 23 1339 #define GLB_ACK_IRQ_MASK_PROTM_EXIT_MASK (0x1 << GLB_ACK_IRQ_MASK_PROTM_EXIT_SHIFT) 1340 #define GLB_ACK_IRQ_MASK_PROTM_EXIT_GET(reg_val) \ 1341 (((reg_val)&GLB_ACK_IRQ_MASK_PROTM_EXIT_MASK) >> GLB_ACK_IRQ_MASK_PROTM_EXIT_SHIFT) 1342 #define GLB_ACK_IRQ_MASK_PROTM_EXIT_SET(reg_val, value) \ 1343 (((reg_val) & ~GLB_ACK_IRQ_MASK_PROTM_EXIT_MASK) | \ 1344 (((value) << GLB_ACK_IRQ_MASK_PROTM_EXIT_SHIFT) & GLB_ACK_IRQ_MASK_PROTM_EXIT_MASK)) 1345 #define GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SHIFT 24 1346 #define GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_MASK \ 1347 (0x1 << GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SHIFT) 1348 #define GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_GET(reg_val) \ 1349 (((reg_val)&GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_MASK) >> \ 1350 GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SHIFT) 1351 #define GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SET(reg_val, value) \ 1352 (((reg_val) & ~GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_MASK) | \ 1353 (((value) << GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SHIFT) & \ 1354 GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_MASK)) 1355 #define GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SHIFT 25 1356 #define GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_MASK \ 1357 (0x1 << GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SHIFT) 1358 #define GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_GET(reg_val) \ 1359 (((reg_val)&GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_MASK) >> \ 1360 GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SHIFT) 1361 #define GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SET(reg_val, value) \ 1362 (((reg_val) & ~GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_MASK) | \ 1363 (((value) << GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SHIFT) & \ 1364 GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_MASK)) 1365 #define GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SHIFT 30 1366 #define GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_MASK (0x1 << GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SHIFT) 1367 #define GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_GET(reg_val) \ 1368 (((reg_val)&GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_MASK) >> GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SHIFT) 1369 #define GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SET(reg_val, value) \ 1370 (((reg_val) & ~GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_MASK) | \ 1371 (((value) << GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SHIFT) & GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_MASK)) 1372 #define GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SHIFT 31 1373 #define GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_MASK (0x1 << GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SHIFT) 1374 #define GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_GET(reg_val) \ 1375 (((reg_val)&GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_MASK) >> GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SHIFT) 1376 #define GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SET(reg_val, value) \ 1377 (((reg_val) & ~GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_MASK) | \ 1378 (((value) << GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SHIFT) & GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_MASK)) 1379 1380 /* GLB_PROGRESS_TIMER register */ 1381 #define GLB_PROGRESS_TIMER_TIMEOUT_SHIFT 0 1382 #define GLB_PROGRESS_TIMER_TIMEOUT_MASK (0xFFFFFFFF << GLB_PROGRESS_TIMER_TIMEOUT_SHIFT) 1383 #define GLB_PROGRESS_TIMER_TIMEOUT_GET(reg_val) \ 1384 (((reg_val)&GLB_PROGRESS_TIMER_TIMEOUT_MASK) >> GLB_PROGRESS_TIMER_TIMEOUT_SHIFT) 1385 #define GLB_PROGRESS_TIMER_TIMEOUT_SET(reg_val, value) \ 1386 (((reg_val) & ~GLB_PROGRESS_TIMER_TIMEOUT_MASK) | \ 1387 (((value) << GLB_PROGRESS_TIMER_TIMEOUT_SHIFT) & GLB_PROGRESS_TIMER_TIMEOUT_MASK)) 1388 1389 /* GLB_PWROFF_TIMER register */ 1390 #define GLB_PWROFF_TIMER_TIMEOUT_SHIFT 0 1391 #define GLB_PWROFF_TIMER_TIMEOUT_MASK (0x7FFFFFFF << GLB_PWROFF_TIMER_TIMEOUT_SHIFT) 1392 #define GLB_PWROFF_TIMER_TIMEOUT_GET(reg_val) \ 1393 (((reg_val)&GLB_PWROFF_TIMER_TIMEOUT_MASK) >> GLB_PWROFF_TIMER_TIMEOUT_SHIFT) 1394 #define GLB_PWROFF_TIMER_TIMEOUT_SET(reg_val, value) \ 1395 (((reg_val) & ~GLB_PWROFF_TIMER_TIMEOUT_MASK) | \ 1396 (((value) << GLB_PWROFF_TIMER_TIMEOUT_SHIFT) & GLB_PWROFF_TIMER_TIMEOUT_MASK)) 1397 #define GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT 31 1398 #define GLB_PWROFF_TIMER_TIMER_SOURCE_MASK (0x1 << GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT) 1399 #define GLB_PWROFF_TIMER_TIMER_SOURCE_GET(reg_val) \ 1400 (((reg_val)&GLB_PWROFF_TIMER_TIMER_SOURCE_MASK) >> GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT) 1401 #define GLB_PWROFF_TIMER_TIMER_SOURCE_SET(reg_val, value) \ 1402 (((reg_val) & ~GLB_PWROFF_TIMER_TIMER_SOURCE_MASK) | \ 1403 (((value) << GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT) & GLB_PWROFF_TIMER_TIMER_SOURCE_MASK)) 1404 /* GLB_PWROFF_TIMER_TIMER_SOURCE values */ 1405 #define GLB_PWROFF_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP 0x0 1406 #define GLB_PWROFF_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1 1407 /* End of GLB_PWROFF_TIMER_TIMER_SOURCE values */ 1408 1409 /* GLB_ALLOC_EN register */ 1410 #define GLB_ALLOC_EN_MASK_SHIFT 0 1411 #define GLB_ALLOC_EN_MASK_MASK (0xFFFFFFFFFFFFFFFF << GLB_ALLOC_EN_MASK_SHIFT) 1412 #define GLB_ALLOC_EN_MASK_GET(reg_val) (((reg_val)&GLB_ALLOC_EN_MASK_MASK) >> GLB_ALLOC_EN_MASK_SHIFT) 1413 #define GLB_ALLOC_EN_MASK_SET(reg_val, value) \ 1414 (((reg_val) & ~GLB_ALLOC_EN_MASK_MASK) | (((value) << GLB_ALLOC_EN_MASK_SHIFT) & GLB_ALLOC_EN_MASK_MASK)) 1415 1416 /* GLB_OUTPUT_BLOCK register set definitions */ 1417 1418 /* GLB_ACK register */ 1419 #define GLB_ACK_CFG_PROGRESS_TIMER_SHIFT 1 1420 #define GLB_ACK_CFG_PROGRESS_TIMER_MASK (0x1 << GLB_ACK_CFG_PROGRESS_TIMER_SHIFT) 1421 #define GLB_ACK_CFG_PROGRESS_TIMER_GET(reg_val) \ 1422 (((reg_val)&GLB_ACK_CFG_PROGRESS_TIMER_MASK) >> GLB_ACK_CFG_PROGRESS_TIMER_SHIFT) 1423 #define GLB_ACK_CFG_PROGRESS_TIMER_SET(reg_val, value) \ 1424 (((reg_val) & ~GLB_ACK_CFG_PROGRESS_TIMER_MASK) | \ 1425 (((value) << GLB_ACK_CFG_PROGRESS_TIMER_SHIFT) & GLB_ACK_CFG_PROGRESS_TIMER_MASK)) 1426 #define GLB_ACK_CFG_ALLOC_EN_SHIFT 2 1427 #define GLB_ACK_CFG_ALLOC_EN_MASK (0x1 << GLB_ACK_CFG_ALLOC_EN_SHIFT) 1428 #define GLB_ACK_CFG_ALLOC_EN_GET(reg_val) (((reg_val)&GLB_ACK_CFG_ALLOC_EN_MASK) >> GLB_ACK_CFG_ALLOC_EN_SHIFT) 1429 #define GLB_ACK_CFG_ALLOC_EN_SET(reg_val, value) \ 1430 (((reg_val) & ~GLB_ACK_CFG_ALLOC_EN_MASK) | (((value) << GLB_ACK_CFG_ALLOC_EN_SHIFT) & GLB_ACK_CFG_ALLOC_EN_MASK)) 1431 /* End of GLB_OUTPUT_BLOCK register set definitions */ 1432 1433 /* The following register and fields are for headers before 10.x.7/11.x.4 */ 1434 #define GLB_REQ_IDLE_ENABLE_SHIFT (10) 1435 #define GLB_REQ_REQ_IDLE_ENABLE (1 << GLB_REQ_IDLE_ENABLE_SHIFT) 1436 #define GLB_REQ_REQ_IDLE_DISABLE (0 << GLB_REQ_IDLE_ENABLE_SHIFT) 1437 #define GLB_REQ_IDLE_ENABLE_MASK (0x1 << GLB_REQ_IDLE_ENABLE_SHIFT) 1438 #define GLB_REQ_IDLE_DISABLE_MASK (0x1 << GLB_REQ_IDLE_ENABLE_SHIFT) 1439 #define GLB_REQ_IDLE_EVENT_SHIFT (26) 1440 #define GLB_REQ_IDLE_EVENT_MASK (0x1 << GLB_REQ_IDLE_EVENT_SHIFT) 1441 #define GLB_ACK_IDLE_ENABLE_SHIFT (10) 1442 #define GLB_ACK_ACK_IDLE_ENABLE (1 << GLB_ACK_IDLE_ENABLE_SHIFT) 1443 #define GLB_ACK_ACK_IDLE_DISABLE (0 << GLB_ACK_IDLE_ENABLE_SHIFT) 1444 #define GLB_ACK_IDLE_ENABLE_MASK (0x1 << GLB_ACK_IDLE_ENABLE_SHIFT) 1445 #define GLB_ACK_IDLE_EVENT_SHIFT (26) 1446 #define GLB_ACK_IDLE_EVENT_MASK (0x1 << GLB_REQ_IDLE_EVENT_SHIFT) 1447 1448 #define GLB_ACK_IRQ_MASK_IDLE_EVENT_SHIFT (26) 1449 #define GLB_ACK_IRQ_MASK_IDLE_EVENT_MASK (0x1 << GLB_ACK_IRQ_MASK_IDLE_EVENT_SHIFT) 1450 1451 #define GLB_IDLE_TIMER (0x0080) 1452 /* GLB_IDLE_TIMER register */ 1453 #define GLB_IDLE_TIMER_TIMEOUT_SHIFT (0) 1454 #define GLB_IDLE_TIMER_TIMEOUT_MASK ((0x7FFFFFFF) << GLB_IDLE_TIMER_TIMEOUT_SHIFT) 1455 #define GLB_IDLE_TIMER_TIMEOUT_GET(reg_val) (((reg_val)&GLB_IDLE_TIMER_TIMEOUT_MASK) >> GLB_IDLE_TIMER_TIMEOUT_SHIFT) 1456 #define GLB_IDLE_TIMER_TIMEOUT_SET(reg_val, value) \ 1457 (((reg_val) & ~GLB_IDLE_TIMER_TIMEOUT_MASK) | \ 1458 (((value) << GLB_IDLE_TIMER_TIMEOUT_SHIFT) & GLB_IDLE_TIMER_TIMEOUT_MASK)) 1459 #define GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT (31) 1460 #define GLB_IDLE_TIMER_TIMER_SOURCE_MASK ((0x1) << GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT) 1461 #define GLB_IDLE_TIMER_TIMER_SOURCE_GET(reg_val) \ 1462 (((reg_val)&GLB_IDLE_TIMER_TIMER_SOURCE_MASK) >> GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT) 1463 #define GLB_IDLE_TIMER_TIMER_SOURCE_SET(reg_val, value) \ 1464 (((reg_val) & ~GLB_IDLE_TIMER_TIMER_SOURCE_MASK) | \ 1465 (((value) << GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT) & GLB_IDLE_TIMER_TIMER_SOURCE_MASK)) 1466 /* GLB_IDLE_TIMER_TIMER_SOURCE values */ 1467 #define GLB_IDLE_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP 0x0 1468 #define GLB_IDLE_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1 1469 /* End of GLB_IDLE_TIMER_TIMER_SOURCE values */ 1470 1471 /* GLB_INSTR_FEATURES register */ 1472 #define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT (0) 1473 #define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK ((u32)0xF << GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) 1474 #define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_GET(reg_val) \ 1475 (((reg_val)&GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK) >> GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) 1476 #define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SET(reg_val, value) \ 1477 (((reg_val) & ~GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK) | \ 1478 (((value) << GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) & GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK)) 1479 #define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT (4) 1480 #define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK ((u32)0xF << GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) 1481 #define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_GET(reg_val) \ 1482 (((reg_val)&GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK) >> GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) 1483 #define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SET(reg_val, value) \ 1484 (((reg_val) & ~GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK) | \ 1485 (((value) << GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) & GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK)) 1486 1487 #define CSG_STATUS_STATE (0x0018) /* CSG state status register */ 1488 /* CSG_STATUS_STATE register */ 1489 #define CSG_STATUS_STATE_IDLE_SHIFT (0) 1490 #define CSG_STATUS_STATE_IDLE_MASK ((0x1) << CSG_STATUS_STATE_IDLE_SHIFT) 1491 #define CSG_STATUS_STATE_IDLE_GET(reg_val) \ 1492 (((reg_val)&CSG_STATUS_STATE_IDLE_MASK) >> CSG_STATUS_STATE_IDLE_SHIFT) 1493 #define CSG_STATUS_STATE_IDLE_SET(reg_val, value) \ 1494 (((reg_val) & ~CSG_STATUS_STATE_IDLE_MASK) | \ 1495 (((value) << CSG_STATUS_STATE_IDLE_SHIFT) & CSG_STATUS_STATE_IDLE_MASK)) 1496 1497 /* GLB_FEATURES_ITER_TRACE_SUPPORTED register */ 1498 #define GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT GPU_U(4) 1499 #define GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK \ 1500 (GPU_U(0x1) << GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) 1501 #define GLB_FEATURES_ITER_TRACE_SUPPORTED_GET(reg_val) \ 1502 (((reg_val)&GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK) >> \ 1503 GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) 1504 #define GLB_FEATURES_ITER_TRACE_SUPPORTED_SET(reg_val, value) \ 1505 (((reg_val) & ~GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK) | \ 1506 (((value) << GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) & \ 1507 GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK)) 1508 1509 /* GLB_REQ_ITER_TRACE_ENABLE register */ 1510 #define GLB_REQ_ITER_TRACE_ENABLE_SHIFT GPU_U(11) 1511 #define GLB_REQ_ITER_TRACE_ENABLE_MASK \ 1512 (GPU_U(0x1) << GLB_REQ_ITER_TRACE_ENABLE_SHIFT) 1513 #define GLB_REQ_ITER_TRACE_ENABLE_GET(reg_val) \ 1514 (((reg_val)&GLB_REQ_ITER_TRACE_ENABLE_MASK) >> \ 1515 GLB_REQ_ITER_TRACE_ENABLE_SHIFT) 1516 #define GLB_REQ_ITER_TRACE_ENABLE_SET(reg_val, value) \ 1517 (((reg_val) & ~GLB_REQ_ITER_TRACE_ENABLE_MASK) | \ 1518 (((value) << GLB_REQ_ITER_TRACE_ENABLE_SHIFT) & \ 1519 GLB_REQ_ITER_TRACE_ENABLE_MASK)) 1520 1521 #endif /* _UAPI_GPU_CSF_REGISTERS_H_ */ 1522