1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2021 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 #ifndef _UAPI_KBASE_GPU_REGMAP_H_ 23 #define _UAPI_KBASE_GPU_REGMAP_H_ 24 25 #include "mali_kbase_gpu_coherency.h" 26 #include "mali_kbase_gpu_id.h" 27 #if MALI_USE_CSF 28 #include "backend/mali_kbase_gpu_regmap_csf.h" 29 #else 30 #include "backend/mali_kbase_gpu_regmap_jm.h" 31 #endif 32 33 /* GPU_U definition */ 34 #ifdef __ASSEMBLER__ 35 #define GPU_U(x) x 36 #else 37 #define GPU_U(x) x##u 38 #endif /* __ASSEMBLER__ */ 39 40 /* Begin Register Offsets */ 41 /* GPU control registers */ 42 43 #define GPU_CONTROL_BASE 0x0000 44 #define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r)) 45 #define GPU_ID 0x000 /* (RO) GPU and revision identifier */ 46 #define L2_FEATURES 0x004 /* (RO) Level 2 cache features */ 47 #define TILER_FEATURES 0x00C /* (RO) Tiler Features */ 48 #define MEM_FEATURES 0x010 /* (RO) Memory system features */ 49 #define MMU_FEATURES 0x014 /* (RO) MMU features */ 50 #define AS_PRESENT 0x018 /* (RO) Address space slots present */ 51 #define GPU_IRQ_RAWSTAT 0x020 /* (RW) */ 52 #define GPU_IRQ_CLEAR 0x024 /* (WO) */ 53 #define GPU_IRQ_MASK 0x028 /* (RW) */ 54 #define GPU_IRQ_STATUS 0x02C /* (RO) */ 55 56 #define GPU_COMMAND 0x030 /* (WO) */ 57 #define GPU_STATUS 0x034 /* (RO) */ 58 59 #define GPU_DBGEN (1 << 8) /* DBGEN wire status */ 60 61 #define GPU_FAULTSTATUS 0x03C /* (RO) GPU exception type and fault status */ 62 #define GPU_FAULTADDRESS_LO 0x040 /* (RO) GPU exception fault address, low word */ 63 #define GPU_FAULTADDRESS_HI 0x044 /* (RO) GPU exception fault address, high word */ 64 65 #define L2_CONFIG 0x048 /* (RW) Level 2 cache configuration */ 66 67 #define GROUPS_L2_COHERENT (1 << 0) /* Cores groups are l2 coherent */ 68 #define SUPER_L2_COHERENT (1 << 1) /* Shader cores within a core 69 * supergroup are l2 coherent 70 */ 71 72 #define PWR_KEY 0x050 /* (WO) Power manager key register */ 73 #define PWR_OVERRIDE0 0x054 /* (RW) Power manager override settings */ 74 #define PWR_OVERRIDE1 0x058 /* (RW) Power manager override settings */ 75 #define GPU_FEATURES_LO 0x060 /* (RO) GPU features, low word */ 76 #define GPU_FEATURES_HI 0x064 /* (RO) GPU features, high word */ 77 #define PRFCNT_FEATURES 0x068 /* (RO) Performance counter features */ 78 #define TIMESTAMP_OFFSET_LO 0x088 /* (RW) Global time stamp offset, low word */ 79 #define TIMESTAMP_OFFSET_HI 0x08C /* (RW) Global time stamp offset, high word */ 80 #define CYCLE_COUNT_LO 0x090 /* (RO) Cycle counter, low word */ 81 #define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */ 82 #define TIMESTAMP_LO 0x098 /* (RO) Global time stamp counter, low word */ 83 #define TIMESTAMP_HI 0x09C /* (RO) Global time stamp counter, high word */ 84 85 #define THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */ 86 #define THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */ 87 #define THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */ 88 #define THREAD_FEATURES 0x0AC /* (RO) Thread features */ 89 #define THREAD_TLS_ALLOC 0x310 /* (RO) Number of threads per core that TLS must be allocated for */ 90 91 #define TEXTURE_FEATURES_0 0x0B0 /* (RO) Support flags for indexed texture formats 0..31 */ 92 #define TEXTURE_FEATURES_1 0x0B4 /* (RO) Support flags for indexed texture formats 32..63 */ 93 #define TEXTURE_FEATURES_2 0x0B8 /* (RO) Support flags for indexed texture formats 64..95 */ 94 #define TEXTURE_FEATURES_3 0x0BC /* (RO) Support flags for texture order */ 95 96 #define TEXTURE_FEATURES_REG(n) GPU_CONTROL_REG(TEXTURE_FEATURES_0 + ((n) << 2)) 97 98 #define SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */ 99 #define SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */ 100 101 #define TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */ 102 #define TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */ 103 104 #define L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */ 105 #define L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */ 106 107 #define STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */ 108 #define STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */ 109 110 #define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */ 111 #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */ 112 113 #define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */ 114 #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */ 115 116 #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */ 117 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */ 118 119 #define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */ 120 #define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */ 121 122 #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */ 123 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */ 124 125 #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */ 126 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */ 127 128 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */ 129 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */ 130 131 #define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */ 132 #define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */ 133 134 #define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */ 135 #define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */ 136 137 #define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */ 138 #define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */ 139 140 #define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */ 141 #define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */ 142 143 #define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */ 144 #define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */ 145 146 #define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */ 147 #define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */ 148 149 #define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */ 150 #define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */ 151 152 #define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */ 153 #define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */ 154 155 #define ASN_HASH_0 0x02C0 /* (RW) ASN hash function argument 0 */ 156 #define ASN_HASH(n) (ASN_HASH_0 + (n)*4) 157 #define ASN_HASH_COUNT 3 158 159 #define SYSC_ALLOC0 0x0340 /* (RW) System cache allocation hint from source ID */ 160 #define SYSC_ALLOC(n) (SYSC_ALLOC0 + (n)*4) 161 #define SYSC_ALLOC_COUNT 8 162 163 #define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */ 164 #define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */ 165 166 #define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */ 167 #define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */ 168 169 #define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */ 170 #define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */ 171 172 #define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */ 173 #define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */ 174 175 #define COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */ 176 #define COHERENCY_ENABLE 0x304 /* (RW) Coherency enable */ 177 178 179 #define SHADER_CONFIG 0xF04 /* (RW) Shader core configuration (implementation-specific) */ 180 #define TILER_CONFIG 0xF08 /* (RW) Tiler core configuration (implementation-specific) */ 181 #define L2_MMU_CONFIG 0xF0C /* (RW) L2 cache and MMU configuration (implementation-specific) */ 182 183 /* Job control registers */ 184 185 #define JOB_CONTROL_BASE 0x1000 186 187 #define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r)) 188 189 #define JOB_IRQ_RAWSTAT 0x000 /* Raw interrupt status register */ 190 #define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */ 191 #define JOB_IRQ_MASK 0x008 /* Interrupt mask register */ 192 #define JOB_IRQ_STATUS 0x00C /* Interrupt status register */ 193 194 /* MMU control registers */ 195 196 #define MEMORY_MANAGEMENT_BASE 0x2000 197 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) 198 199 #define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */ 200 #define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */ 201 #define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */ 202 #define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */ 203 204 #define MMU_AS0 0x400 /* Configuration registers for address space 0 */ 205 #define MMU_AS1 0x440 /* Configuration registers for address space 1 */ 206 #define MMU_AS2 0x480 /* Configuration registers for address space 2 */ 207 #define MMU_AS3 0x4C0 /* Configuration registers for address space 3 */ 208 #define MMU_AS4 0x500 /* Configuration registers for address space 4 */ 209 #define MMU_AS5 0x540 /* Configuration registers for address space 5 */ 210 #define MMU_AS6 0x580 /* Configuration registers for address space 6 */ 211 #define MMU_AS7 0x5C0 /* Configuration registers for address space 7 */ 212 #define MMU_AS8 0x600 /* Configuration registers for address space 8 */ 213 #define MMU_AS9 0x640 /* Configuration registers for address space 9 */ 214 #define MMU_AS10 0x680 /* Configuration registers for address space 10 */ 215 #define MMU_AS11 0x6C0 /* Configuration registers for address space 11 */ 216 #define MMU_AS12 0x700 /* Configuration registers for address space 12 */ 217 #define MMU_AS13 0x740 /* Configuration registers for address space 13 */ 218 #define MMU_AS14 0x780 /* Configuration registers for address space 14 */ 219 #define MMU_AS15 0x7C0 /* Configuration registers for address space 15 */ 220 221 /* MMU address space control registers */ 222 223 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r)) 224 225 #define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */ 226 #define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */ 227 #define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */ 228 #define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */ 229 #define AS_LOCKADDR_LO 0x10 /* (RW) Lock region address for address space n, low word */ 230 #define AS_LOCKADDR_HI 0x14 /* (RW) Lock region address for address space n, high word */ 231 #define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */ 232 #define AS_FAULTSTATUS 0x1C /* (RO) MMU fault status register for address space n */ 233 #define AS_FAULTADDRESS_LO 0x20 /* (RO) Fault Address for address space n, low word */ 234 #define AS_FAULTADDRESS_HI 0x24 /* (RO) Fault Address for address space n, high word */ 235 #define AS_STATUS 0x28 /* (RO) Status flags for address space n */ 236 237 /* (RW) Translation table configuration for address space n, low word */ 238 #define AS_TRANSCFG_LO 0x30 239 /* (RW) Translation table configuration for address space n, high word */ 240 #define AS_TRANSCFG_HI 0x34 241 /* (RO) Secondary fault address for address space n, low word */ 242 #define AS_FAULTEXTRA_LO 0x38 243 /* (RO) Secondary fault address for address space n, high word */ 244 #define AS_FAULTEXTRA_HI 0x3C 245 246 /* End Register Offsets */ 247 248 #define GPU_IRQ_REG_ALL (GPU_IRQ_REG_COMMON) 249 250 /* 251 * MMU_IRQ_RAWSTAT register values. Values are valid also for 252 * MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers. 253 */ 254 255 #define MMU_PAGE_FAULT_FLAGS 16 256 257 /* Macros returning a bitmask to retrieve page fault or bus error flags from 258 * MMU registers 259 */ 260 #define MMU_PAGE_FAULT(n) (1UL << (n)) 261 #define MMU_BUS_ERROR(n) (1UL << ((n) + MMU_PAGE_FAULT_FLAGS)) 262 263 /* 264 * Begin AARCH64 MMU TRANSTAB register values 265 */ 266 #define MMU_HW_OUTA_BITS 40 267 #define AS_TRANSTAB_BASE_MASK ((1ULL << MMU_HW_OUTA_BITS) - (1ULL << 4)) 268 269 /* 270 * Begin MMU STATUS register values 271 */ 272 #define AS_STATUS_AS_ACTIVE 0x01 273 274 #define AS_FAULTSTATUS_EXCEPTION_CODE_MASK (0x7<<3) 275 #define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSLATION_FAULT (0x0<<3) 276 #define AS_FAULTSTATUS_EXCEPTION_CODE_PERMISSION_FAULT (0x1<<3) 277 #define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSTAB_BUS_FAULT (0x2<<3) 278 #define AS_FAULTSTATUS_EXCEPTION_CODE_ACCESS_FLAG (0x3<<3) 279 #define AS_FAULTSTATUS_EXCEPTION_CODE_ADDRESS_SIZE_FAULT (0x4<<3) 280 #define AS_FAULTSTATUS_EXCEPTION_CODE_MEMORY_ATTRIBUTES_FAULT (0x5<<3) 281 282 #define AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT 0 283 #define AS_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFF << AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT) 284 #define AS_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \ 285 (((reg_val)&AS_FAULTSTATUS_EXCEPTION_TYPE_MASK) >> AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT) 286 #define AS_FAULTSTATUS_EXCEPTION_TYPE_TRANSLATION_FAULT_0 0xC0 287 288 #define AS_FAULTSTATUS_ACCESS_TYPE_SHIFT 8 289 #define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << AS_FAULTSTATUS_ACCESS_TYPE_SHIFT) 290 #define AS_FAULTSTATUS_ACCESS_TYPE_GET(reg_val) \ 291 (((reg_val)&AS_FAULTSTATUS_ACCESS_TYPE_MASK) >> AS_FAULTSTATUS_ACCESS_TYPE_SHIFT) 292 293 #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0) 294 #define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1) 295 #define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2) 296 #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3) 297 298 #define AS_FAULTSTATUS_SOURCE_ID_SHIFT 16 299 #define AS_FAULTSTATUS_SOURCE_ID_MASK (0xFFFF << AS_FAULTSTATUS_SOURCE_ID_SHIFT) 300 #define AS_FAULTSTATUS_SOURCE_ID_GET(reg_val) \ 301 (((reg_val)&AS_FAULTSTATUS_SOURCE_ID_MASK) >> AS_FAULTSTATUS_SOURCE_ID_SHIFT) 302 303 #define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT (0) 304 #define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK \ 305 ((0xFF) << PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT) 306 #define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val) \ 307 (((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >> \ 308 PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT) 309 310 /* 311 * Begin MMU TRANSCFG register values 312 */ 313 #define AS_TRANSCFG_ADRMODE_LEGACY 0 314 #define AS_TRANSCFG_ADRMODE_UNMAPPED 1 315 #define AS_TRANSCFG_ADRMODE_IDENTITY 2 316 #define AS_TRANSCFG_ADRMODE_AARCH64_4K 6 317 #define AS_TRANSCFG_ADRMODE_AARCH64_64K 8 318 319 #define AS_TRANSCFG_ADRMODE_MASK 0xF 320 321 /* 322 * Begin TRANSCFG register values 323 */ 324 #define AS_TRANSCFG_PTW_MEMATTR_MASK (3ull << 24) 325 #define AS_TRANSCFG_PTW_MEMATTR_NON_CACHEABLE (1ull << 24) 326 #define AS_TRANSCFG_PTW_MEMATTR_WRITE_BACK (2ull << 24) 327 328 #define AS_TRANSCFG_PTW_SH_MASK ((3ull << 28)) 329 #define AS_TRANSCFG_PTW_SH_OS (2ull << 28) 330 #define AS_TRANSCFG_PTW_SH_IS (3ull << 28) 331 #define AS_TRANSCFG_R_ALLOCATE (1ull << 30) 332 333 /* 334 * Begin Command Values 335 */ 336 337 /* AS_COMMAND register commands */ 338 #define AS_COMMAND_NOP 0x00 /* NOP Operation */ 339 #define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */ 340 #define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */ 341 #define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */ 342 /* Flush all L2 caches then issue a flush region command to all MMUs */ 343 #define AS_COMMAND_FLUSH_PT 0x04 344 /* Wait for memory accesses to complete, flush all the L1s cache then flush all 345 * L2 caches then issue a flush region command to all MMUs 346 */ 347 #define AS_COMMAND_FLUSH_MEM 0x05 348 349 /* AS_LOCKADDR register */ 350 #define AS_LOCKADDR_LOCKADDR_SIZE_SHIFT GPU_U(0) 351 #define AS_LOCKADDR_LOCKADDR_SIZE_MASK \ 352 (GPU_U(0x3F) << AS_LOCKADDR_LOCKADDR_SIZE_SHIFT) 353 #define AS_LOCKADDR_LOCKADDR_SIZE_GET(reg_val) \ 354 (((reg_val)&AS_LOCKADDR_LOCKADDR_SIZE_MASK) >> \ 355 AS_LOCKADDR_LOCKADDR_SIZE_SHIFT) 356 #define AS_LOCKADDR_LOCKADDR_SIZE_SET(reg_val, value) \ 357 (((reg_val) & ~AS_LOCKADDR_LOCKADDR_SIZE_MASK) | \ 358 (((value) << AS_LOCKADDR_LOCKADDR_SIZE_SHIFT) & \ 359 AS_LOCKADDR_LOCKADDR_SIZE_MASK)) 360 #define AS_LOCKADDR_LOCKADDR_BASE_SHIFT GPU_U(12) 361 #define AS_LOCKADDR_LOCKADDR_BASE_MASK \ 362 (GPU_U(0xFFFFFFFFFFFFF) << AS_LOCKADDR_LOCKADDR_BASE_SHIFT) 363 #define AS_LOCKADDR_LOCKADDR_BASE_GET(reg_val) \ 364 (((reg_val)&AS_LOCKADDR_LOCKADDR_BASE_MASK) >> \ 365 AS_LOCKADDR_LOCKADDR_BASE_SHIFT) 366 #define AS_LOCKADDR_LOCKADDR_BASE_SET(reg_val, value) \ 367 (((reg_val) & ~AS_LOCKADDR_LOCKADDR_BASE_MASK) | \ 368 (((value) << AS_LOCKADDR_LOCKADDR_BASE_SHIFT) & \ 369 AS_LOCKADDR_LOCKADDR_BASE_MASK)) 370 371 /* GPU_STATUS values */ 372 #define GPU_STATUS_PRFCNT_ACTIVE (1 << 2) /* Set if the performance counters are active. */ 373 #define GPU_STATUS_CYCLE_COUNT_ACTIVE (1 << 6) /* Set if the cycle counter is active. */ 374 #define GPU_STATUS_PROTECTED_MODE_ACTIVE (1 << 7) /* Set if protected mode is active */ 375 376 /* PRFCNT_CONFIG register values */ 377 #define PRFCNT_CONFIG_MODE_SHIFT 0 /* Counter mode position. */ 378 #define PRFCNT_CONFIG_AS_SHIFT 4 /* Address space bitmap position. */ 379 #define PRFCNT_CONFIG_SETSELECT_SHIFT 8 /* Set select position. */ 380 381 /* The performance counters are disabled. */ 382 #define PRFCNT_CONFIG_MODE_OFF 0 383 /* The performance counters are enabled, but are only written out when a 384 * PRFCNT_SAMPLE command is issued using the GPU_COMMAND register. 385 */ 386 #define PRFCNT_CONFIG_MODE_MANUAL 1 387 /* The performance counters are enabled, and are written out each time a tile 388 * finishes rendering. 389 */ 390 #define PRFCNT_CONFIG_MODE_TILE 2 391 392 /* AS<n>_MEMATTR values from MMU_MEMATTR_STAGE1: */ 393 /* Use GPU implementation-defined caching policy. */ 394 #define AS_MEMATTR_IMPL_DEF_CACHE_POLICY 0x88ull 395 /* The attribute set to force all resources to be cached. */ 396 #define AS_MEMATTR_FORCE_TO_CACHE_ALL 0x8Full 397 /* Inner write-alloc cache setup, no outer caching */ 398 #define AS_MEMATTR_WRITE_ALLOC 0x8Dull 399 400 /* Use GPU implementation-defined caching policy. */ 401 #define AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY 0x48ull 402 /* The attribute set to force all resources to be cached. */ 403 #define AS_MEMATTR_LPAE_FORCE_TO_CACHE_ALL 0x4Full 404 /* Inner write-alloc cache setup, no outer caching */ 405 #define AS_MEMATTR_LPAE_WRITE_ALLOC 0x4Dull 406 /* Set to implementation defined, outer caching */ 407 #define AS_MEMATTR_LPAE_OUTER_IMPL_DEF 0x88ull 408 /* Set to write back memory, outer caching */ 409 #define AS_MEMATTR_LPAE_OUTER_WA 0x8Dull 410 /* There is no LPAE support for non-cacheable, since the memory type is always 411 * write-back. 412 * Marking this setting as reserved for LPAE 413 */ 414 #define AS_MEMATTR_LPAE_NON_CACHEABLE_RESERVED 415 416 /* L2_MMU_CONFIG register */ 417 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT (23) 418 #define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT) 419 420 /* End L2_MMU_CONFIG register */ 421 422 /* THREAD_* registers */ 423 424 /* THREAD_FEATURES IMPLEMENTATION_TECHNOLOGY values */ 425 #define IMPLEMENTATION_UNSPECIFIED 0 426 #define IMPLEMENTATION_SILICON 1 427 #define IMPLEMENTATION_FPGA 2 428 #define IMPLEMENTATION_MODEL 3 429 430 /* Default values when registers are not supported by the implemented hardware */ 431 #define THREAD_MT_DEFAULT 256 432 #define THREAD_MWS_DEFAULT 256 433 #define THREAD_MBS_DEFAULT 256 434 #define THREAD_MR_DEFAULT 1024 435 #define THREAD_MTQ_DEFAULT 4 436 #define THREAD_MTGS_DEFAULT 10 437 438 /* End THREAD_* registers */ 439 440 /* SHADER_CONFIG register */ 441 #define SC_LS_ALLOW_ATTR_TYPES (1ul << 16) 442 #define SC_TLS_HASH_ENABLE (1ul << 17) 443 #define SC_LS_ATTR_CHECK_DISABLE (1ul << 18) 444 #define SC_VAR_ALGORITHM (1ul << 29) 445 /* End SHADER_CONFIG register */ 446 447 /* TILER_CONFIG register */ 448 #define TC_CLOCK_GATE_OVERRIDE (1ul << 0) 449 /* End TILER_CONFIG register */ 450 451 /* L2_CONFIG register */ 452 #define L2_CONFIG_SIZE_SHIFT 16 453 #define L2_CONFIG_SIZE_MASK (0xFFul << L2_CONFIG_SIZE_SHIFT) 454 #define L2_CONFIG_HASH_SHIFT 24 455 #define L2_CONFIG_HASH_MASK (0xFFul << L2_CONFIG_HASH_SHIFT) 456 #define L2_CONFIG_ASN_HASH_ENABLE_SHIFT 24 457 #define L2_CONFIG_ASN_HASH_ENABLE_MASK (1ul << L2_CONFIG_ASN_HASH_ENABLE_SHIFT) 458 /* End L2_CONFIG register */ 459 460 461 /* IDVS_GROUP register */ 462 #define IDVS_GROUP_SIZE_SHIFT (16) 463 #define IDVS_GROUP_MAX_SIZE (0x3F) 464 465 /* SYSC_ALLOC read IDs */ 466 #define SYSC_ALLOC_ID_R_OTHER 0x00 467 #define SYSC_ALLOC_ID_R_CSF 0x02 468 #define SYSC_ALLOC_ID_R_MMU 0x04 469 #define SYSC_ALLOC_ID_R_TILER_VERT 0x08 470 #define SYSC_ALLOC_ID_R_TILER_PTR 0x09 471 #define SYSC_ALLOC_ID_R_TILER_INDEX 0x0A 472 #define SYSC_ALLOC_ID_R_TILER_OTHER 0x0B 473 #define SYSC_ALLOC_ID_R_IC 0x10 474 #define SYSC_ALLOC_ID_R_ATTR 0x11 475 #define SYSC_ALLOC_ID_R_SCM 0x12 476 #define SYSC_ALLOC_ID_R_FSDC 0x13 477 #define SYSC_ALLOC_ID_R_VL 0x14 478 #define SYSC_ALLOC_ID_R_PLR 0x15 479 #define SYSC_ALLOC_ID_R_TEX 0x18 480 #define SYSC_ALLOC_ID_R_LSC 0x1c 481 482 /* SYSC_ALLOC write IDs */ 483 #define SYSC_ALLOC_ID_W_OTHER 0x00 484 #define SYSC_ALLOC_ID_W_CSF 0x02 485 #define SYSC_ALLOC_ID_W_PCB 0x07 486 #define SYSC_ALLOC_ID_W_TILER_PTR 0x09 487 #define SYSC_ALLOC_ID_W_TILER_VERT_PLIST 0x0A 488 #define SYSC_ALLOC_ID_W_TILER_OTHER 0x0B 489 #define SYSC_ALLOC_ID_W_L2_EVICT 0x0C 490 #define SYSC_ALLOC_ID_W_L2_FLUSH 0x0D 491 #define SYSC_ALLOC_ID_W_TIB_COLOR 0x10 492 #define SYSC_ALLOC_ID_W_TIB_COLOR_AFBCH 0x11 493 #define SYSC_ALLOC_ID_W_TIB_COLOR_AFBCB 0x12 494 #define SYSC_ALLOC_ID_W_TIB_CRC 0x13 495 #define SYSC_ALLOC_ID_W_TIB_DS 0x14 496 #define SYSC_ALLOC_ID_W_TIB_DS_AFBCH 0x15 497 #define SYSC_ALLOC_ID_W_TIB_DS_AFBCB 0x16 498 #define SYSC_ALLOC_ID_W_LSC 0x1C 499 500 /* SYSC_ALLOC values */ 501 #define SYSC_ALLOC_L2_ALLOC 0x0 502 #define SYSC_ALLOC_NEVER_ALLOC 0x2 503 #define SYSC_ALLOC_ALWAYS_ALLOC 0x3 504 #define SYSC_ALLOC_PTL_ALLOC 0x4 505 #define SYSC_ALLOC_L2_PTL_ALLOC 0x5 506 507 /* SYSC_ALLOC register */ 508 #define SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT (0) 509 #define SYSC_ALLOC_R_SYSC_ALLOC0_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT) 510 #define SYSC_ALLOC_R_SYSC_ALLOC0_GET(reg_val) \ 511 (((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC0_MASK) >> \ 512 SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT) 513 #define SYSC_ALLOC_R_SYSC_ALLOC0_SET(reg_val, value) \ 514 (((reg_val) & ~SYSC_ALLOC_R_SYSC_ALLOC0_MASK) | \ 515 (((value) << SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT) & \ 516 SYSC_ALLOC_R_SYSC_ALLOC0_MASK)) 517 /* End of SYSC_ALLOC_R_SYSC_ALLOC0 values */ 518 #define SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT (4) 519 #define SYSC_ALLOC_W_SYSC_ALLOC0_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT) 520 #define SYSC_ALLOC_W_SYSC_ALLOC0_GET(reg_val) \ 521 (((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC0_MASK) >> \ 522 SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT) 523 #define SYSC_ALLOC_W_SYSC_ALLOC0_SET(reg_val, value) \ 524 (((reg_val) & ~SYSC_ALLOC_W_SYSC_ALLOC0_MASK) | \ 525 (((value) << SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT) & \ 526 SYSC_ALLOC_W_SYSC_ALLOC0_MASK)) 527 /* End of SYSC_ALLOC_W_SYSC_ALLOC0 values */ 528 #define SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT (8) 529 #define SYSC_ALLOC_R_SYSC_ALLOC1_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT) 530 #define SYSC_ALLOC_R_SYSC_ALLOC1_GET(reg_val) \ 531 (((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC1_MASK) >> \ 532 SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT) 533 #define SYSC_ALLOC_R_SYSC_ALLOC1_SET(reg_val, value) \ 534 (((reg_val) & ~SYSC_ALLOC_R_SYSC_ALLOC1_MASK) | \ 535 (((value) << SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT) & \ 536 SYSC_ALLOC_R_SYSC_ALLOC1_MASK)) 537 /* End of SYSC_ALLOC_R_SYSC_ALLOC1 values */ 538 #define SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT (12) 539 #define SYSC_ALLOC_W_SYSC_ALLOC1_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT) 540 #define SYSC_ALLOC_W_SYSC_ALLOC1_GET(reg_val) \ 541 (((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC1_MASK) >> \ 542 SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT) 543 #define SYSC_ALLOC_W_SYSC_ALLOC1_SET(reg_val, value) \ 544 (((reg_val) & ~SYSC_ALLOC_W_SYSC_ALLOC1_MASK) | \ 545 (((value) << SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT) & \ 546 SYSC_ALLOC_W_SYSC_ALLOC1_MASK)) 547 /* End of SYSC_ALLOC_W_SYSC_ALLOC1 values */ 548 #define SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT (16) 549 #define SYSC_ALLOC_R_SYSC_ALLOC2_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT) 550 #define SYSC_ALLOC_R_SYSC_ALLOC2_GET(reg_val) \ 551 (((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC2_MASK) >> \ 552 SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT) 553 #define SYSC_ALLOC_R_SYSC_ALLOC2_SET(reg_val, value) \ 554 (((reg_val) & ~SYSC_ALLOC_R_SYSC_ALLOC2_MASK) | \ 555 (((value) << SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT) & \ 556 SYSC_ALLOC_R_SYSC_ALLOC2_MASK)) 557 /* End of SYSC_ALLOC_R_SYSC_ALLOC2 values */ 558 #define SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT (20) 559 #define SYSC_ALLOC_W_SYSC_ALLOC2_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT) 560 #define SYSC_ALLOC_W_SYSC_ALLOC2_GET(reg_val) \ 561 (((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC2_MASK) >> \ 562 SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT) 563 #define SYSC_ALLOC_W_SYSC_ALLOC2_SET(reg_val, value) \ 564 (((reg_val) & ~SYSC_ALLOC_W_SYSC_ALLOC2_MASK) | \ 565 (((value) << SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT) & \ 566 SYSC_ALLOC_W_SYSC_ALLOC2_MASK)) 567 /* End of SYSC_ALLOC_W_SYSC_ALLOC2 values */ 568 #define SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT (24) 569 #define SYSC_ALLOC_R_SYSC_ALLOC3_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT) 570 #define SYSC_ALLOC_R_SYSC_ALLOC3_GET(reg_val) \ 571 (((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC3_MASK) >> \ 572 SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT) 573 #define SYSC_ALLOC_R_SYSC_ALLOC3_SET(reg_val, value) \ 574 (((reg_val) & ~SYSC_ALLOC_R_SYSC_ALLOC3_MASK) | \ 575 (((value) << SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT) & \ 576 SYSC_ALLOC_R_SYSC_ALLOC3_MASK)) 577 /* End of SYSC_ALLOC_R_SYSC_ALLOC3 values */ 578 #define SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT (28) 579 #define SYSC_ALLOC_W_SYSC_ALLOC3_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT) 580 #define SYSC_ALLOC_W_SYSC_ALLOC3_GET(reg_val) \ 581 (((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC3_MASK) >> \ 582 SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT) 583 #define SYSC_ALLOC_W_SYSC_ALLOC3_SET(reg_val, value) \ 584 (((reg_val) & ~SYSC_ALLOC_W_SYSC_ALLOC3_MASK) | \ 585 (((value) << SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT) & \ 586 SYSC_ALLOC_W_SYSC_ALLOC3_MASK)) 587 /* End of SYSC_ALLOC_W_SYSC_ALLOC3 values */ 588 589 #endif /* _UAPI_KBASE_GPU_REGMAP_H_ */ 590