1 /*
2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/mfd/rk808.h>
21 #include "rk817_codec.h"
22 #include "audio_driver_log.h"
23
24 #define HDF_LOG_TAG "rk809_codec_linux_driver"
25
26 struct platform_device *rk817_pdev;
GetCodecPlatformDevice(void)27 struct platform_device *GetCodecPlatformDevice(void)
28 {
29 return rk817_pdev;
30 }
31
32 static const struct of_device_id rk817_codec_dt_ids[] = {
33 { .compatible = "rockchip,rk817-codec" },
34 };
35 MODULE_DEVICE_TABLE(of, rk817_codec_dt_ids);
36
rk817_platform_probe(struct platform_device * pdev)37 static int rk817_platform_probe(struct platform_device *pdev)
38 {
39 int ret;
40 struct clk *clk;
41
42 rk817_pdev = pdev;
43
44 clk = devm_clk_get(&pdev->dev, "mclk");
45 if (!IS_ERR(clk)) {
46 ret = clk_prepare_enable(clk);
47 if (ret) {
48 dev_err(&pdev->dev, "enable rk817-codec mclk fail!");
49 return ret;
50 }
51 }
52
53 dev_info(&pdev->dev, "got rk817-codec platform_device");
54 return 0;
55 }
56
rk817_platform_remove(struct platform_device * pdev)57 static int rk817_platform_remove(struct platform_device *pdev)
58 {
59 panic("%s not support now", __func__);
60 }
61
62 static struct platform_driver rk817_codec_driver = {
63 .driver = {
64 .name = "rk817-codec",
65 .of_match_table = rk817_codec_dt_ids,
66 },
67 .probe = rk817_platform_probe,
68 .remove = rk817_platform_remove,
69 };
70
71 module_platform_driver(rk817_codec_driver);
72
73 static const struct reg_default rk817_reg_defaults[] = {
74 { RK817_CODEC_DTOP_VUCTL, 0x003 },
75 { RK817_CODEC_DTOP_VUCTIME, 0x00 },
76 { RK817_CODEC_DTOP_LPT_SRST, 0x00 },
77 { RK817_CODEC_DTOP_DIGEN_CLKE, 0x00 },
78 { RK817_CODEC_AREF_RTCFG0, 0x00 },
79 { RK817_CODEC_AREF_RTCFG1, 0x06 },
80 { RK817_CODEC_AADC_CFG0, 0xc8 },
81 { RK817_CODEC_AADC_CFG1, 0x00 },
82 { RK817_CODEC_DADC_SR_ACL0, 0x00 },
83 { RK817_CODEC_DADC_ALC1, 0x00 },
84 { RK817_CODEC_DADC_ALC2, 0x00 },
85 { RK817_CODEC_DADC_NG, 0x00 },
86 { RK817_CODEC_DADC_HPF, 0x00 },
87 { RK817_CODEC_DADC_RVOLL, 0xff },
88 { RK817_CODEC_DADC_RVOLR, 0xff },
89 { RK817_CODEC_AMIC_CFG0, 0x70 },
90 { RK817_CODEC_AMIC_CFG1, 0x00 },
91 { RK817_CODEC_DMIC_PGA_GAIN, 0x6F },
92 { RK817_CODEC_DMIC_LMT1, 0x00 },
93 { RK817_CODEC_DMIC_LMT2, 0x00 },
94 { RK817_CODEC_DMIC_NG1, 0x00 },
95 { RK817_CODEC_DMIC_NG2, 0x00 },
96 { RK817_CODEC_ADAC_CFG0, 0x00 },
97 { RK817_CODEC_ADAC_CFG1, 0x07 },
98 { RK817_CODEC_DDAC_POPD_DACST, 0x82 },
99 { RK817_CODEC_DDAC_VOLL, 0x00 },
100 { RK817_CODEC_DDAC_VOLR, 0x00 },
101 { RK817_CODEC_DDAC_SR_LMT0, 0x00 },
102 { RK817_CODEC_DDAC_LMT1, 0x00 },
103 { RK817_CODEC_DDAC_LMT2, 0x00 },
104 { RK817_CODEC_DDAC_MUTE_MIXCTL, 0xa0 },
105 { RK817_CODEC_DDAC_RVOLL, 0xff },
106 { RK817_CODEC_DDAC_RVOLR, 0xff },
107 { RK817_CODEC_AHP_ANTI0, 0x00 },
108 { RK817_CODEC_AHP_ANTI1, 0x00 },
109 { RK817_CODEC_AHP_CFG0, 0xe0 },
110 { RK817_CODEC_AHP_CFG1, 0x1f },
111 { RK817_CODEC_AHP_CP, 0x09 },
112 { RK817_CODEC_ACLASSD_CFG1, 0x69 },
113 { RK817_CODEC_ACLASSD_CFG2, 0x44 },
114 { RK817_CODEC_APLL_CFG0, 0x04 },
115 { RK817_CODEC_APLL_CFG1, 0x00 },
116 { RK817_CODEC_APLL_CFG2, 0x30 },
117 { RK817_CODEC_APLL_CFG3, 0x19 },
118 { RK817_CODEC_APLL_CFG4, 0x65 },
119 { RK817_CODEC_APLL_CFG5, 0x01 },
120 { RK817_CODEC_DI2S_CKM, 0x01 },
121 { RK817_CODEC_DI2S_RSD, 0x00 },
122 { RK817_CODEC_DI2S_RXCR1, 0x00 },
123 { RK817_CODEC_DI2S_RXCR2, 0x17 },
124 { RK817_CODEC_DI2S_RXCMD_TSD, 0x00 },
125 { RK817_CODEC_DI2S_TXCR1, 0x00 },
126 { RK817_CODEC_DI2S_TXCR2, 0x17 },
127 { RK817_CODEC_DI2S_TXCR3_TXCMD, 0x00 },
128 };
129
rk817_volatile_register(struct device * dev,unsigned int reg)130 static bool rk817_volatile_register(struct device *dev, unsigned int reg)
131 {
132 switch (reg) {
133 case RK817_CODEC_DTOP_LPT_SRST:
134 return true;
135 default:
136 return false;
137 }
138 }
139
rk817_codec_register(struct device * dev,unsigned int reg)140 static bool rk817_codec_register(struct device *dev, unsigned int reg)
141 {
142 switch (reg) {
143 case RK817_CODEC_DTOP_VUCTL:
144 case RK817_CODEC_DTOP_VUCTIME:
145 case RK817_CODEC_DTOP_LPT_SRST:
146 case RK817_CODEC_DTOP_DIGEN_CLKE:
147 case RK817_CODEC_AREF_RTCFG0:
148 case RK817_CODEC_AREF_RTCFG1:
149 case RK817_CODEC_AADC_CFG0:
150 case RK817_CODEC_AADC_CFG1:
151 case RK817_CODEC_DADC_VOLL:
152 case RK817_CODEC_DADC_VOLR:
153 case RK817_CODEC_DADC_SR_ACL0:
154 case RK817_CODEC_DADC_ALC1:
155 case RK817_CODEC_DADC_ALC2:
156 case RK817_CODEC_DADC_NG:
157 case RK817_CODEC_DADC_HPF:
158 case RK817_CODEC_DADC_RVOLL:
159 case RK817_CODEC_DADC_RVOLR:
160 case RK817_CODEC_AMIC_CFG0:
161 case RK817_CODEC_AMIC_CFG1:
162 case RK817_CODEC_DMIC_PGA_GAIN:
163 case RK817_CODEC_DMIC_LMT1:
164 case RK817_CODEC_DMIC_LMT2:
165 case RK817_CODEC_DMIC_NG1:
166 case RK817_CODEC_DMIC_NG2:
167 case RK817_CODEC_ADAC_CFG0:
168 case RK817_CODEC_ADAC_CFG1:
169 case RK817_CODEC_DDAC_POPD_DACST:
170 case RK817_CODEC_DDAC_VOLL:
171 case RK817_CODEC_DDAC_VOLR:
172 case RK817_CODEC_DDAC_SR_LMT0:
173 case RK817_CODEC_DDAC_LMT1:
174 case RK817_CODEC_DDAC_LMT2:
175 case RK817_CODEC_DDAC_MUTE_MIXCTL:
176 case RK817_CODEC_DDAC_RVOLL:
177 case RK817_CODEC_DDAC_RVOLR:
178 case RK817_CODEC_AHP_ANTI0:
179 case RK817_CODEC_AHP_ANTI1:
180 case RK817_CODEC_AHP_CFG0:
181 case RK817_CODEC_AHP_CFG1:
182 case RK817_CODEC_AHP_CP:
183 case RK817_CODEC_ACLASSD_CFG1:
184 case RK817_CODEC_ACLASSD_CFG2:
185 case RK817_CODEC_APLL_CFG0:
186 case RK817_CODEC_APLL_CFG1:
187 case RK817_CODEC_APLL_CFG2:
188 case RK817_CODEC_APLL_CFG3:
189 case RK817_CODEC_APLL_CFG4:
190 case RK817_CODEC_APLL_CFG5:
191 case RK817_CODEC_DI2S_CKM:
192 case RK817_CODEC_DI2S_RSD:
193 case RK817_CODEC_DI2S_RXCR1:
194 case RK817_CODEC_DI2S_RXCR2:
195 case RK817_CODEC_DI2S_RXCMD_TSD:
196 case RK817_CODEC_DI2S_TXCR1:
197 case RK817_CODEC_DI2S_TXCR2:
198 case RK817_CODEC_DI2S_TXCR3_TXCMD:
199 return true;
200 default:
201 return false;
202 }
203 }
204
205 static const struct regmap_config rk817_codec_regmap_config = {
206 .name = "rk817-codec",
207 .reg_bits = 8,
208 .val_bits = 8,
209 .reg_stride = 1,
210 .max_register = 0x4f,
211 .cache_type = REGCACHE_FLAT,
212 .volatile_reg = rk817_volatile_register,
213 .writeable_reg = rk817_codec_register,
214 .readable_reg = rk817_codec_register,
215 .reg_defaults = rk817_reg_defaults,
216 .num_reg_defaults = ARRAY_SIZE(rk817_reg_defaults),
217 };
218
getCodecRegmap(void)219 struct regmap_config getCodecRegmap(void)
220 {
221 return rk817_codec_regmap_config;
222 }
223