1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 /* 23 * Dummy Model interface 24 */ 25 26 #ifndef _KBASE_MODEL_DUMMY_H_ 27 #define _KBASE_MODEL_DUMMY_H_ 28 29 #include <uapi/gpu/arm/bifrost/backend/gpu/mali_kbase_model_dummy.h> 30 31 #define model_error_log(module, ...) pr_err(__VA_ARGS__) 32 33 #define NUM_SLOTS 4 /*number of job slots */ 34 35 /*Errors Mask Codes*/ 36 /* each bit of errors_mask is associated to a specific error: 37 * NON FAULT STATUS CODES: only the following are implemented since the others 38 * represent normal working statuses 39 */ 40 #define KBASE_JOB_INTERRUPTED (1<<0) 41 #define KBASE_JOB_STOPPED (1<<1) 42 #define KBASE_JOB_TERMINATED (1<<2) 43 44 /* JOB EXCEPTIONS: */ 45 #define KBASE_JOB_CONFIG_FAULT (1<<3) 46 #define KBASE_JOB_POWER_FAULT (1<<4) 47 #define KBASE_JOB_READ_FAULT (1<<5) 48 #define KBASE_JOB_WRITE_FAULT (1<<6) 49 #define KBASE_JOB_AFFINITY_FAULT (1<<7) 50 #define KBASE_JOB_BUS_FAULT (1<<8) 51 #define KBASE_INSTR_INVALID_PC (1<<9) 52 #define KBASE_INSTR_INVALID_ENC (1<<10) 53 #define KBASE_INSTR_TYPE_MISMATCH (1<<11) 54 #define KBASE_INSTR_OPERAND_FAULT (1<<12) 55 #define KBASE_INSTR_TLS_FAULT (1<<13) 56 #define KBASE_INSTR_BARRIER_FAULT (1<<14) 57 #define KBASE_INSTR_ALIGN_FAULT (1<<15) 58 #define KBASE_DATA_INVALID_FAULT (1<<16) 59 #define KBASE_TILE_RANGE_FAULT (1<<17) 60 #define KBASE_ADDR_RANGE_FAULT (1<<18) 61 #define KBASE_OUT_OF_MEMORY (1<<19) 62 #define KBASE_UNKNOWN (1<<20) 63 64 /* GPU EXCEPTIONS:*/ 65 #define KBASE_DELAYED_BUS_FAULT (1<<21) 66 #define KBASE_SHAREABILITY_FAULT (1<<22) 67 68 /* MMU EXCEPTIONS:*/ 69 #define KBASE_TRANSLATION_FAULT (1<<23) 70 #define KBASE_PERMISSION_FAULT (1<<24) 71 #define KBASE_TRANSTAB_BUS_FAULT (1<<25) 72 #define KBASE_ACCESS_FLAG (1<<26) 73 74 /* generic useful bitmasks */ 75 #define IS_A_JOB_ERROR ((KBASE_UNKNOWN << 1) - KBASE_JOB_INTERRUPTED) 76 #define IS_A_MMU_ERROR ((KBASE_ACCESS_FLAG << 1) - KBASE_TRANSLATION_FAULT) 77 #define IS_A_GPU_ERROR (KBASE_DELAYED_BUS_FAULT|KBASE_SHAREABILITY_FAULT) 78 79 /* number of possible MMU address spaces */ 80 #define NUM_MMU_AS 16 /* total number of MMU address spaces as in 81 * MMU_IRQ_RAWSTAT register 82 */ 83 84 /* Forward declaration */ 85 struct kbase_device; 86 87 /* 88 * the function below is used to trigger the simulation of a faulty 89 * HW condition for a specific job chain atom 90 */ 91 92 struct kbase_error_params { 93 u64 jc; 94 u32 errors_mask; 95 u32 mmu_table_level; 96 u16 faulty_mmu_as; 97 u16 padding[3]; 98 }; 99 100 enum kbase_model_control_command { 101 /* Disable/Enable job completion in the dummy model */ 102 KBASE_MC_DISABLE_JOBS 103 }; 104 105 /* struct to control dummy model behavior */ 106 struct kbase_model_control_params { 107 s32 command; 108 s32 value; 109 }; 110 111 /* struct to track faulty atoms */ 112 struct kbase_error_atom { 113 struct kbase_error_params params; 114 struct kbase_error_atom *next; 115 }; 116 117 /*struct to track the system error state*/ 118 struct error_status_t { 119 u32 errors_mask; 120 u32 mmu_table_level; 121 int faulty_mmu_as; 122 123 u64 current_jc; 124 int current_job_slot; 125 126 u32 job_irq_rawstat; 127 u32 job_irq_status; 128 u32 js_status[NUM_SLOTS]; 129 130 u32 mmu_irq_mask; 131 u32 mmu_irq_rawstat; 132 133 u32 gpu_error_irq; 134 u32 gpu_fault_status; 135 136 u32 as_faultstatus[NUM_MMU_AS]; 137 u32 as_command[NUM_MMU_AS]; 138 u64 as_transtab[NUM_MMU_AS]; 139 }; 140 141 void *midgard_model_create(const void *config); 142 void midgard_model_destroy(void *h); 143 u8 midgard_model_write_reg(void *h, u32 addr, u32 value); 144 u8 midgard_model_read_reg(void *h, u32 addr, 145 u32 * const value); 146 void gpu_generate_error(void); 147 void midgard_set_error(int job_slot); 148 int job_atom_inject_error(struct kbase_error_params *params); 149 int gpu_model_control(void *h, 150 struct kbase_model_control_params *params); 151 152 void gpu_model_set_dummy_prfcnt_sample(u32 *usr_data, u32 usr_data_size); 153 void gpu_model_set_dummy_prfcnt_kernel_sample(u64 *usr_data, u32 usr_data_size); 154 void gpu_model_get_dummy_prfcnt_cores(struct kbase_device *kbdev, 155 u64 *l2_present, u64 *shader_present); 156 void gpu_model_set_dummy_prfcnt_cores(struct kbase_device *kbdev, 157 u64 l2_present, u64 shader_present); 158 void gpu_model_set_dummy_prfcnt_base_cpu(u32 *base, struct kbase_device *kbdev, 159 struct tagged_addr *pages, 160 size_t page_count); 161 /* Clear the counter values array maintained by the dummy model */ 162 void gpu_model_clear_prfcnt_values(void); 163 164 enum gpu_dummy_irq { 165 GPU_DUMMY_JOB_IRQ, 166 GPU_DUMMY_GPU_IRQ, 167 GPU_DUMMY_MMU_IRQ 168 }; 169 170 void gpu_device_raise_irq(void *model, 171 enum gpu_dummy_irq irq); 172 void gpu_device_set_data(void *model, void *data); 173 void *gpu_device_get_data(void *model); 174 175 extern struct error_status_t hw_error_status; 176 177 #endif 178