1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 20 #ifndef __HI_BOARD_H__ 21 #define __HI_BOARD_H__ 22 23 #include "hi_common.h" 24 25 #define DDRC0_REG_ADDR 0x12060000 /* base addr of DDRCB */ 26 #define DDRC_REGS_SIZE 0x10000 27 28 #define DDRC0_REG_STAT_CFG_ADDR (DDRC0_REG_ADDR + 0x260) 29 #define DDRC0_REG_STAT_WRITE_ADDR (DDRC0_REG_ADDR + 0x264) 30 #define DDRC0_REG_STAT_READ_ADDR (DDRC0_REG_ADDR + 0x268) 31 32 #define CRG_REGS_ADDR 0x12010000 33 #define CRG_REGS_SIZE 0X10000 34 35 #define SYS_REGS_ADDR 0x12020000 36 #define SYS_REGS_SIZE 0x8000 37 38 #define MISC_REGS_ADDR 0x12030000 39 #define MISC_REGS_SIZE 0x8000 40 41 #define SCT_REGS_ADDR 0x12040000 42 #define SCT_REGS_SIZE 0x100 43 44 #define OTP_REGS_ADDR 0x100A0000 45 #define OTP_REGS_SIZE 0X10000 46 47 #define VOU_REGS_ADDR 0x11440000 48 #define VOU_REGS_SIZE 0x40000 49 50 #define VGS0_REGS_ADDR 0x11240000 51 #define VGS_REGS_SIZE 0x10000 52 53 #define GDC0_BASE_ADDR 0x11110000 54 #define GDC_REGS_SIZE 0x10000 55 56 #define VPSS0_REGS_ADDR 0x11040000 57 #define VPSS_REGS_SIZE 0x10000 58 59 #define VI_CAP0_REGS_ADDR 0x11300000 60 #define VI_PROC0_REGS_ADDR 0x11000000 61 62 #define VEDU_0_REGS_ADDR 0x11500000 63 #define VEDU_REGS_SIZE 0x10000 64 65 #define JPEGU_REGS_ADDR 0x11220000 66 #define JPEGU_REGS_SIZE 0x10000 67 68 /* 0x11260000 ~ 0x1126FFFF */ 69 #define JPEGD_REGS_ADDR (0x11260000) 70 #define JPEGD_REGS_SIZE 0x10000 71 72 #define IVE_REGS_ADDR 0x11230000 73 #define IVE_REGS_SIZE 0x10000 74 #define IVE_CRG_RESET_REGS_ADDR 0x120100c0 75 76 #define SVP_NNIE_0_REGS_ADDR 0x11100000 77 #define SVP_NNIE_0_REGS_SIZE 0x10000 78 79 #define UDIR_REGS_ADDR 0x100CF000 80 #define UDIR_REGS_SIZE 0x20000 81 82 #define SCD_REGS_ADDR 0x10030000 83 84 /* Interrupt Request Number */ 85 #define VOU_IRQ_NR 90 86 #define VOU1_IRQ_NR 91 87 #define VI_CAP0_IRQ_NR 88 88 #define VI_PROC0_IRQ_NR 76 89 #define VPSS0_IRQ_NR 75 90 #define TDE_IRQ_NR 67 91 #define VGS0_IRQ_NR 70 92 #define AIO_IRQ_NR 87 93 #define VEDU_0_IRQ_NR 72 94 95 #define JPEGU_IRQ_NR 68 96 #define JPEGD_IRQ_NR 77 97 #define IVE_IRQ_NR 69 98 #define GDC0_IRQ_NR 74 99 #define SVP_NNIE_IRQ_NR0 73 100 101 #define SYS_PERCTL0_ADDR (0x0 + SYS_REGS_ADDR) 102 #define SYS_PERCTL1_ADDR (0x4 + SYS_REGS_ADDR) 103 #define SYS_PERCTL2_ADDR (0x8 + SYS_REGS_ADDR) 104 #define SYS_PERCTL3_ADDR (0xc + SYS_REGS_ADDR) 105 #define SYS_PERCTL4_ADDR (0x10 + SYS_REGS_ADDR) 106 #define SYS_PERCTL5_ADDR (0x14 + SYS_REGS_ADDR) 107 #define SYS_PERCTL6_ADDR (0x18 + SYS_REGS_ADDR) 108 #define SYS_PERCTL7_ADDR (0x1c + SYS_REGS_ADDR) 109 #define SYS_PERCTL8_ADDR (0x20 + SYS_REGS_ADDR) 110 #define SYS_PERCTL9_ADDR (0x24 + SYS_REGS_ADDR) 111 #define SYS_PERCTL10_ADDR (0x28 + SYS_REGS_ADDR) 112 #define SYS_PERCTL11_ADDR (0x2C + SYS_REGS_ADDR) 113 #define SYS_PERCTL12_ADDR (0x30 + SYS_REGS_ADDR) 114 #define SYS_PERCTL13_ADDR (0x34 + SYS_REGS_ADDR) 115 #define SYS_PERCTL14_ADDR (0x38 + SYS_REGS_ADDR) 116 #define SYS_PERCTL15_ADDR (0x3C + SYS_REGS_ADDR) 117 #define SYS_PERCTL16_ADDR (0x40 + SYS_REGS_ADDR) 118 #define SYS_PERCTL17_ADDR (0x44 + SYS_REGS_ADDR) 119 #define SYS_PERCTL18_ADDR (0x48 + SYS_REGS_ADDR) 120 #define SYS_PERCTL19_ADDR (0x4c + SYS_REGS_ADDR) 121 #define SYS_PERCTL20_ADDR (0x50 + SYS_REGS_ADDR) 122 #define SYS_PERCTL21_ADDR (0x54 + SYS_REGS_ADDR) 123 #define SYS_PERCTL22_ADDR (0x58 + SYS_REGS_ADDR) 124 #define SYS_PERCTL23_ADDR (0x5c + SYS_REGS_ADDR) 125 #define SYS_PERCTL24_ADDR (0x60 + SYS_REGS_ADDR) 126 #define SYS_PERCTL25_ADDR (0x64 + SYS_REGS_ADDR) 127 #define SYS_PERCTL26_ADDR (0x68 + SYS_REGS_ADDR) 128 #define SYS_PERCTL27_ADDR (0x6C + SYS_REGS_ADDR) 129 #define SYS_PERCTL28_ADDR (0x70 + SYS_REGS_ADDR) 130 #define SYS_PERCTL29_ADDR (0x74 + SYS_REGS_ADDR) 131 #define SYS_PERCTL30_ADDR (0x78 + SYS_REGS_ADDR) 132 #define SYS_PERCTL31_ADDR (0x7C + SYS_REGS_ADDR) 133 #define SYS_PERCTL32_ADDR (0x80 + SYS_REGS_ADDR) 134 #define SYS_PERCTL33_ADDR (0x84 + SYS_REGS_ADDR) 135 #define SYS_PERCTL34_ADDR (0x88 + SYS_REGS_ADDR) 136 #define SYS_PERCTL35_ADDR (0x8C + SYS_REGS_ADDR) 137 #define SYS_PERCTL36_ADDR (0x90 + SYS_REGS_ADDR) 138 #define SYS_PERCTL37_ADDR (0x94 + SYS_REGS_ADDR) 139 #define SYS_PERCTL38_ADDR (0x98 + SYS_REGS_ADDR) 140 #define SYS_PERCTL39_ADDR (0x9C + SYS_REGS_ADDR) 141 #define SYS_PERCTL40_ADDR (0xa0 + SYS_REGS_ADDR) 142 #define SYS_PERCTL41_ADDR (0xa4 + SYS_REGS_ADDR) 143 #define SYS_PERCTL42_ADDR (0xa8 + SYS_REGS_ADDR) 144 #define SYS_PERCTL43_ADDR (0xaC + SYS_REGS_ADDR) 145 #define SYS_PERCTL44_ADDR (0xb0 + SYS_REGS_ADDR) 146 #define SYS_PERCTL45_ADDR (0xb4 + SYS_REGS_ADDR) 147 #define SYS_PERCTL46_ADDR (0xb8 + SYS_REGS_ADDR) 148 #define SYS_PERCTL47_ADDR (0xbC + SYS_REGS_ADDR) 149 #define SYS_PERCTL48_ADDR (0xc0 + SYS_REGS_ADDR) 150 #define SYS_PERCTL49_ADDR (0xc4 + SYS_REGS_ADDR) 151 #define SYS_PERCTL50_ADDR (0xc8 + SYS_REGS_ADDR) 152 #define SYS_PERCTL51_ADDR (0xcC + SYS_REGS_ADDR) 153 #define SYS_PERCTL52_ADDR (0xd0 + SYS_REGS_ADDR) 154 #define SYS_PERCTL53_ADDR (0xd4 + SYS_REGS_ADDR) 155 #define SYS_PERCTL54_ADDR (0xd8 + SYS_REGS_ADDR) 156 #define SYS_PERCTL55_ADDR (0xdC + SYS_REGS_ADDR) 157 #define SYS_PERCTL56_ADDR (0xe0 + SYS_REGS_ADDR) 158 #define SYS_PERCTL57_ADDR (0xe4 + SYS_REGS_ADDR) 159 #define SYS_PERCTL58_ADDR (0xe8 + SYS_REGS_ADDR) 160 #define SYS_PERCTL59_ADDR (0xeC + SYS_REGS_ADDR) 161 #define SYS_PERCTL60_ADDR (0xf0 + SYS_REGS_ADDR) 162 #define SYS_PERCTL61_ADDR (0xf4 + SYS_REGS_ADDR) 163 #define SYS_PERCTL62_ADDR (0xf8 + SYS_REGS_ADDR) 164 #define SYS_PERCTL63_ADDR (0xfC + SYS_REGS_ADDR) 165 #define SYS_PERCTL64_ADDR (0x100 + SYS_REGS_ADDR) 166 #define SYS_PERCTL65_ADDR (0x104 + SYS_REGS_ADDR) 167 #define SYS_PERCTL66_ADDR (0x108 + SYS_REGS_ADDR) 168 #define SYS_PERCTL67_ADDR (0x10c + SYS_REGS_ADDR) 169 #define SYS_PERCTL68_ADDR (0x110 + SYS_REGS_ADDR) 170 #define SYS_PERCTL69_ADDR (0x114 + SYS_REGS_ADDR) 171 #define SYS_PERCTL70_ADDR (0x118 + SYS_REGS_ADDR) 172 #define SYS_PERCTL71_ADDR (0x11c + SYS_REGS_ADDR) 173 #define SYS_PERCTL72_ADDR (0x120 + SYS_REGS_ADDR) 174 #define SYS_PERCTL73_ADDR (0x124 + SYS_REGS_ADDR) 175 #define SYS_PERCTL74_ADDR (0x128 + SYS_REGS_ADDR) 176 #define SYS_PERCTL75_ADDR (0x12C + SYS_REGS_ADDR) 177 #define SYS_PERCTL76_ADDR (0x130 + SYS_REGS_ADDR) 178 #define SYS_PERCTL77_ADDR (0x134 + SYS_REGS_ADDR) 179 #define SYS_PERCTL78_ADDR (0x138 + SYS_REGS_ADDR) 180 #define SYS_PERCTL79_ADDR (0x13C + SYS_REGS_ADDR) 181 #define SYS_PERCTL80_ADDR (0x140 + SYS_REGS_ADDR) 182 #define SYS_PERCTL81_ADDR (0x144 + SYS_REGS_ADDR) 183 #define SYS_PERCTL82_ADDR (0x148 + SYS_REGS_ADDR) 184 #define SYS_PERCTL83_ADDR (0x14c + SYS_REGS_ADDR) 185 #define SYS_PERCTL84_ADDR (0x150 + SYS_REGS_ADDR) 186 #define SYS_PERCTL85_ADDR (0x154 + SYS_REGS_ADDR) 187 #define SYS_PERCTL86_ADDR (0x158 + SYS_REGS_ADDR) 188 #define SYS_PERCTL87_ADDR (0x15c + SYS_REGS_ADDR) 189 #define SYS_PERCTL88_ADDR (0x160 + SYS_REGS_ADDR) 190 #define SYS_PERCTL89_ADDR (0x164 + SYS_REGS_ADDR) 191 #define SYS_PERCTL90_ADDR (0x168 + SYS_REGS_ADDR) 192 #define SYS_PERCTL91_ADDR (0x16C + SYS_REGS_ADDR) 193 #define SYS_PERCTL92_ADDR (0x170 + SYS_REGS_ADDR) 194 #define SYS_PERCTL93_ADDR (0x174 + SYS_REGS_ADDR) 195 #define SYS_PERCTL94_ADDR (0x178 + SYS_REGS_ADDR) 196 #define SYS_PERCTL95_ADDR (0x17C + SYS_REGS_ADDR) 197 #define SYS_PERCTL96_ADDR (0x180 + SYS_REGS_ADDR) 198 #define SYS_PERCTL97_ADDR (0x184 + SYS_REGS_ADDR) 199 #define SYS_PERCTL98_ADDR (0x188 + SYS_REGS_ADDR) 200 #define SYS_PERCTL99_ADDR (0x18C + SYS_REGS_ADDR) 201 #define SYS_PERCTL100_ADDR (0x190 + SYS_REGS_ADDR) 202 #define SYS_PERCTL101_ADDR (0x194 + SYS_REGS_ADDR) 203 #define SYS_PERCTL102_ADDR (0x198 + SYS_REGS_ADDR) 204 #define SYS_PERCTL103_ADDR (0x19C + SYS_REGS_ADDR) 205 #define SYS_PERCTL104_ADDR (0x1a0 + SYS_REGS_ADDR) 206 #define SYS_PERCTL105_ADDR (0x1a4 + SYS_REGS_ADDR) 207 #define SYS_PERCTL106_ADDR (0x1a8 + SYS_REGS_ADDR) 208 #define SYS_PERCTL107_ADDR (0x1aC + SYS_REGS_ADDR) 209 #define SYS_PERCTL108_ADDR (0x1b0 + SYS_REGS_ADDR) 210 #define SYS_PERCTL109_ADDR (0x1b4 + SYS_REGS_ADDR) 211 #define SYS_PERCTL110_ADDR (0x1b8 + SYS_REGS_ADDR) 212 #define SYS_PERCTL111_ADDR (0x1bC + SYS_REGS_ADDR) 213 #define SYS_PERCTL112_ADDR (0x1c0 + SYS_REGS_ADDR) 214 #define SYS_PERCTL113_ADDR (0x1c4 + SYS_REGS_ADDR) 215 #define SYS_PERCTL114_ADDR (0x1c8 + SYS_REGS_ADDR) 216 #define SYS_PERCTL115_ADDR (0x1cC + SYS_REGS_ADDR) 217 #define SYS_PERCTL116_ADDR (0x1d0 + SYS_REGS_ADDR) 218 #define SYS_PERCTL117_ADDR (0x1d4 + SYS_REGS_ADDR) 219 #define SYS_PERCTL118_ADDR (0x1d8 + SYS_REGS_ADDR) 220 #define SYS_PERCTL119_ADDR (0x1dC + SYS_REGS_ADDR) 221 #define SYS_PERCTL120_ADDR (0x1e0 + SYS_REGS_ADDR) 222 #define SYS_PERCTL121_ADDR (0x1e4 + SYS_REGS_ADDR) 223 #define SYS_PERCTL122_ADDR (0x1e8 + SYS_REGS_ADDR) 224 #define SYS_PERCTL123_ADDR (0x1eC + SYS_REGS_ADDR) 225 #define SYS_PERCTL124_ADDR (0x1f0 + SYS_REGS_ADDR) 226 #define SYS_PERCTL125_ADDR (0x1f4 + SYS_REGS_ADDR) 227 #define SYS_PERCTL126_ADDR (0x1f8 + SYS_REGS_ADDR) 228 #define SYS_PERCTL127_ADDR (0x1fC + SYS_REGS_ADDR) 229 230 #define CRG_PERCTL0_ADDR (0x0 + CRG_REGS_ADDR) 231 #define CRG_PERCTL1_ADDR (0x4 + CRG_REGS_ADDR) 232 #define CRG_PERCTL2_ADDR (0x8 + CRG_REGS_ADDR) 233 #define CRG_PERCTL3_ADDR (0xc + CRG_REGS_ADDR) 234 #define CRG_PERCTL4_ADDR (0x10 + CRG_REGS_ADDR) 235 #define CRG_PERCTL5_ADDR (0x14 + CRG_REGS_ADDR) 236 #define CRG_PERCTL6_ADDR (0x18 + CRG_REGS_ADDR) 237 #define CRG_PERCTL7_ADDR (0x1c + CRG_REGS_ADDR) 238 #define CRG_PERCTL8_ADDR (0x20 + CRG_REGS_ADDR) 239 #define CRG_PERCTL9_ADDR (0x24 + CRG_REGS_ADDR) 240 #define CRG_PERCTL10_ADDR (0x28 + CRG_REGS_ADDR) 241 #define CRG_PERCTL11_ADDR (0x2C + CRG_REGS_ADDR) 242 #define CRG_PERCTL12_ADDR (0x30 + CRG_REGS_ADDR) 243 #define CRG_PERCTL13_ADDR (0x34 + CRG_REGS_ADDR) 244 #define CRG_PERCTL14_ADDR (0x38 + CRG_REGS_ADDR) 245 #define CRG_PERCTL15_ADDR (0x3C + CRG_REGS_ADDR) 246 #define CRG_PERCTL16_ADDR (0x40 + CRG_REGS_ADDR) 247 #define CRG_PERCTL17_ADDR (0x44 + CRG_REGS_ADDR) 248 #define CRG_PERCTL18_ADDR (0x48 + CRG_REGS_ADDR) 249 #define CRG_PERCTL19_ADDR (0x4c + CRG_REGS_ADDR) 250 #define CRG_PERCTL20_ADDR (0x50 + CRG_REGS_ADDR) 251 #define CRG_PERCTL21_ADDR (0x54 + CRG_REGS_ADDR) 252 #define CRG_PERCTL22_ADDR (0x58 + CRG_REGS_ADDR) 253 #define CRG_PERCTL23_ADDR (0x5c + CRG_REGS_ADDR) 254 #define CRG_PERCTL24_ADDR (0x60 + CRG_REGS_ADDR) 255 #define CRG_PERCTL25_ADDR (0x64 + CRG_REGS_ADDR) 256 #define CRG_PERCTL26_ADDR (0x68 + CRG_REGS_ADDR) 257 #define CRG_PERCTL27_ADDR (0x6C + CRG_REGS_ADDR) 258 #define CRG_PERCTL28_ADDR (0x70 + CRG_REGS_ADDR) 259 #define CRG_PERCTL29_ADDR (0x74 + CRG_REGS_ADDR) 260 #define CRG_PERCTL30_ADDR (0x78 + CRG_REGS_ADDR) 261 #define CRG_PERCTL31_ADDR (0x7C + CRG_REGS_ADDR) 262 #define CRG_PERCTL32_ADDR (0x80 + CRG_REGS_ADDR) 263 #define CRG_PERCTL33_ADDR (0x84 + CRG_REGS_ADDR) 264 #define CRG_PERCTL34_ADDR (0x88 + CRG_REGS_ADDR) 265 #define CRG_PERCTL35_ADDR (0x8C + CRG_REGS_ADDR) 266 #define CRG_PERCTL36_ADDR (0x90 + CRG_REGS_ADDR) 267 #define CRG_PERCTL37_ADDR (0x94 + CRG_REGS_ADDR) 268 #define CRG_PERCTL38_ADDR (0x98 + CRG_REGS_ADDR) 269 #define CRG_PERCTL39_ADDR (0x9C + CRG_REGS_ADDR) 270 #define CRG_PERCTL40_ADDR (0xa0 + CRG_REGS_ADDR) 271 #define CRG_PERCTL41_ADDR (0xa4 + CRG_REGS_ADDR) 272 #define CRG_PERCTL42_ADDR (0xa8 + CRG_REGS_ADDR) 273 #define CRG_PERCTL43_ADDR (0xaC + CRG_REGS_ADDR) 274 #define CRG_PERCTL44_ADDR (0xb0 + CRG_REGS_ADDR) 275 #define CRG_PERCTL45_ADDR (0xb4 + CRG_REGS_ADDR) 276 #define CRG_PERCTL46_ADDR (0xb8 + CRG_REGS_ADDR) 277 #define CRG_PERCTL47_ADDR (0xbC + CRG_REGS_ADDR) 278 #define CRG_PERCTL48_ADDR (0xc0 + CRG_REGS_ADDR) 279 #define CRG_PERCTL49_ADDR (0xc4 + CRG_REGS_ADDR) 280 #define CRG_PERCTL50_ADDR (0xc8 + CRG_REGS_ADDR) 281 #define CRG_PERCTL51_ADDR (0xcC + CRG_REGS_ADDR) 282 #define CRG_PERCTL52_ADDR (0xd0 + CRG_REGS_ADDR) 283 #define CRG_PERCTL53_ADDR (0xd4 + CRG_REGS_ADDR) 284 #define CRG_PERCTL54_ADDR (0xd8 + CRG_REGS_ADDR) 285 #define CRG_PERCTL55_ADDR (0xdC + CRG_REGS_ADDR) 286 #define CRG_PERCTL56_ADDR (0xe0 + CRG_REGS_ADDR) 287 #define CRG_PERCTL57_ADDR (0xe4 + CRG_REGS_ADDR) 288 #define CRG_PERCTL58_ADDR (0xe8 + CRG_REGS_ADDR) 289 #define CRG_PERCTL59_ADDR (0xeC + CRG_REGS_ADDR) 290 #define CRG_PERCTL60_ADDR (0xf0 + CRG_REGS_ADDR) 291 #define CRG_PERCTL61_ADDR (0xf4 + CRG_REGS_ADDR) 292 #define CRG_PERCTL62_ADDR (0xf8 + CRG_REGS_ADDR) 293 #define CRG_PERCTL63_ADDR (0xfC + CRG_REGS_ADDR) 294 #define CRG_PERCTL64_ADDR (0x100 + CRG_REGS_ADDR) 295 #define CRG_PERCTL65_ADDR (0x104 + CRG_REGS_ADDR) 296 #define CRG_PERCTL66_ADDR (0x108 + CRG_REGS_ADDR) 297 #define CRG_PERCTL67_ADDR (0x10c + CRG_REGS_ADDR) 298 #define CRG_PERCTL68_ADDR (0x110 + CRG_REGS_ADDR) 299 #define CRG_PERCTL69_ADDR (0x114 + CRG_REGS_ADDR) 300 #define CRG_PERCTL70_ADDR (0x118 + CRG_REGS_ADDR) 301 #define CRG_PERCTL71_ADDR (0x11c + CRG_REGS_ADDR) 302 #define CRG_PERCTL72_ADDR (0x120 + CRG_REGS_ADDR) 303 #define CRG_PERCTL73_ADDR (0x124 + CRG_REGS_ADDR) 304 #define CRG_PERCTL74_ADDR (0x128 + CRG_REGS_ADDR) 305 #define CRG_PERCTL75_ADDR (0x12C + CRG_REGS_ADDR) 306 #define CRG_PERCTL76_ADDR (0x130 + CRG_REGS_ADDR) 307 #define CRG_PERCTL77_ADDR (0x134 + CRG_REGS_ADDR) 308 #define CRG_PERCTL78_ADDR (0x138 + CRG_REGS_ADDR) 309 #define CRG_PERCTL79_ADDR (0x13C + CRG_REGS_ADDR) 310 #define CRG_PERCTL80_ADDR (0x140 + CRG_REGS_ADDR) 311 #define CRG_PERCTL81_ADDR (0x144 + CRG_REGS_ADDR) 312 #define CRG_PERCTL82_ADDR (0x148 + CRG_REGS_ADDR) 313 #define CRG_PERCTL83_ADDR (0x14c + CRG_REGS_ADDR) 314 #define CRG_PERCTL84_ADDR (0x150 + CRG_REGS_ADDR) 315 #define CRG_PERCTL85_ADDR (0x154 + CRG_REGS_ADDR) 316 #define CRG_PERCTL86_ADDR (0x158 + CRG_REGS_ADDR) 317 #define CRG_PERCTL87_ADDR (0x15c + CRG_REGS_ADDR) 318 #define CRG_PERCTL88_ADDR (0x160 + CRG_REGS_ADDR) 319 #define CRG_PERCTL89_ADDR (0x164 + CRG_REGS_ADDR) 320 #define CRG_PERCTL90_ADDR (0x168 + CRG_REGS_ADDR) 321 #define CRG_PERCTL91_ADDR (0x16C + CRG_REGS_ADDR) 322 #define CRG_PERCTL92_ADDR (0x170 + CRG_REGS_ADDR) 323 #define CRG_PERCTL93_ADDR (0x174 + CRG_REGS_ADDR) 324 #define CRG_PERCTL94_ADDR (0x178 + CRG_REGS_ADDR) 325 #define CRG_PERCTL95_ADDR (0x17C + CRG_REGS_ADDR) 326 #define CRG_PERCTL96_ADDR (0x180 + CRG_REGS_ADDR) 327 #define CRG_PERCTL97_ADDR (0x184 + CRG_REGS_ADDR) 328 #define CRG_PERCTL98_ADDR (0x188 + CRG_REGS_ADDR) 329 #define CRG_PERCTL99_ADDR (0x18C + CRG_REGS_ADDR) 330 #define CRG_PERCTL100_ADDR (0x190 + CRG_REGS_ADDR) 331 #define CRG_PERCTL101_ADDR (0x194 + CRG_REGS_ADDR) 332 #define CRG_PERCTL102_ADDR (0x198 + CRG_REGS_ADDR) 333 #define CRG_PERCTL103_ADDR (0x19C + CRG_REGS_ADDR) 334 #define CRG_PERCTL104_ADDR (0x1a0 + CRG_REGS_ADDR) 335 #define CRG_PERCTL105_ADDR (0x1a4 + CRG_REGS_ADDR) 336 #define CRG_PERCTL106_ADDR (0x1a8 + CRG_REGS_ADDR) 337 #define CRG_PERCTL107_ADDR (0x1aC + CRG_REGS_ADDR) 338 #define CRG_PERCTL108_ADDR (0x1b0 + CRG_REGS_ADDR) 339 #define CRG_PERCTL109_ADDR (0x1b4 + CRG_REGS_ADDR) 340 #define CRG_PERCTL110_ADDR (0x1b8 + CRG_REGS_ADDR) 341 #define CRG_PERCTL111_ADDR (0x1bC + CRG_REGS_ADDR) 342 #define CRG_PERCTL112_ADDR (0x1c0 + CRG_REGS_ADDR) 343 #define CRG_PERCTL113_ADDR (0x1c4 + CRG_REGS_ADDR) 344 #define CRG_PERCTL114_ADDR (0x1c8 + CRG_REGS_ADDR) 345 #define CRG_PERCTL115_ADDR (0x1cC + CRG_REGS_ADDR) 346 #define CRG_PERCTL116_ADDR (0x1d0 + CRG_REGS_ADDR) 347 #define CRG_PERCTL117_ADDR (0x1d4 + CRG_REGS_ADDR) 348 #define CRG_PERCTL118_ADDR (0x1d8 + CRG_REGS_ADDR) 349 #define CRG_PERCTL119_ADDR (0x1dC + CRG_REGS_ADDR) 350 #define CRG_PERCTL120_ADDR (0x1e0 + CRG_REGS_ADDR) 351 #define CRG_PERCTL121_ADDR (0x1e4 + CRG_REGS_ADDR) 352 #define CRG_PERCTL122_ADDR (0x1e8 + CRG_REGS_ADDR) 353 #define CRG_PERCTL123_ADDR (0x1eC + CRG_REGS_ADDR) 354 #define CRG_PERCTL124_ADDR (0x1f0 + CRG_REGS_ADDR) 355 #define CRG_PERCTL125_ADDR (0x1f4 + CRG_REGS_ADDR) 356 #define CRG_PERCTL126_ADDR (0x1f8 + CRG_REGS_ADDR) 357 #define CRG_PERCTL127_ADDR (0x1fC + CRG_REGS_ADDR) 358 359 #define MISC_CTL18_ADDR (0x18 + MISC_REGS_ADDR) 360 #define MISC_CTL34_ADDR (0x34 + MISC_REGS_ADDR) 361 #define MISC_CTL80_ADDR (0x80 + MISC_REGS_ADDR) 362 #define MISC_CTL88_ADDR (0x88 + MISC_REGS_ADDR) 363 #define MISC_CTL98_ADDR (0x98 + MISC_REGS_ADDR) 364 #define MISC_CTL9C_ADDR (0x9C + MISC_REGS_ADDR) 365 #define MISC_CTL12C_ADDR (0x12C + MISC_REGS_ADDR) 366 367 #define SYS_VI_DIV_SEL2 0x00 /* 2 division */ 368 #define SYS_VI_DIV_SEL4 0x01 /* 4 division */ 369 #define SYS_VI_DIV_SEL1 0x02 /* no division */ 370 371 #define SYS_VO_DIV_SEL1 0x00 /* 1 division */ 372 #define SYS_VO_DIV_SEL2 0x01 /* 2 division */ 373 #define SYS_VO_DIV_SEL4 0x02 /* 4 division */ 374 375 #define SYS_AIO_SAMPLE_CLK16 0x0 /* 16 division */ 376 #define SYS_AIO_SAMPLE_CLK32 0x01 /* 32 division */ 377 #define SYS_AIO_SAMPLE_CLK48 0x02 /* 48 division */ 378 #define SYS_AIO_SAMPLE_CLK64 0x03 /* 64 division */ 379 #define SYS_AIO_SAMPLE_CLK128 0x04 /* 128 division */ 380 #define SYS_AIO_SAMPLE_CLK256 0x05 /* 256 division */ 381 382 #define SYS_AIO_BS_CLK1 0x00 /* 1 division */ 383 #define SYS_AIO_BS_CLK2 0x02 /* 2 division */ 384 #define SYS_AIO_BS_CLK3 0x01 /* 3 division */ 385 #define SYS_AIO_BS_CLK4 0x03 /* 4 division */ 386 #define SYS_AIO_BS_CLK6 0x04 /* 6 division */ 387 #define SYS_AIO_BS_CLK8 0x05 /* 8 division */ 388 #define SYS_AIO_BS_CLK12 0x06 /* 12 division */ 389 #define SYS_AIO_BS_CLK16 0x07 /* 16 division */ 390 #define SYS_AIO_BS_CLK24 0x08 /* 24 division */ 391 #define SYS_AIO_BS_CLK32 0x09 /* 32 division */ 392 #define SYS_AIO_BS_CLK48 0x0a /* 48 division */ 393 #define SYS_AIO_BS_CLK64 0x0b /* 64 division */ 394 395 #endif /* __HI_BOARD_H__ */ 396 397