1 /* 2 * Copyright (c) 2009-2022 Huawei Technologies Co., Ltd. All rights reserved. 3 * 4 * UniProton is licensed under Mulan PSL v2. 5 * You can use this software according to the terms and conditions of the Mulan PSL v2. 6 * You may obtain a copy of Mulan PSL v2 at: 7 * http://license.coscl.org.cn/MulanPSL2 8 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 9 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 10 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 11 * See the Mulan PSL v2 for more details. 12 * Create: 2009-12-22 13 * Description: UniProton配置私有文件。 14 */ 15 #ifndef CPU_CONFIG_H 16 #define CPU_CONFIG_H 17 18 #include "cache_asm.h" 19 20 #define MMU_IMAGE_ADDR 0x93000000ULL 21 #define MMU_GIC_ADDR 0x24000000ULL 22 #define MMU_UART_ADDR 0x08743000ULL 23 #define MMU_OPENAMP_ADDR 0x90000000ULL 24 25 #define UART_BASE_ADDR MMU_UART_ADDR 26 27 #define TEST_CLK_INT 30 28 29 #define OS_GIC_VER 3 30 #define SICR_ADDR_OFFSET_PER_CORE 0x20000U 31 #define GIC_REG_BASE_ADDR 0x24000000ULL 32 33 #define GICD_CTLR_S_ADDR (GIC_REG_BASE_ADDR + 0x0000U) 34 #define GICD_IGROUPN_ADDR (GIC_REG_BASE_ADDR + 0x0080U) 35 #define GICD_ISENABLER0_ADDR (GIC_REG_BASE_ADDR + 0x0100U) 36 #define GICD_ICENABLER0_ADDR (GIC_REG_BASE_ADDR + 0x0180U) 37 #define GICD_IPRIORITYN_ADDR (GIC_REG_BASE_ADDR + 0x0400U) 38 #define GICD_IGRPMODRN_ADDR (GIC_REG_BASE_ADDR + 0x0D00U) 39 40 #define GICR_BASE0 (GIC_REG_BASE_ADDR + 0x40000U) 41 #define GICR_BASE1 (GIC_REG_BASE_ADDR + 0x50000U) 42 43 #define GICR_CTRL_ADDR (GICR_BASE0 + 0x0000U) 44 #define GICR_WAKER_ADDR (GICR_BASE0 + 0x0014U) 45 46 #define GICR_IGROUPR0_ADDR (GICR_BASE1 + 0x0080U) 47 #define GICR_ISENABLER0_ADDR (GICR_BASE1 + 0x0100U) 48 #define GICR_ICENABLER0_ADDR (GICR_BASE1 + 0x0180U) 49 #define GICR_IGRPMODR0_ADDR (GICR_BASE1 + 0x0D00U) 50 51 52 #define MAX_INT_NUM 387 53 #define MIN_GIC_SPI_NUM 32 54 #define SICD_IGROUP_INT_NUM 32 55 #define SICD_REG_SIZE 4 56 57 #define GROUP_MAX_BPR 0x7U 58 #define GROUP0_BP 0 59 #define GROUP1_BP 0 60 61 #define PRIO_MASK_LEVEL 0xFFU 62 63 #define ICC_SRE_EL1 S3_0_C12_C12_5 64 #define ICC_BPR0_EL1 S3_0_C12_C8_3 65 #define ICC_BPR1_EL1 S3_0_C12_C12_3 66 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 67 #define ICC_PMR_EL1 S3_0_C4_C6_0 68 69 #define PARAS_TO_STRING(x...) #x 70 #define REG_ALIAS(x...) PARAS_TO_STRING(x) 71 72 #define GIC_REG_READ(addr) (*(volatile U32 *)((uintptr_t)(addr))) 73 #define GIC_REG_WRITE(addr, data) (*(volatile U32 *)((uintptr_t)(addr)) = (U32)(data)) 74 75 #endif 76