1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _RGA_DRIVER_H_ 3 #define _RGA_DRIVER_H_ 4 5 #include <linux/mutex.h> 6 #include <linux/scatterlist.h> 7 8 /* Use 'r' as magic number */ 9 #define RGA_IOC_MAGIC 'r' 10 #define RGA_IOW(nr, type) _IOW(RGA_IOC_MAGIC, nr, type) 11 #define RGA_IOR(nr, type) _IOR(RGA_IOC_MAGIC, nr, type) 12 #define RGA_IOWR(nr, type) _IOWR(RGA_IOC_MAGIC, nr, type) 13 14 #define RGA_IOC_GET_DRVIER_VERSION RGA_IOR(0x1, struct rga_version_t) 15 #define RGA_IOC_GET_HW_VERSION RGA_IOR(0x2, struct rga_hw_versions_t) 16 #define RGA_IOC_IMPORT_BUFFER RGA_IOWR(0x3, struct rga_buffer_pool) 17 #define RGA_IOC_RELEASE_BUFFER RGA_IOW(0x4, struct rga_buffer_pool) 18 19 #define RGA_BLIT_SYNC 0x5017 20 #define RGA_BLIT_ASYNC 0x5018 21 #define RGA_FLUSH 0x5019 22 #define RGA_GET_RESULT 0x501a 23 #define RGA_GET_VERSION 0x501b 24 #define RGA_CACHE_FLUSH 0x501c 25 26 #define RGA2_GET_VERSION 0x601b 27 #define RGA_IMPORT_DMA 0x601d 28 #define RGA_RELEASE_DMA 0x601e 29 30 #define RGA_OUT_OF_RESOURCES -10 31 #define RGA_MALLOC_ERROR -11 32 33 #define SCALE_DOWN_LARGE 1 34 #define SCALE_UP_LARGE 1 35 36 #define RGA_BUFFER_POOL_SIZE_MAX 40 37 38 #define RGA3_MAJOR_VERSION_MASK (0xF0000000) 39 #define RGA3_MINOR_VERSION_MASK (0x0FF00000) 40 #define RGA3_SVN_VERSION_MASK (0x000FFFFF) 41 42 #define RGA2_MAJOR_VERSION_MASK (0xFF000000) 43 #define RGA2_MINOR_VERSION_MASK (0x00F00000) 44 #define RGA2_SVN_VERSION_MASK (0x000FFFFF) 45 46 #define RGA_MODE_ROTATE_0 (1<<0) 47 #define RGA_MODE_ROTATE_90 (1<<1) 48 #define RGA_MODE_ROTATE_180 (1<<2) 49 #define RGA_MODE_ROTATE_270 (1<<3) 50 #define RGA_MODE_X_MIRROR (1<<4) 51 #define RGA_MODE_Y_MIRROR (1<<5) 52 53 #define RGA_MODE_CSC_BT601L (1<<0) 54 #define RGA_MODE_CSC_BT601F (1<<1) 55 #define RGA_MODE_CSC_BT709 (1<<2) 56 #define RGA_MODE_CSC_BT2020 (1<<3) 57 58 #define RGA_MODE_ROTATE_MASK (\ 59 RGA_MODE_ROTATE_0 | \ 60 RGA_MODE_ROTATE_90 | \ 61 RGA_MODE_ROTATE_180 | \ 62 RGA_MODE_ROTATE_270 | \ 63 RGA_MODE_X_MIRROR | \ 64 RGA_MODE_Y_MIRROR) 65 66 enum rga_memory_type { 67 RGA_DMA_BUFFER = 0, 68 RGA_VIRTUAL_ADDRESS, 69 RGA_PHYSICAL_ADDRESS 70 }; 71 72 enum rga_scale_up_mode { 73 RGA_SCALE_UP_NONE = 0x0, 74 RGA_SCALE_UP_BIC = 0x1, 75 }; 76 77 enum rga_scale_down_mode { 78 RGA_SCALE_DOWN_NONE = 0x0, 79 RGA_SCALE_DOWN_AVG = 0x1, 80 }; 81 82 /* RGA process mode enum */ 83 enum { 84 BITBLT_MODE = 0x0, 85 COLOR_PALETTE_MODE = 0x1, 86 COLOR_FILL_MODE = 0x2, 87 /* used by rga2 */ 88 UPDATE_PALETTE_TABLE_MODE = 0x6, 89 UPDATE_PATTEN_BUF_MODE = 0x7, 90 }; /*render mode*/ 91 92 /* RGA rd_mode */ 93 enum { 94 RGA_RASTER_MODE = 0x1 << 0, 95 RGA_FBC_MODE = 0x1 << 1, 96 RGA_TILE_MODE = 0x1 << 2, 97 }; 98 99 /* RGA feature */ 100 enum { 101 RGA_COLOR_FILL = 0x1 << 0, 102 RGA_COLOR_PALETTE = 0x1 << 1, 103 RGA_COLOR_KEY = 0x1 << 2, 104 RGA_ROP_CALCULATE = 0x1 << 3, 105 RGA_NN_QUANTIZE = 0x1 << 4, 106 RGA_OSD_BLEND = 0x1 << 5, 107 RGA_DITHER = 0x1 << 6, 108 }; 109 110 enum { 111 RGA2_FORMAT_RGBA_8888 = 0x0, 112 RGA2_FORMAT_RGBX_8888 = 0x1, 113 RGA2_FORMAT_RGB_888 = 0x2, 114 RGA2_FORMAT_BGRA_8888 = 0x3, 115 RGA2_FORMAT_BGRX_8888 = 0x4, 116 RGA2_FORMAT_BGR_888 = 0x5, 117 RGA2_FORMAT_RGB_565 = 0x6, 118 RGA2_FORMAT_RGBA_5551 = 0x7, 119 RGA2_FORMAT_RGBA_4444 = 0x8, 120 RGA2_FORMAT_BGR_565 = 0x9, 121 RGA2_FORMAT_BGRA_5551 = 0xa, 122 RGA2_FORMAT_BGRA_4444 = 0xb, 123 124 RGA2_FORMAT_Y4 = 0xe, 125 RGA2_FORMAT_YCbCr_400 = 0xf, 126 127 RGA2_FORMAT_YCbCr_422_SP = 0x10, 128 RGA2_FORMAT_YCbCr_422_P = 0x11, 129 RGA2_FORMAT_YCbCr_420_SP = 0x12, 130 RGA2_FORMAT_YCbCr_420_P = 0x13, 131 RGA2_FORMAT_YCrCb_422_SP = 0x14, 132 RGA2_FORMAT_YCrCb_422_P = 0x15, 133 RGA2_FORMAT_YCrCb_420_SP = 0x16, 134 RGA2_FORMAT_YCrCb_420_P = 0x17, 135 136 RGA2_FORMAT_YVYU_422 = 0x18, 137 RGA2_FORMAT_YVYU_420 = 0x19, 138 RGA2_FORMAT_VYUY_422 = 0x1a, 139 RGA2_FORMAT_VYUY_420 = 0x1b, 140 RGA2_FORMAT_YUYV_422 = 0x1c, 141 RGA2_FORMAT_YUYV_420 = 0x1d, 142 RGA2_FORMAT_UYVY_422 = 0x1e, 143 RGA2_FORMAT_UYVY_420 = 0x1f, 144 145 RGA2_FORMAT_YCbCr_420_SP_10B = 0x20, 146 RGA2_FORMAT_YCrCb_420_SP_10B = 0x21, 147 RGA2_FORMAT_YCbCr_422_SP_10B = 0x22, 148 RGA2_FORMAT_YCrCb_422_SP_10B = 0x23, 149 150 RGA2_FORMAT_BPP_1 = 0x24, 151 RGA2_FORMAT_BPP_2 = 0x25, 152 RGA2_FORMAT_BPP_4 = 0x26, 153 RGA2_FORMAT_BPP_8 = 0x27, 154 155 RGA2_FORMAT_ARGB_8888 = 0x28, 156 RGA2_FORMAT_XRGB_8888 = 0x29, 157 RGA2_FORMAT_ARGB_5551 = 0x2a, 158 RGA2_FORMAT_ARGB_4444 = 0x2b, 159 RGA2_FORMAT_ABGR_8888 = 0x2c, 160 RGA2_FORMAT_XBGR_8888 = 0x2d, 161 RGA2_FORMAT_ABGR_5551 = 0x2e, 162 RGA2_FORMAT_ABGR_4444 = 0x2f, 163 }; 164 165 #define RGA_SCHED_PRIORITY_DEFAULT 0 166 #define RGA_SCHED_PRIORITY_MAX 6 167 168 #define RGA_VERSION_SIZE 16 169 #define RGA_HW_SIZE 5 170 171 struct rga_version_t { 172 uint32_t major; 173 uint32_t minor; 174 uint32_t revision; 175 uint8_t str[RGA_VERSION_SIZE]; 176 }; 177 178 struct rga_hw_versions_t { 179 struct rga_version_t version[RGA_HW_SIZE]; 180 uint32_t size; 181 }; 182 183 struct rga_memory_parm { 184 uint32_t width; 185 uint32_t height; 186 uint32_t format; 187 }; 188 189 struct rga_external_buffer { 190 uint64_t memory; 191 uint32_t type; 192 193 uint32_t handle; 194 struct rga_memory_parm memory_parm; 195 196 uint8_t reserve[256]; 197 }; 198 199 struct rga_buffer_pool { 200 struct rga_external_buffer __user *buffers; 201 uint32_t size; 202 }; 203 204 struct rga_mmu_info_t { 205 unsigned long src0_base_addr; 206 unsigned long src1_base_addr; 207 unsigned long dst_base_addr; 208 unsigned long els_base_addr; 209 210 /* [0] mmu enable [1] flush [2] prefetch_en [3] prefetch dir */ 211 u8 src0_mmu_flag; 212 u8 src1_mmu_flag; 213 u8 dst_mmu_flag; 214 u8 els_mmu_flag; 215 }; 216 217 struct rga_color_fill_t { 218 int16_t gr_x_a; 219 int16_t gr_y_a; 220 int16_t gr_x_b; 221 int16_t gr_y_b; 222 int16_t gr_x_g; 223 int16_t gr_y_g; 224 int16_t gr_x_r; 225 int16_t gr_y_r; 226 }; 227 228 /***************************************/ 229 /* porting from rga.h for msg convert */ 230 /***************************************/ 231 232 struct rga_fading_t { 233 uint8_t b; 234 uint8_t g; 235 uint8_t r; 236 uint8_t res; 237 }; 238 239 struct rga_mmu_t { 240 uint8_t mmu_en; 241 uint64_t base_addr; 242 /* 243 * [0] mmu enable [1] src_flush [2] dst_flush 244 * [3] CMD_flush [4~5] page size 245 */ 246 uint32_t mmu_flag; 247 }; 248 249 struct rga_rect_t { 250 uint16_t xmin; 251 /* width - 1 */ 252 uint16_t xmax; 253 uint16_t ymin; 254 /* height - 1 */ 255 uint16_t ymax; 256 }; 257 258 struct rga_point_t { 259 uint16_t x; 260 uint16_t y; 261 }; 262 263 struct rga_line_draw_t { 264 /* LineDraw_start_point */ 265 struct rga_point_t start_point; 266 /* LineDraw_end_point */ 267 struct rga_point_t end_point; 268 /* LineDraw_color */ 269 uint32_t color; 270 /* (enum) LineDrawing mode sel */ 271 uint32_t flag; 272 /* range 1~16 */ 273 uint32_t line_width; 274 }; 275 276 /* color space convert coefficient. */ 277 struct rga_csc_coe_t { 278 int16_t r_v; 279 int16_t g_y; 280 int16_t b_u; 281 int32_t off; 282 }; 283 284 struct rga_full_csc_t { 285 uint8_t flag; 286 struct rga_csc_coe_t coe_y; 287 struct rga_csc_coe_t coe_u; 288 struct rga_csc_coe_t coe_v; 289 }; 290 291 struct rga_win_info_t { 292 /* yrgb mem addr */ 293 unsigned long yrgb_addr; 294 /* cb/cr mem addr */ 295 unsigned long uv_addr; 296 /* cr mem addr */ 297 unsigned long v_addr; 298 /* definition by RK_FORMAT */ 299 unsigned int format; 300 301 unsigned short src_act_w; 302 unsigned short src_act_h; 303 304 unsigned short dst_act_w; 305 unsigned short dst_act_h; 306 307 unsigned short x_offset; 308 unsigned short y_offset; 309 310 unsigned short vir_w; 311 unsigned short vir_h; 312 313 unsigned short y2r_mode; 314 unsigned short r2y_mode; 315 316 unsigned short rotate_mode; 317 /* RASTER or FBCD or TILE */ 318 unsigned short rd_mode; 319 320 unsigned short is_10b_compact; 321 unsigned short is_10b_endian; 322 323 unsigned short enable; 324 }; 325 326 struct rga_img_info_t { 327 /* yrgb mem addr */ 328 uint64_t yrgb_addr; 329 /* cb/cr mem addr */ 330 uint64_t uv_addr; 331 /* cr mem addr */ 332 uint64_t v_addr; 333 /* definition by RK_FORMAT */ 334 uint32_t format; 335 336 uint16_t act_w; 337 uint16_t act_h; 338 uint16_t x_offset; 339 uint16_t y_offset; 340 341 uint16_t vir_w; 342 uint16_t vir_h; 343 344 uint16_t endian_mode; 345 /* useless */ 346 uint16_t alpha_swap; 347 348 /* used by RGA3 */ 349 uint16_t rotate_mode; 350 uint16_t rd_mode; 351 352 uint16_t is_10b_compact; 353 uint16_t is_10b_endian; 354 355 uint16_t enable; 356 }; 357 358 struct rga_req { 359 /* (enum) process mode sel */ 360 uint8_t render_mode; 361 362 struct rga_img_info_t src; 363 struct rga_img_info_t dst; 364 struct rga_img_info_t pat; 365 366 /* rop4 mask addr */ 367 uint64_t rop_mask_addr; 368 /* LUT addr */ 369 uint64_t LUT_addr; 370 371 /* dst clip window default value is dst_vir */ 372 /* value from [0, w-1] / [0, h-1]*/ 373 struct rga_rect_t clip; 374 375 /* dst angle default value 0 16.16 scan from table */ 376 int32_t sina; 377 /* dst angle default value 0 16.16 scan from table */ 378 int32_t cosa; 379 380 /* alpha rop process flag */ 381 /* ([0] = 1 alpha_rop_enable) */ 382 /* ([1] = 1 rop enable) */ 383 /* ([2] = 1 fading_enable) */ 384 /* ([3] = 1 PD_enable) */ 385 /* ([4] = 1 alpha cal_mode_sel) */ 386 /* ([5] = 1 dither_enable) */ 387 /* ([6] = 1 gradient fill mode sel) */ 388 /* ([7] = 1 AA_enable) */ 389 uint16_t alpha_rop_flag; 390 391 /* 0 nearst / 1 bilnear / 2 bicubic */ 392 uint8_t scale_mode; 393 394 /* color key max */ 395 uint32_t color_key_max; 396 /* color key min */ 397 uint32_t color_key_min; 398 399 /* foreground color */ 400 uint32_t fg_color; 401 /* background color */ 402 uint32_t bg_color; 403 404 /* color fill use gradient */ 405 struct rga_color_fill_t gr_color; 406 407 struct rga_line_draw_t line_draw_info; 408 409 struct rga_fading_t fading; 410 411 /* porter duff alpha mode sel */ 412 uint8_t PD_mode; 413 414 /* global alpha value */ 415 uint8_t alpha_global_value; 416 417 /* rop2/3/4 code scan from rop code table*/ 418 uint16_t rop_code; 419 420 /* [2] 0 blur 1 sharp / [1:0] filter_type*/ 421 uint8_t bsfilter_flag; 422 423 /* (enum) color palette 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 424 uint8_t palette_mode; 425 426 /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 427 uint8_t yuv2rgb_mode; 428 429 /* 0/big endian 1/little endian*/ 430 uint8_t endian_mode; 431 432 /* (enum) rotate mode */ 433 /* 0x0, no rotate */ 434 /* 0x1, rotate */ 435 /* 0x2, x_mirror */ 436 /* 0x3, y_mirror */ 437 uint8_t rotate_mode; 438 439 /* 0 solid color / 1 pattern color */ 440 uint8_t color_fill_mode; 441 442 /* mmu information */ 443 struct rga_mmu_t mmu_info; 444 445 /* ([0~1] alpha mode) */ 446 /* ([2~3] rop mode) */ 447 /* ([4] zero mode en) */ 448 /* ([5] dst alpha mode) */ 449 /* ([6] alpha output mode sel) 0 src / 1 dst*/ 450 uint8_t alpha_rop_mode; 451 452 uint8_t src_trans_mode; 453 454 uint8_t dither_mode; 455 456 /* full color space convert */ 457 struct rga_full_csc_t full_csc; 458 459 int32_t in_fence_fd; 460 uint8_t core; 461 uint8_t priority; 462 int32_t out_fence_fd; 463 464 uint8_t handle_flag; 465 466 uint8_t reservr[127]; 467 }; 468 469 struct rga2_req { 470 /* (enum) process mode sel */ 471 u8 render_mode; 472 473 /* active window */ 474 struct rga_img_info_t src; 475 struct rga_img_info_t src1; 476 struct rga_img_info_t dst; 477 struct rga_img_info_t pat; 478 479 /* rop4 mask addr */ 480 unsigned long rop_mask_addr; 481 /* LUT addr */ 482 unsigned long LUT_addr; 483 484 u32 rop_mask_stride; 485 486 /* 0: SRC + DST => DST */ 487 /* 1: SRC + SRC1 => DST */ 488 u8 bitblt_mode; 489 490 /* [1:0] */ 491 /* 0 degree 0x0 */ 492 /* 90 degree 0x1 */ 493 /* 180 degree 0x2 */ 494 /* 270 degree 0x3 */ 495 /* [5:4] */ 496 /* none 0x0 */ 497 /* x_mirror 0x1 */ 498 /* y_mirror 0x2 */ 499 /* x_mirror + y_mirror 0x3 */ 500 u8 rotate_mode; 501 502 /* alpha rop process flag */ 503 /* ([0] = 1 alpha_rop_enable) */ 504 /* ([1] = 1 rop enable) */ 505 /* ([2] = 1 fading_enable) */ 506 /* ([3] = 1 alpha cal_mode_sel) */ 507 /* ([4] = 1 src_dither_up_enable) */ 508 /* ([5] = 1 dst_dither_up_enable) */ 509 /* ([6] = 1 dither_down_enable) */ 510 /* ([7] = 1 gradient fill mode sel) */ 511 u16 alpha_rop_flag; 512 513 /* [0] SrcAlphaMode0 */ 514 /* [2:1] SrcGlobalAlphaMode0 */ 515 /* [3] SrcAlphaSelectMode0 */ 516 /* [6:4] SrcFactorMode0 */ 517 /* [7] SrcColorMode */ 518 519 /* [8] DstAlphaMode0 */ 520 /* [10:9] DstGlobalAlphaMode0 */ 521 /* [11] DstAlphaSelectMode0 */ 522 /* [14:12] DstFactorMode0 */ 523 /* [15] DstColorMode0 */ 524 u16 alpha_mode_0; 525 526 /* [0] SrcAlphaMode1 */ 527 /* [2:1] SrcGlobalAlphaMode1 */ 528 /* [3] SrcAlphaSelectMode1 */ 529 /* [6:4] SrcFactorMode1 */ 530 531 /* [8] DstAlphaMode1 */ 532 /* [10:9] DstGlobalAlphaMode1 */ 533 /* [11] DstAlphaSelectMode1 */ 534 /* [14:12] DstFactorMode1 */ 535 u16 alpha_mode_1; 536 537 /* 0 1 2 3 */ 538 u8 scale_bicu_mode; 539 540 u32 color_key_max; 541 u32 color_key_min; 542 543 /* foreground color */ 544 u32 fg_color; 545 /* background color */ 546 u32 bg_color; 547 548 u8 color_fill_mode; 549 /* color fill use gradient */ 550 struct rga_color_fill_t gr_color; 551 552 /* Fading value */ 553 u8 fading_alpha_value; 554 u8 fading_r_value; 555 u8 fading_g_value; 556 u8 fading_b_value; 557 558 /* src global alpha value */ 559 u8 src_a_global_val; 560 /* dst global alpha value */ 561 u8 dst_a_global_val; 562 563 /* rop mode select 0 : rop2 1 : rop3 2 : rop4 */ 564 u8 rop_mode; 565 /* rop2/3/4 code */ 566 u16 rop_code; 567 568 /* (enum) color palette 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 569 u8 palette_mode; 570 571 /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 572 u8 yuv2rgb_mode; 573 574 /* [1:0] src0 csc mode */ 575 /* [3:2] dst csc mode */ 576 /* [4] dst csc clip enable */ 577 /* [6:5] src1 csc mdoe */ 578 /* [7] src1 csc clip enable */ 579 /* full color space convert */ 580 struct rga_full_csc_t full_csc; 581 582 /* 0/little endian 1/big endian */ 583 u8 endian_mode; 584 585 u8 CMD_fin_int_enable; 586 587 /* mmu information */ 588 struct rga_mmu_info_t mmu_info; 589 590 u8 alpha_zero_key; 591 u8 src_trans_mode; 592 593 /* useless */ 594 u8 alpha_swp; 595 u8 dither_mode; 596 597 u8 rgb2yuv_mode; 598 }; 599 600 struct rga3_req { 601 /* (enum) process mode sel */ 602 u8 render_mode; 603 604 struct rga_win_info_t win0; 605 struct rga_win_info_t wr; 606 struct rga_win_info_t win1; 607 608 /* rop4 mask addr */ 609 unsigned long rop_mask_addr; 610 unsigned long LUT_addr; 611 612 u32 rop_mask_stride; 613 614 u8 bitblt_mode; 615 u8 rotate_mode; 616 617 u16 alpha_rop_flag; 618 619 u16 alpha_mode_0; 620 u16 alpha_mode_1; 621 622 u8 scale_bicu_mode; 623 624 u32 color_key_max; 625 u32 color_key_min; 626 627 u32 fg_color; 628 u32 bg_color; 629 630 u8 color_fill_mode; 631 struct rga_color_fill_t gr_color; 632 633 u8 fading_alpha_value; 634 u8 fading_r_value; 635 u8 fading_g_value; 636 u8 fading_b_value; 637 638 /* win0 global alpha value */ 639 u8 win0_a_global_val; 640 /* win1 global alpha value */ 641 u8 win1_a_global_val; 642 643 u8 rop_mode; 644 u16 rop_code; 645 646 u8 palette_mode; 647 648 u8 yuv2rgb_mode; 649 650 u8 endian_mode; 651 652 u8 CMD_fin_int_enable; 653 654 struct rga_mmu_info_t mmu_info; 655 656 u8 alpha_zero_key; 657 u8 src_trans_mode; 658 659 u8 alpha_swp; 660 u8 dither_mode; 661 662 u8 rgb2yuv_mode; 663 }; 664 665 struct rga_mpi_job_t { 666 struct dma_buf *dma_buf_src0; 667 struct dma_buf *dma_buf_src1; 668 struct dma_buf *dma_buf_dst; 669 }; 670 671 int rga_mpi_commit(struct rga_req *cmd, struct rga_mpi_job_t *mpi_job); 672 673 #endif /*_RGA_DRIVER_H_*/ 674