1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * SDIO spec header file 4 * Protocol and standard (common) device definitions 5 * 6 * Copyright (C) 1999-2019, Broadcom. 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: sdio.h 689948 2017-03-14 05:21:03Z $ 30 */ 31 32 #ifndef _SDIO_H 33 #define _SDIO_H 34 35 #ifdef BCMSDIO 36 37 /* CCCR structure for function 0 */ 38 typedef volatile struct { 39 uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */ 40 uint8 sd_rev; /* RO, sd spec revision */ 41 uint8 io_en; /* I/O enable */ 42 uint8 io_rdy; /* I/O ready reg */ 43 uint8 intr_ctl; /* Master and per function interrupt enable control */ 44 uint8 intr_status; /* RO, interrupt pending status */ 45 uint8 io_abort; /* read/write abort or reset all functions */ 46 uint8 bus_inter; /* bus interface control */ 47 uint8 capability; /* RO, card capability */ 48 49 uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */ 50 uint8 cis_base_mid; 51 uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */ 52 53 /* suspend/resume registers */ 54 uint8 bus_suspend; /* 0xC */ 55 uint8 func_select; /* 0xD */ 56 uint8 exec_flag; /* 0xE */ 57 uint8 ready_flag; /* 0xF */ 58 59 uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */ 60 61 uint8 power_control; /* 0x12 (SDIO version 1.10) */ 62 63 uint8 speed_control; /* 0x13 */ 64 } sdio_regs_t; 65 66 /* SDIO Device CCCR offsets */ 67 #define SDIOD_CCCR_REV 0x00 68 #define SDIOD_CCCR_SDREV 0x01 69 #define SDIOD_CCCR_IOEN 0x02 70 #define SDIOD_CCCR_IORDY 0x03 71 #define SDIOD_CCCR_INTEN 0x04 72 #define SDIOD_CCCR_INTPEND 0x05 73 #define SDIOD_CCCR_IOABORT 0x06 74 #define SDIOD_CCCR_BICTRL 0x07 75 #define SDIOD_CCCR_CAPABLITIES 0x08 76 #define SDIOD_CCCR_CISPTR_0 0x09 77 #define SDIOD_CCCR_CISPTR_1 0x0A 78 #define SDIOD_CCCR_CISPTR_2 0x0B 79 #define SDIOD_CCCR_BUSSUSP 0x0C 80 #define SDIOD_CCCR_FUNCSEL 0x0D 81 #define SDIOD_CCCR_EXECFLAGS 0x0E 82 #define SDIOD_CCCR_RDYFLAGS 0x0F 83 #define SDIOD_CCCR_BLKSIZE_0 0x10 84 #define SDIOD_CCCR_BLKSIZE_1 0x11 85 #define SDIOD_CCCR_POWER_CONTROL 0x12 86 #define SDIOD_CCCR_SPEED_CONTROL 0x13 87 #define SDIOD_CCCR_UHSI_SUPPORT 0x14 88 #define SDIOD_CCCR_DRIVER_STRENGTH 0x15 89 #define SDIOD_CCCR_INTR_EXTN 0x16 90 91 /* Broadcom extensions (corerev >= 1) */ 92 #define SDIOD_CCCR_BRCM_CARDCAP 0xf0 93 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02 94 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04 95 #define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08 96 #define SDIOD_CCCR_BRCM_CARDCTL 0xf1 97 #define SDIOD_CCCR_BRCM_SEPINT 0xf2 98 99 /* cccr_sdio_rev */ 100 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ 101 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ 102 #define SDIO_SPEC_VERSION_3_0 0x40 /* SDIO spec version 3.0 */ 103 104 /* sd_rev */ 105 #define SD_REV_PHY_MASK 0x0f /* SD format version number */ 106 107 /* io_en */ 108 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ 109 #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */ 110 #if defined(BT_OVER_SDIO) 111 #define SDIO_FUNC_ENABLE_3 0x08 /* function 2 I/O enable */ 112 #define SDIO_FUNC_DISABLE_3 0xF0 /* function 2 I/O enable */ 113 #endif /* defined (BT_OVER_SDIO) */ 114 115 /* io_rdys */ 116 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ 117 #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */ 118 119 /* intr_ctl */ 120 #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ 121 #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ 122 #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */ 123 #if defined(BT_OVER_SDIO) 124 #define INTR_CTL_FUNC3_EN 0x8 /* interrupt enable for function 3 */ 125 #endif /* defined (BT_OVER_SDIO) */ 126 /* intr_status */ 127 #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ 128 #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */ 129 130 /* io_abort */ 131 #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ 132 #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */ 133 134 /* bus_inter */ 135 #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ 136 #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ 137 #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ 138 #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */ 139 #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ 140 #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ 141 142 /* capability */ 143 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ 144 #define SDIO_CAP_LSC 0x40 /* low speed card */ 145 #define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */ 146 #define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */ 147 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */ 148 #define SDIO_CAP_SRW 0x04 /* support read wait */ 149 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ 150 #define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */ 151 152 /* power_control */ 153 #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */ 154 #define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */ 155 156 /* speed_control (control device entry into high-speed clocking mode) */ 157 #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */ 158 #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */ 159 #define SDIO_SPEED_UHSI_DDR50 0x08 160 161 /* for setting bus speed in card: 0x13h */ 162 #define SDIO_BUS_SPEED_UHSISEL_M BITFIELD_MASK(3) 163 #define SDIO_BUS_SPEED_UHSISEL_S 1 164 165 /* for getting bus speed cap in card: 0x14h */ 166 #define SDIO_BUS_SPEED_UHSICAP_M BITFIELD_MASK(3) 167 #define SDIO_BUS_SPEED_UHSICAP_S 0 168 169 /* for getting driver type CAP in card: 0x15h */ 170 #define SDIO_BUS_DRVR_TYPE_CAP_M BITFIELD_MASK(3) 171 #define SDIO_BUS_DRVR_TYPE_CAP_S 0 172 173 /* for setting driver type selection in card: 0x15h */ 174 #define SDIO_BUS_DRVR_TYPE_SEL_M BITFIELD_MASK(2) 175 #define SDIO_BUS_DRVR_TYPE_SEL_S 4 176 177 /* for getting async int support in card: 0x16h */ 178 #define SDIO_BUS_ASYNCINT_CAP_M BITFIELD_MASK(1) 179 #define SDIO_BUS_ASYNCINT_CAP_S 0 180 181 /* for setting async int selection in card: 0x16h */ 182 #define SDIO_BUS_ASYNCINT_SEL_M BITFIELD_MASK(1) 183 #define SDIO_BUS_ASYNCINT_SEL_S 1 184 185 /* brcm sepint */ 186 #define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */ 187 #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */ 188 #define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */ 189 190 /* FBR structure for function 1-7, FBR addresses and register offsets */ 191 typedef volatile struct { 192 uint8 devctr; /* device interface, CSA control */ 193 uint8 ext_dev; /* extended standard I/O device type code */ 194 uint8 pwr_sel; /* power selection support */ 195 uint8 PAD[6]; /* reserved */ 196 197 uint8 cis_low; /* CIS LSB */ 198 uint8 cis_mid; 199 uint8 cis_high; /* CIS MSB */ 200 uint8 csa_low; /* code storage area, LSB */ 201 uint8 csa_mid; 202 uint8 csa_high; /* code storage area, MSB */ 203 uint8 csa_dat_win; /* data access window to function */ 204 205 uint8 fnx_blk_size[2]; /* block size, little endian */ 206 } sdio_fbr_t; 207 208 /* Maximum number of I/O funcs */ 209 #define SDIOD_MAX_FUNCS 8 210 #define SDIOD_MAX_IOFUNCS 7 211 212 /* SDIO Device FBR Start Address */ 213 #define SDIOD_FBR_STARTADDR 0x100 214 215 /* SDIO Device FBR Size */ 216 #define SDIOD_FBR_SIZE 0x100 217 218 /* Macro to calculate FBR register base */ 219 #define SDIOD_FBR_BASE(n) ((n) * 0x100) 220 221 /* Function register offsets */ 222 #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */ 223 #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */ 224 #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */ 225 226 /* SDIO Function CIS ptr offset */ 227 #define SDIOD_FBR_CISPTR_0 0x09 228 #define SDIOD_FBR_CISPTR_1 0x0A 229 #define SDIOD_FBR_CISPTR_2 0x0B 230 231 /* Code Storage Area pointer */ 232 #define SDIOD_FBR_CSA_ADDR_0 0x0C 233 #define SDIOD_FBR_CSA_ADDR_1 0x0D 234 #define SDIOD_FBR_CSA_ADDR_2 0x0E 235 #define SDIOD_FBR_CSA_DATA 0x0F 236 237 /* SDIO Function I/O Block Size */ 238 #define SDIOD_FBR_BLKSIZE_0 0x10 239 #define SDIOD_FBR_BLKSIZE_1 0x11 240 241 /* devctr */ 242 #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */ 243 #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */ 244 #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */ 245 /* interface codes */ 246 #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */ 247 #define SDIOD_DIC_UART 1 248 #define SDIOD_DIC_BLUETOOTH_A 2 249 #define SDIOD_DIC_BLUETOOTH_B 3 250 #define SDIOD_DIC_GPS 4 251 #define SDIOD_DIC_CAMERA 5 252 #define SDIOD_DIC_PHS 6 253 #define SDIOD_DIC_WLAN 7 254 #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */ 255 256 /* pwr_sel */ 257 #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */ 258 #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */ 259 260 /* misc defines */ 261 #define SDIO_FUNC_0 0 262 #define SDIO_FUNC_1 1 263 #define SDIO_FUNC_2 2 264 #define SDIO_FUNC_4 4 265 #define SDIO_FUNC_5 5 266 #define SDIO_FUNC_6 6 267 #define SDIO_FUNC_7 7 268 269 #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */ 270 #define SD_CARD_TYPE_IO 1 /* IO only card */ 271 #define SD_CARD_TYPE_MEMORY 2 /* memory only card */ 272 #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */ 273 274 #define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */ 275 #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */ 276 277 /* Card registers: status bit position */ 278 #define CARDREG_STATUS_BIT_OUTOFRANGE 31 279 #define CARDREG_STATUS_BIT_COMCRCERROR 23 280 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22 281 #define CARDREG_STATUS_BIT_ERROR 19 282 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12 283 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11 284 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10 285 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9 286 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4 287 288 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ 289 #define SD_CMD_SEND_OPCOND 1 290 #define SD_CMD_MMC_SET_RCA 3 291 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ 292 #define SD_CMD_SELECT_DESELECT_CARD 7 293 #define SD_CMD_SEND_CSD 9 294 #define SD_CMD_SEND_CID 10 295 #define SD_CMD_STOP_TRANSMISSION 12 296 #define SD_CMD_SEND_STATUS 13 297 #define SD_CMD_GO_INACTIVE_STATE 15 298 #define SD_CMD_SET_BLOCKLEN 16 299 #define SD_CMD_READ_SINGLE_BLOCK 17 300 #define SD_CMD_READ_MULTIPLE_BLOCK 18 301 #define SD_CMD_WRITE_BLOCK 24 302 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25 303 #define SD_CMD_PROGRAM_CSD 27 304 #define SD_CMD_SET_WRITE_PROT 28 305 #define SD_CMD_CLR_WRITE_PROT 29 306 #define SD_CMD_SEND_WRITE_PROT 30 307 #define SD_CMD_ERASE_WR_BLK_START 32 308 #define SD_CMD_ERASE_WR_BLK_END 33 309 #define SD_CMD_ERASE 38 310 #define SD_CMD_LOCK_UNLOCK 42 311 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ 312 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ 313 #define SD_CMD_APP_CMD 55 314 #define SD_CMD_GEN_CMD 56 315 #define SD_CMD_READ_OCR 58 316 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ 317 #define SD_ACMD_SD_STATUS 13 318 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22 319 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 320 #define SD_ACMD_SD_SEND_OP_COND 41 321 #define SD_ACMD_SET_CLR_CARD_DETECT 42 322 #define SD_ACMD_SEND_SCR 51 323 324 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ 325 #define SD_IO_OP_READ 0 /* Read_Write: Read */ 326 #define SD_IO_OP_WRITE 1 /* Read_Write: Write */ 327 #define SD_IO_RW_NORMAL 0 /* no RAW */ 328 #define SD_IO_RW_RAW 1 /* RAW */ 329 #define SD_IO_BYTE_MODE 0 /* Byte Mode */ 330 #define SD_IO_BLOCK_MODE 1 /* BlockMode */ 331 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */ 332 #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */ 333 334 /* build SD_CMD_IO_RW_DIRECT Argument */ 335 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \ 336 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \ 337 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF)) 338 339 /* build SD_CMD_IO_RW_EXTENDED Argument */ 340 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \ 341 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \ 342 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF)) 343 344 /* SDIO response parameters */ 345 #define SD_RSP_NO_NONE 0 346 #define SD_RSP_NO_1 1 347 #define SD_RSP_NO_2 2 348 #define SD_RSP_NO_3 3 349 #define SD_RSP_NO_4 4 350 #define SD_RSP_NO_5 5 351 #define SD_RSP_NO_6 6 352 353 /* Modified R6 response (to CMD3) */ 354 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000 355 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 356 #define SD_RSP_MR6_ERROR 0x2000 357 358 /* Modified R1 in R4 Response (to CMD5) */ 359 #define SD_RSP_MR1_SBIT 0x80 360 #define SD_RSP_MR1_PARAMETER_ERROR 0x40 361 #define SD_RSP_MR1_RFU5 0x20 362 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 363 #define SD_RSP_MR1_COM_CRC_ERROR 0x08 364 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04 365 #define SD_RSP_MR1_RFU1 0x02 366 #define SD_RSP_MR1_IDLE_STATE 0x01 367 368 /* R5 response (to CMD52 and CMD53) */ 369 #define SD_RSP_R5_COM_CRC_ERROR 0x80 370 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40 371 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20 372 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10 373 #define SD_RSP_R5_ERROR 0x08 374 #define SD_RSP_R5_RFU 0x04 375 #define SD_RSP_R5_FUNC_NUM_ERROR 0x02 376 #define SD_RSP_R5_OUT_OF_RANGE 0x01 377 378 #define SD_RSP_R5_ERRBITS 0xCB 379 380 /* ------------------------------------------------ 381 * SDIO Commands and responses 382 * 383 * I/O only commands are: 384 * CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53 385 * ------------------------------------------------ 386 */ 387 388 /* SDIO Commands */ 389 #define SDIOH_CMD_0 0 390 #define SDIOH_CMD_3 3 391 #define SDIOH_CMD_5 5 392 #define SDIOH_CMD_7 7 393 #define SDIOH_CMD_11 11 394 #define SDIOH_CMD_14 14 395 #define SDIOH_CMD_15 15 396 #define SDIOH_CMD_19 19 397 #define SDIOH_CMD_52 52 398 #define SDIOH_CMD_53 53 399 #define SDIOH_CMD_59 59 400 401 /* SDIO Command Responses */ 402 #define SDIOH_RSP_NONE 0 403 #define SDIOH_RSP_R1 1 404 #define SDIOH_RSP_R2 2 405 #define SDIOH_RSP_R3 3 406 #define SDIOH_RSP_R4 4 407 #define SDIOH_RSP_R5 5 408 #define SDIOH_RSP_R6 6 409 410 /* 411 * SDIO Response Error flags 412 */ 413 #define SDIOH_RSP5_ERROR_FLAGS 0xCB 414 415 /* ------------------------------------------------ 416 * SDIO Command structures. I/O only commands are: 417 * 418 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 419 * ------------------------------------------------ 420 */ 421 422 #define CMD5_OCR_M BITFIELD_MASK(24) 423 #define CMD5_OCR_S 0 424 425 #define CMD5_S18R_M BITFIELD_MASK(1) 426 #define CMD5_S18R_S 24 427 428 #define CMD7_RCA_M BITFIELD_MASK(16) 429 #define CMD7_RCA_S 16 430 431 #define CMD14_RCA_M BITFIELD_MASK(16) 432 #define CMD14_RCA_S 16 433 #define CMD14_SLEEP_M BITFIELD_MASK(1) 434 #define CMD14_SLEEP_S 15 435 436 #define CMD_15_RCA_M BITFIELD_MASK(16) 437 #define CMD_15_RCA_S 16 438 439 #define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52 440 */ 441 #define CMD52_DATA_S 0 442 #define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 443 #define CMD52_REG_ADDR_S 9 444 #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */ 445 #define CMD52_RAW_S 27 446 #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 447 #define CMD52_FUNCTION_S 28 448 #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 449 #define CMD52_RW_FLAG_S 31 450 451 #define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */ 452 #define CMD53_BYTE_BLK_CNT_S 0 453 #define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 454 #define CMD53_REG_ADDR_S 9 455 #define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */ 456 #define CMD53_OP_CODE_S 26 457 #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */ 458 #define CMD53_BLK_MODE_S 27 459 #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 460 #define CMD53_FUNCTION_S 28 461 #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 462 #define CMD53_RW_FLAG_S 31 463 464 /* ------------------------------------------------------ 465 * SDIO Command Response structures for SD1 and SD4 modes 466 * ----------------------------------------------------- 467 */ 468 #define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */ 469 #define RSP4_IO_OCR_S 0 470 471 #define RSP4_S18A_M BITFIELD_MASK(1) /* Bits [23:0] - Card's OCR Bits [23:0] */ 472 #define RSP4_S18A_S 24 473 474 #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */ 475 #define RSP4_STUFF_S 24 476 #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */ 477 #define RSP4_MEM_PRESENT_S 27 478 #define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */ 479 #define RSP4_NUM_FUNCS_S 28 480 #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */ 481 #define RSP4_CARD_READY_S 31 482 483 #define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0] 484 */ 485 #define RSP6_STATUS_S 0 486 #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */ 487 #define RSP6_IO_RCA_S 16 488 489 #define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */ 490 #define RSP1_AKE_SEQ_ERROR_S 3 491 #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 492 #define RSP1_APP_CMD_S 5 493 #define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */ 494 #define RSP1_READY_FOR_DATA_S 8 495 #define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card 496 * when Cmd was received 497 */ 498 #define RSP1_CURR_STATE_S 9 499 #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */ 500 #define RSP1_EARSE_RESET_S 13 501 #define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */ 502 #define RSP1_CARD_ECC_DISABLE_S 14 503 #define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */ 504 #define RSP1_WP_ERASE_SKIP_S 15 505 #define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits 506 * of CSD 507 */ 508 #define RSP1_CID_CSD_OVERW_S 16 509 #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */ 510 #define RSP1_ERROR_S 19 511 #define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */ 512 #define RSP1_CC_ERROR_S 20 513 #define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed 514 * to correct data 515 */ 516 #define RSP1_CARD_ECC_FAILED_S 21 517 #define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */ 518 #define RSP1_ILLEGAL_CMD_S 22 519 #define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed 520 */ 521 #define RSP1_COM_CRC_ERROR_S 23 522 #define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */ 523 #define RSP1_LOCK_UNLOCK_FAIL_S 24 524 #define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */ 525 #define RSP1_CARD_LOCKED_S 25 526 #define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program 527 * write-protected blocks 528 */ 529 #define RSP1_WP_VIOLATION_S 26 530 #define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */ 531 #define RSP1_ERASE_PARAM_S 27 532 #define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */ 533 #define RSP1_ERASE_SEQ_ERR_S 28 534 #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */ 535 #define RSP1_BLK_LEN_ERR_S 29 536 #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */ 537 #define RSP1_ADDR_ERR_S 30 538 #define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */ 539 #define RSP1_OUT_OF_RANGE_S 31 540 541 #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */ 542 #define RSP5_DATA_S 0 543 #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */ 544 #define RSP5_FLAGS_S 8 545 #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */ 546 #define RSP5_STUFF_S 16 547 548 /* ---------------------------------------------- 549 * SDIO Command Response structures for SPI mode 550 * ---------------------------------------------- 551 */ 552 #define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */ 553 #define SPIRSP4_IO_OCR_S 0 554 #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */ 555 #define SPIRSP4_STUFF_S 16 556 #define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */ 557 #define SPIRSP4_MEM_PRESENT_S 19 558 #define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */ 559 #define SPIRSP4_NUM_FUNCS_S 20 560 #define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */ 561 #define SPIRSP4_CARD_READY_S 23 562 #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */ 563 #define SPIRSP4_IDLE_STATE_S 24 564 #define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 565 #define SPIRSP4_ILLEGAL_CMD_S 26 566 #define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 567 #define SPIRSP4_COM_CRC_ERROR_S 27 568 #define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 569 */ 570 #define SPIRSP4_FUNC_NUM_ERROR_S 28 571 #define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 572 #define SPIRSP4_PARAM_ERROR_S 30 573 #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 574 #define SPIRSP4_START_BIT_S 31 575 576 #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */ 577 #define SPIRSP5_DATA_S 16 578 #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */ 579 #define SPIRSP5_IDLE_STATE_S 24 580 #define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 581 #define SPIRSP5_ILLEGAL_CMD_S 26 582 #define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 583 #define SPIRSP5_COM_CRC_ERROR_S 27 584 #define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 585 */ 586 #define SPIRSP5_FUNC_NUM_ERROR_S 28 587 #define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 588 #define SPIRSP5_PARAM_ERROR_S 30 589 #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 590 #define SPIRSP5_START_BIT_S 31 591 592 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */ 593 #define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error 594 */ 595 #define RSP6STAT_AKE_SEQ_ERROR_S 3 596 #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 597 #define RSP6STAT_APP_CMD_S 5 598 #define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data 599 * (buff empty) 600 */ 601 #define RSP6STAT_READY_FOR_DATA_S 8 602 #define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at 603 * Cmd reception 604 */ 605 #define RSP6STAT_CURR_STATE_S 9 606 #define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19 607 */ 608 #define RSP6STAT_ERROR_S 13 609 #define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for 610 * card state Bit 22 611 */ 612 #define RSP6STAT_ILLEGAL_CMD_S 14 613 #define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command 614 * failed Bit 23 615 */ 616 #define RSP6STAT_COM_CRC_ERROR_S 15 617 618 #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ 619 #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE 620 621 /* command issue options */ 622 #define CMD_OPTION_DEFAULT 0 623 #define CMD_OPTION_TUNING 1 624 625 #endif /* def BCMSDIO */ 626 #endif /* _SDIO_H */ 627