1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides V154 adc register \n 16 * 17 * History: \n 18 * 2024-02-01， Create file. \n 19 */ 20 21 #ifndef HAL_ADC_V154_REGS_DEF_H 22 #define HAL_ADC_V154_REGS_DEF_H 23 24 #include <stdint.h> 25 26 #ifdef __cplusplus 27 #if __cplusplus 28 extern "C" { 29 #endif /* __cplusplus */ 30 #endif /* __cplusplus */ 31 32 typedef struct adc_regs { 33 volatile uint32_t lsadc_ctrl_0; 34 volatile uint32_t lsadc_ctrl_1; 35 volatile uint32_t lsadc_ctrl_2; 36 volatile uint32_t lsadc_ctrl_3; 37 volatile uint32_t lsadc_ctrl_4; 38 volatile uint32_t lsadc_ctrl_6; 39 volatile uint32_t lsadc_ctrl_7; 40 volatile uint32_t lsadc_ctrl_8; 41 volatile uint32_t lsadc_ctrl_9; 42 volatile uint32_t lsadc_ctrl_11; 43 volatile uint32_t lsadc_ctrl_12; 44 45 volatile uint32_t cfg_adc_offset_cali; 46 volatile uint32_t cfg_adc_offset_cali_en; 47 volatile uint32_t cfg_adc_offset_cali_data_en; 48 volatile uint32_t cfg_adc_offset_cali_data_spi_refresh; 49 volatile uint32_t cfg_adc_offset_cali_state_clr; 50 volatile uint32_t rpt_adc_offset_cali_zero_num; 51 volatile uint32_t rpt_adc_offset_cali_finish_sts; 52 volatile uint32_t rpt_adc_offset_cali_sts; 53 volatile uint32_t rpt_adc_offset_cali_curr_st; 54 volatile uint32_t rpt_adc_offset_cali_data; 55 56 volatile uint32_t cfg_cap_cali_wac1_spi; 57 volatile uint32_t cfg_cap_cali_wac2_spi; 58 volatile uint32_t cfg_cap_cali_wac3_spi; 59 volatile uint32_t cfg_cap_cali_wac4_spi; 60 volatile uint32_t cfg_cap_cali_wac5_spi; 61 volatile uint32_t cfg_cap_cali_wac6_spi; 62 volatile uint32_t cfg_cap_cali_wac7_spi; 63 volatile uint32_t cfg_cap_cali_wac8_spi; 64 volatile uint32_t cfg_cap_cali_wac9_spi; 65 volatile uint32_t cfg_cap_cali_wac10_spi; 66 volatile uint32_t cfg_cap_cali_wac11_spi; 67 volatile uint32_t rpt_intr_gain_cali_gain; 68 volatile uint32_t rpt_gain_dataout_31b; 69 70 volatile uint32_t cfg_adc_cap_cali; 71 volatile uint32_t cfg_adc_cap_cali_en; 72 volatile uint32_t cfg_gain_cali_en; 73 volatile uint32_t cfg_cap_cali_data_spi_refresh; 74 volatile uint32_t cfg_cap_cali_finish_clr; 75 volatile uint32_t cfg_intr_gain_state_clr; 76 volatile uint32_t rpt_cap_cali_sts_0; 77 volatile uint32_t rpt_cap_cali_sts_1; 78 79 volatile uint32_t rpt_cap_cali_wt_1; 80 volatile uint32_t rpt_cap_cali_wt_2; 81 volatile uint32_t rpt_cap_cali_wt_3; 82 volatile uint32_t rpt_cap_cali_wt_4; 83 volatile uint32_t rpt_cap_cali_wt_5; 84 volatile uint32_t rpt_cap_cali_wt_6; 85 volatile uint32_t rpt_cap_cali_wt_7; 86 volatile uint32_t rpt_cap_cali_wt_8; 87 volatile uint32_t rpt_cap_cali_wt_9; 88 volatile uint32_t rpt_cap_cali_wt_10; 89 volatile uint32_t rpt_cap_cali_wt_11; 90 volatile uint32_t rpt_cap_cali_curr_st; 91 92 volatile uint32_t cfg_ctc_filter_bybass; 93 volatile uint32_t cfg_data_sel; 94 volatile uint32_t cfg_offset; 95 volatile uint32_t cfg_gain; 96 volatile uint32_t cfg_cic_filter_en; 97 volatile uint32_t cfg_cic_osr; 98 volatile uint32_t cfg_cic_trigger_rst; 99 100 volatile uint32_t da_lsadc_rwreg_1; 101 volatile uint32_t da_lsadc_rwreg_2; 102 volatile uint32_t da_lsadc_rwreg_3; 103 volatile uint32_t da_lsadc_rwreg_4; 104 } adc_regs_t; 105 106 typedef struct cldo_crg_cfg { 107 volatile uint32_t cldo_crg_rst_soft_cfg_0; 108 volatile uint32_t cldo_crg_rst_soft_cfg_1; 109 } cldo_crg_cfg_t; 110 111 typedef union cldo_rst_soft_ctl { 112 uint32_t d32; 113 struct { 114 uint32_t soft_rst_gpio_n : 1; 115 uint32_t soft_rst_tglp_n : 1; 116 uint32_t soft_rst_bsub_n : 1; 117 uint32_t soft_rst_crg_bsub_n : 1; 118 uint32_t soft_rst_wifi_n : 1; 119 uint32_t soft_rst_lsadc_n : 1; 120 uint32_t soft_rst_tcxo_cnt_n : 1; 121 uint32_t soft_rst_lsadc_bus_n : 1; 122 uint32_t soft_rst_wcpu_mem_ctl_n : 1; 123 uint32_t reserved : 23; 124 } b; 125 } cldo_rst_soft_ctl_t; 126 127 typedef union adc_irg_data { 128 uint32_t d32; 129 struct { 130 uint32_t rorim : 1; 131 uint32_t rxim : 1; 132 uint32_t rormis : 1; 133 uint32_t rxmis : 1; 134 uint32_t rorris : 1; 135 uint32_t rxris : 1; 136 uint32_t reserved : 26; 137 } b; 138 } adc_irg_data_t; 139 140 typedef union adc_fifo_data { 141 uint32_t d32; 142 struct { 143 uint32_t rxintsize : 3; 144 uint32_t rne : 1; 145 uint32_t rff : 1; 146 uint32_t bsy : 1; 147 uint32_t reserved : 26; 148 } b; 149 } adc_fifo_data_t; 150 151 typedef union adc_channel_data { 152 uint32_t d32; 153 struct { 154 uint32_t channel_0 : 1; 155 uint32_t channel_1 : 1; 156 uint32_t channel_2 : 1; 157 uint32_t channel_3 : 1; 158 uint32_t channel_4 : 1; 159 uint32_t channel_5 : 1; 160 uint32_t reserved : 26; 161 } b; 162 } adc_channel_data_t; 163 164 typedef union adc_ctrl_data { 165 uint32_t d32; 166 struct { 167 uint32_t channel : 6; 168 uint32_t equ_model_sel : 2; 169 uint32_t sample_cnt : 5; 170 uint32_t satrt_cnt : 8; 171 uint32_t cast_cnt : 7; 172 uint32_t reserved : 4; 173 } b; 174 } adc_ctrl_data_t; 175 176 typedef enum { 177 ADC_CHANNEL_A = 0, 178 ADC_CHANNEL_B, 179 ADC_CHANNEL_C, 180 ADC_CHANNEL_D, 181 ADC_CHANNEL_E, 182 ADC_CHANNEL_F, 183 ADC_SCAN_MODE_MAX_NUM 184 } hal_adc_channel_t; 185 186 typedef union adc_fifo_read_data { 187 uint32_t d32; 188 struct { 189 uint32_t data : 17; 190 uint32_t reserved : 15; 191 } b; 192 } adc_fifo_read_data_t; 193 194 typedef union adc_fifo_data_str { 195 uint32_t d32; 196 struct { 197 uint32_t data : 14; 198 uint32_t channel : 3; 199 uint32_t reserved : 15; 200 } b; 201 } adc_fifo_data_str_t; 202 203 typedef union adc_enable_data { 204 uint32_t d32; 205 struct { 206 uint32_t da_lsadc_en : 16; 207 uint32_t da_lsadc_rstn : 1; 208 uint32_t reserved : 15; 209 } b; 210 } adc_enable_data_t; 211 212 typedef union adc_offset_cali_state_clr_data { 213 uint32_t d32; 214 struct { 215 uint32_t offset_cali_finish_clr : 1; 216 uint32_t reserved : 31; 217 } b; 218 } adc_offset_cali_state_clr_data_t; 219 220 typedef union adc_offset_cali_spi_refresh_data { 221 uint32_t d32; 222 struct { 223 uint32_t offset_cali_spi_refresh : 1; 224 uint32_t reserved : 31; 225 } b; 226 } adc_offset_cali_spi_refresh_data_t; 227 228 typedef union adc_offset_cali_data { 229 uint32_t d32; 230 struct { 231 uint32_t offset_cali_mode : 1; 232 uint32_t offset_cali_loop_sel : 1; 233 uint32_t offset_cali_inverse : 1; 234 uint32_t reserved1 : 1; 235 uint32_t offset_cali_acc_cycle_sel : 2; 236 uint32_t offset_cali_range_sel : 2; 237 uint32_t offset_cali_data_spi : 6; 238 uint32_t reserved2 : 2; 239 uint32_t offset_cali_adc_data_inv : 1; 240 uint32_t reserved : 15; 241 } b; 242 } adc_offset_cali_data_t; 243 244 typedef union adc_offset_cali_en_data { 245 uint32_t d32; 246 struct { 247 uint32_t offset_cali_en : 1; 248 uint32_t reserved : 31; 249 } b; 250 } adc_offset_cali_en_data_t; 251 252 typedef union adc_offset_cali_sts_data { 253 uint32_t d32; 254 struct { 255 uint32_t offset_cali_finish : 1; 256 uint32_t reserved : 31; 257 } b; 258 } adc_offset_cali_sts_data_t; 259 260 typedef union adc_rpt_offset_cali_data { 261 uint32_t d32; 262 struct { 263 uint32_t offset_cali_data : 6; 264 uint32_t offset_cali_loop_cnt : 6; 265 uint32_t reserved : 20; 266 } b; 267 } adc_rpt_offset_cali_data_t; 268 269 typedef union adc_cfg_offset_cali_en_data { 270 uint32_t d32; 271 struct { 272 uint32_t offset_data_en : 1; 273 uint32_t reserved : 31; 274 } b; 275 } adc_cfg_offset_cali_en_data_t; 276 277 typedef union cfg_cap_cali_finish_clr_data { 278 uint32_t d32; 279 struct { 280 uint32_t finish_clr : 1; 281 uint32_t reserved : 31; 282 } b; 283 } cfg_cap_cali_finish_clr_data_t; 284 285 typedef union cfg_intr_gain_state_clr_data { 286 uint32_t d32; 287 struct { 288 uint32_t gain_state_clr : 1; 289 uint32_t reserved : 31; 290 } b; 291 } cfg_intr_gain_state_clr_data_t; 292 293 typedef union cfg_cap_cali_data_spi_refresh_data { 294 uint32_t d32; 295 struct { 296 uint32_t spi_refresh : 1; 297 uint32_t reserved : 31; 298 } b; 299 } cfg_cap_cali_data_spi_refresh_data_t; 300 301 typedef union cfg_adc_cap_cali_data { 302 uint32_t d32; 303 struct { 304 uint32_t mode : 1; 305 uint32_t alg_sel : 1; 306 uint32_t acc_cycle_sel : 2; 307 uint32_t start_index : 4; 308 uint32_t weight_sel : 1; 309 uint32_t dac_setting_dly_ctrl : 1; 310 uint32_t reserved1 : 2; 311 uint32_t cap_selman : 4; 312 uint32_t sh_en_man : 1; 313 uint32_t pn_sel_man : 1; 314 uint32_t reserved2 : 14; 315 } b; 316 } cfg_adc_cap_cali_data_t; 317 318 typedef union cfg_adc_cap_cali_en_data { 319 uint32_t d32; 320 struct { 321 uint32_t en : 1; 322 uint32_t reserved : 31; 323 } b; 324 } cfg_adc_cap_cali_en_data_t; 325 326 typedef union rpt_cap_cali_sts0_data { 327 uint32_t d32; 328 struct { 329 uint32_t finish : 1; 330 uint32_t reserved1 : 7; 331 uint32_t error : 1; 332 uint32_t reserved2 : 23; 333 } b; 334 } rpt_cap_cali_sts0_data_t; 335 336 typedef union cfg_gain_cali_en_data { 337 uint32_t d32; 338 struct { 339 uint32_t en : 1; 340 uint32_t reserved : 31; 341 } b; 342 } cfg_gain_cali_en_data_t; 343 344 typedef union rpt_intr_gain_cali_gain_data { 345 uint32_t d32; 346 struct { 347 uint32_t intr_gain : 19; 348 uint32_t reserved : 1; 349 uint32_t intr_gain_uint : 12; 350 } b; 351 } rpt_intr_gain_cali_gain_data_t; 352 353 typedef union adc_scan_start_and_stop_data { 354 uint32_t d32; 355 struct { 356 uint32_t lsadc_start : 1; 357 uint32_t lsadc_stop : 1; 358 uint32_t reserved : 30; 359 } b; 360 } adc_scan_start_and_stop_data_t; 361 362 errcode_t hal_adc_v154_regs_init(void); 363 364 365 #ifdef __cplusplus 366 #if __cplusplus 367 } 368 #endif /* __cplusplus */ 369 #endif /* __cplusplus */ 370 371 #endif