| /arkcompiler/ets_runtime/ecmascript/compiler/assembler/x64/ |
| D | macro_assembler_x64.cpp | 24 x64::Register baseReg = (dstStackSlot.IsFrameBase()) ? x64::rbp : x64::rsp; in Move() local
43 x64::Register baseReg = (stackSlot.IsFrameBase()) ? x64::rbp : x64::rsp; in Cmp() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/assembler/ |
| D | macro_assembler.h | 42 StackSlotOperand(BaseRegister baseReg, int32_t stackOffset) in StackSlotOperand()
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| /arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/ |
| D | macro_assembler_aarch64.cpp | 38 aarch64::Register baseReg = (dstStackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in Move() local
60 aarch64::Register baseReg = (stackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in Cmp() local
106 aarch64::Register baseReg = (dstStackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in SaveReturnRegister() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/ |
| D | aarch64_obj_emitter.cpp | 1171 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadStoreRegInsn() local
1223 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadStoreARInsn() local
1237 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadExclusiveInsn() local
1253 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadExclusivePairInsn() local
1269 Operand *baseReg = memOpnd.GetBaseRegister(); in GenStoreExclusiveInsn() local
1287 Operand *baseReg = memOpnd.GetBaseRegister(); in GenStoreExclusivePairInsn() local
1303 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadPairInsn() local
1340 Operand *baseReg = memOpnd.GetBaseRegister(); in GenStorePairInsn() local
1382 Operand *baseReg = memOpnd.GetBaseRegister(); in GenLoadPairFloatInsn() local
1419 Operand *baseReg = memOpnd.GetBaseRegister(); in GenStorePairFloatInsn() local
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| D | aarch64_insn.cpp | 126 auto *baseReg = v->GetBaseRegister(); in Visit() local
183 auto *baseReg = v->GetBaseRegister(); in Visit() local
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| D | aarch64_cgfunc.cpp | 558 MemOperand &AArch64CGFunc::CreateReplacementMemOperand(uint32 bitLen, RegOperand &baseReg, int64 of… in CreateReplacementMemOperand()
3978 auto *baseReg = SelectRegread(*static_cast<RegreadNode *>(baseExpr)); in CheckAndCreateExtendMemOpnd() local
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| /arkcompiler/ets_frontend/es2panda/ir/base/ |
| D | classDefinition.cpp | 107 compiler::VReg baseReg = pg->AllocReg(); in CompileHeritageClause() local
394 compiler::VReg baseReg = CompileHeritageClause(pg); in Compile() local
683 compiler::VReg baseReg = CompileHeritageClause(pg); in CompileSendableClass() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/ |
| D | x64_proepilog.cpp | 36 RegOperand &baseReg = cgFunc.GetOpndBuilder()->CreatePReg(x64::RBP, k64BitSize, kRegTyInt); in GenerateCalleeSavedRegs() local
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| D | x64_MPIsel.cpp | 530 …RegOperand &baseReg = cgFunc->GetOpndBuilder()->CreatePReg(x64::RBP, GetPrimTypeBitSize(PTY_i64), … in SelectRangeGoto() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/ |
| D | operand.cpp | 164 RegOperand *baseReg = GetBaseRegister(); in Less() local
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| D | reg_alloc_lsra.cpp | 1018 uint32 baseReg = isInt ? firstIntReg : firstFpReg; in UpdateParamAllocateInfo() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/ |
| D | encode.cpp | 235 auto baseReg = VixlReg(mem.GetBase()); in ConvertMem() local
850 auto baseReg = VixlReg(mem.GetBase()); in PrepareMemLdS() local
923 auto baseReg = VixlReg(mem.GetBase()); in PrepareMemLdSForFloat() local
3199 vixl::aarch32::Register baseReg = VixlReg(base); in LoadStoreRegistersMainLoop() local
3226 vixl::aarch32::Register baseReg = VixlReg(base); in LoadStoreRegisters() local
3256 …h32Encoder::ConstructAddForBigOffset(vixl::aarch32::Register tmp, vixl::aarch32::Register *baseReg, in ConstructAddForBigOffset()
3286 vixl::aarch32::Register baseReg = vixl::aarch32::sp; in LoadStoreRegisters() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/ |
| D | encode.cpp | 142 auto baseReg = Reg(mem.GetBase().GetId(), INT64_TYPE); in ConvertMem() local
2283 [[maybe_unused]] auto baseReg = mem.GetBase(); in EncodeLdr() local
2341 [[maybe_unused]] auto baseReg = mem.GetBase(); in EncodeLdrAcquireInvalid() local
2419 auto baseReg = mem.GetBase(); in CheckAlignment() local
3343 auto baseReg = VixlReg(base); in LoadStorePair() local
3355 auto baseReg = VixlReg(base); in LoadStoreReg() local
3444 const vixl::aarch64::Register &baseReg) in LoadStoreRegistersLoop()
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| /arkcompiler/ets_frontend/ets2panda/compiler/core/ |
| D | JSCompiler.cpp | 51 compiler::VReg baseReg = pg->AllocReg(); in CompileHeritageClause() local
398 compiler::VReg baseReg = CompileHeritageClause(pg, node); in Compile() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/ |
| D | codegen.cpp | 2857 void PostWriteBarrier::EncodeCalculateCardIndex(Reg baseReg, ScopedTmpReg *tmp, ScopedTmpReg *tmp1) in EncodeCalculateCardIndex()
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/amd64/ |
| D | encode.cpp | 3187 auto baseReg = ArchReg(base); in LoadStoreRegisters() local
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| /arkcompiler/runtime_core/static_core/libllvmbackend/lowering/ |
| D | llvm_ir_constructor.cpp | 1841 std::string baseReg = representable ? "sp" : "x16"; in CreateInterpreterReturnRestoreRegs() local
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