1 /**
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 *
15 * Description: Provides tcxo port \n
16 *
17 * History: \n
18 * 2023-09-14， Create file. \n
19 */
20 #include "soc_porting.h"
21 #include "chip_io.h"
22 #include "watchdog_porting.h"
23 #include "tcxo_porting.h"
24 #include "uart_porting.h"
25 #include "tcxo.h"
26
27
28 #define REFCLK_FREQ_STATUS_MASK 0x1
29 #define HW_CTL 0x40000014
get_tcxo_freq(void)30 uint32_t get_tcxo_freq(void)
31 {
32 uint32_t hw_ctl;
33 hw_ctl = readl(HW_CTL);
34 if ((hw_ctl & REFCLK_FREQ_STATUS_MASK) == CLK24M_TCXO) {
35 return CLK24M_TCXO;
36 } else {
37 return CLK40M_TCXO;
38 }
39 }
40
41 #define REQ_24M 24000000
42 #define REQ_40M 40000000
43 #define USEC_PER_SEC 1000000
boot_clock_adapt(void)44 void boot_clock_adapt(void)
45 {
46 if (get_tcxo_freq() == CLK24M_TCXO) {
47 uart_port_set_clock_value(UART_BUS_0, REQ_24M);
48 tcxo_porting_ticks_per_usec_set(REQ_24M / USEC_PER_SEC);
49 watchdog_port_set_clock(REQ_24M);
50 } else {
51 uart_port_set_clock_value(UART_BUS_0, REQ_40M);
52 tcxo_porting_ticks_per_usec_set(REQ_40M / USEC_PER_SEC);
53 watchdog_port_set_clock(REQ_40M);
54 }
55 }
56
is_tcxo_24mhz(void)57 bool is_tcxo_24mhz(void)
58 {
59 return (get_tcxo_freq() == CLK24M_TCXO);
60 }
61
62 #define CLDO_CRG_CLK_SEL 0x44001134
63 #define CMU_NEW_CFG1 0x400034A4
64 #define DELAY_1_US 1
65 #define CPU_DIV_FLASH_RSTN_SYNC 0x1
66 #define CPU_DIV_FLASH_RSTN 0x3
switch_flash_clock_to_pll(void)67 void switch_flash_clock_to_pll(void)
68 {
69 writel(CMU_NEW_CFG1, CPU_DIV_FLASH_RSTN_SYNC);
70 uapi_tcxo_delay_us(DELAY_1_US);
71 writel(CMU_NEW_CFG1, CPU_DIV_FLASH_RSTN);
72 reg_setbit(CLDO_CRG_CLK_SEL, 0, POS_18);
73 }
74
75 #define PAD_SFC_CLK_CTRL 0x4400d868
76 #define PAD_SFC_CSN_CTRL 0x4400d86C
77 #define PAD_SFC_IO0_CTRL 0x4400d870
78 #define PAD_SFC_IO1_CTRL 0x4400d874
79 #define PAD_SFC_IO2_CTRL 0x4400d878
80 #define PAD_SFC_IO3_CTRL 0x4400d87C
81 #define SFC_CLK_DS_VALUE 0x3
82 #define SFC_CSN_DS_VALUE 0x2
83 #define SFC_DATA_DS_VALUE 0x2
84 #define DTRL_DS_LEN 0x3
config_sfc_ctrl_ds(void)85 void config_sfc_ctrl_ds(void)
86 {
87 reg_setbits(PAD_SFC_CLK_CTRL, 0, POS_4, DTRL_DS_LEN, SFC_CLK_DS_VALUE);
88 reg_setbits(PAD_SFC_CSN_CTRL, 0, POS_4, DTRL_DS_LEN, SFC_CSN_DS_VALUE);
89 reg_setbits(PAD_SFC_IO0_CTRL, 0, POS_4, DTRL_DS_LEN, SFC_DATA_DS_VALUE);
90 reg_setbits(PAD_SFC_IO1_CTRL, 0, POS_4, DTRL_DS_LEN, SFC_DATA_DS_VALUE);
91 reg_setbits(PAD_SFC_IO2_CTRL, 0, POS_4, DTRL_DS_LEN, SFC_DATA_DS_VALUE);
92 reg_setbits(PAD_SFC_IO3_CTRL, 0, POS_4, DTRL_DS_LEN, SFC_DATA_DS_VALUE);
93 }
94