1 /* 2 * Copyright (c) 2023 Institute of Parallel And Distributed Systems (IPADS), Shanghai Jiao Tong University (SJTU) 3 * Licensed under the Mulan PSL v2. 4 * You can use this software according to the terms and conditions of the Mulan PSL v2. 5 * You may obtain a copy of Mulan PSL v2 at: 6 * http://license.coscl.org.cn/MulanPSL2 7 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR 8 * IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR 9 * PURPOSE. 10 * See the Mulan PSL v2 for more details. 11 */ 12 #ifndef ARCH_AARCH64_ARCH_MACHINE_SMP_H 13 #define ARCH_AARCH64_ARCH_MACHINE_SMP_H 14 15 #ifndef __ASM__ 16 #include <common/vars.h> 17 #include <machine.h> 18 #include <common/types.h> 19 20 enum cpu_state { cpu_hang = 0, cpu_run = 1, cpu_idle = 2 }; 21 #endif 22 23 /* 24 * The offset in the per_cpu struct, i.e., struct per_cpu_info. 25 * The base addr of this struct is stored in TPIDR_EL1 register. 26 * 27 * IMPORTANT: modify the following offset values after 28 * modifying struct per_cpu_info. 29 */ 30 #define OFFSET_CURRENT_EXEC_CTX 0 31 #define OFFSET_LOCAL_CPU_STACK 8 32 #define OFFSET_CURRENT_FPU_OWNER 16 33 #define OFFSET_FPU_DISABLE 24 34 35 #ifndef __ASM__ 36 struct per_cpu_info { 37 /* The execution context of current thread */ 38 u64 cur_exec_ctx; 39 40 /* Per-CPU stack */ 41 char *cpu_stack; 42 43 /* struct thread *fpu_owner */ 44 void *fpu_owner; 45 u32 fpu_disable; 46 47 char pad[pad_to_cache_line(sizeof(u64) + sizeof(char *) + sizeof(void *) 48 + sizeof(u32))]; 49 } __attribute__((packed, aligned(64))); 50 51 extern struct per_cpu_info cpu_info[PLAT_CPU_NUM]; 52 53 extern volatile char cpu_status[PLAT_CPU_NUM]; 54 55 extern u64 ctr_el0; 56 57 void enable_smp_cores(paddr_t boot_flag); 58 void init_per_cpu_info(u32 cpuid); 59 struct per_cpu_info *get_per_cpu_info(void); 60 u32 smp_get_cpu_id(void); 61 u64 smp_get_mpidr(void); 62 void smp_print_status(u32 cpuid); 63 #endif 64 65 #endif /* ARCH_AARCH64_ARCH_MACHINE_SMP_H */